JPH0955085A - Internal power source circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an internal power source circuit which has high capability of controlling the internal power source voltage when the sense amplifier operates. SOLUTION: During the period when the row address strobe signal/RAS is brought into the L level to operate the sense amplifier and the internal source voltage int Vcc decreases greatly, external signals ϕ1 and A become the H level to operate only the circuit 115 which includes a differential amplifier circuit a little low in sensitivity so that the power source circuit does not react too sensitively for the variation of the internal power source voltage int Vcc. After the sense amplifier operates no longer and the internal power source voltage int Vcc is roughly stabilized, the external signal A becomes the L level; the external signal B becomes H level and the circuit 115 which includes the differential amplifier circuit of low sensitivity is switched to a circuit 117 which includes a highly sensitive differential amplifier circuit so that the power source circuit reacts sensitively to the variation of the int Vcc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal power supply circuit, and more particularly to an internal power supply circuit used in a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional internal power supply circuit 1000.
It is a circuit diagram of.

Referring to FIG. 10, a conventional internal power supply circuit 1
000 is an internal power supply node 130, a differential amplifier circuit 100 that operates by comparing a reference voltage serving as a reference of the internal power supply voltage with the internal power supply voltage, and an external power supply voltage in response to the output of the differential amplifier circuit 100. P-channel MOS transistor (hereinafter referred to as PMO
S transistor 110).

Reference voltage Vref and internal power supply voltage intVcc are input to differential amplifier circuit 100. The PMOS transistor 110 has a source electrode connected to an external power supply that supplies an external power supply voltage extVcc,
The drain electrode is connected to the internal power supply that supplies the internal power supply voltage intVcc, and the output of the differential amplifier circuit 100 is applied to the gate electrode.

FIG. 11 shows an internal power supply circuit 1000 of FIG.
3 is a timing chart showing the operation of FIG.

Referring to FIG. 11, the internal power supply circuit 10 of FIG.
00 will be described. Row address strobe signal /
When RAS falls to the L level and the sense amplifier operates, the internal power supply voltage intVcc becomes much lower than the reference voltage Vref which is the reference value of the internal power supply voltage. At this time, the external signal φ1 goes high, and in response to this, the differential amplifier circuit 100 operates. The differential amplifier circuit 100 detects the difference between the reference voltage Vref and the internal power supply voltage intVcc, and its output is PM.
When applied to the gate electrode of the OS transistor 110,
The PMOS transistor 110 is turned on, a voltage is supplied from the external power supply connected to the source electrode thereof to the internal power supply node 130, and the internal power supply voltage intVcc is boosted.

[0007]

However, it takes time to control when the boosted internal power supply voltage intVcc exceeds the reference voltage Vref due to overshoot, and the power supply current is wasted during that period. There was a problem.

The present invention has been made to solve the above problems, and an object thereof is to provide an internal power supply circuit having a high controllability of the internal power supply voltage during the operation of the sense amplifier.

[0009]

An internal power supply circuit according to a first aspect of the present invention has an internal power supply node and first and second drive capacities larger than the first power supply voltage, and based on an external power supply voltage. To supply the internal power supply node to the internal power supply node, and the internal power supply voltage generation means is operated with the first drive capability for a predetermined period after the internal power supply voltage is lowered. And a control means for operating the voltage generation means with the second drive capability.

An internal power supply circuit according to a second aspect of the present invention has an internal power supply node and a first drive capability, and generates an internal power supply voltage based on an external power supply voltage and supplies it to the internal power supply node. A power supply voltage generating means and a second power supply which is larger than the first power supply voltage
And a second internal power supply voltage generating means for generating an internal power supply voltage based on the external power supply voltage and supplying the internal power supply voltage to the internal power supply node; and a first period for a predetermined period after the internal power supply voltage is lowered. A control means for operating the internal power supply voltage generation means and for operating the second internal power supply voltage generation means after a predetermined period has elapsed is provided.

According to another aspect of the present invention, there is provided an internal power supply circuit.
Of the internal power supply circuit, the first internal power supply voltage generating means has the first amplification factor, and the first differential amplifier circuit to which the reference voltage and the internal power supply voltage are input, the external power supply voltage and the internal power supply voltage A first transistor provided between the power supply voltage and the first differential amplifier circuit and turned on / off by the output of the first differential amplifier circuit;
A second differential amplifier circuit having a second amplification factor larger than the first amplification factor and having the reference voltage and the internal power supply voltage inputted to the internal power supply voltage generation means of the external power supply voltage and the internal power supply voltage. And a second transistor which is provided between the second differential amplifier circuit and turned on / off by the output of the second differential amplifier circuit.

According to another aspect of the present invention, there is provided an internal power supply circuit.
In the internal power supply circuit of, the internal power supply voltage generating means is provided with a differential amplifier circuit for detecting a difference between the reference voltage and the internal power supply voltage, and an output of the differential amplifier circuit provided between the external power supply and the internal power supply node. A first transistor for turning on / off is provided, and a differential amplifier circuit is provided with a current source and second and third transistors provided in parallel between the external power source and the current source. .

An internal power supply circuit according to a fifth aspect is the fourth aspect.
In the internal power supply circuit, the current source is provided with fourth and fifth transistors connected to one electrodes of the second and third transistors and turned on / off based on an external signal.

According to another aspect of the present invention, there is provided an internal power supply circuit, an internal power supply node, an internal power supply voltage generating means for generating an internal power supply voltage based on an external power supply voltage and supplying the internal power supply node to the internal power supply node, an external power supply voltage or a ground potential. And an internal power supply voltage correction means for supplying a voltage for correcting the internal power supply voltage generated by the internal power supply voltage generation means to the internal power supply node based on the internal power supply voltage generation means. The first and second transistors that are activated in accordance with the above are provided.

An internal power supply circuit according to a seventh aspect of the present invention has an internal power supply node and a predetermined drive capability, generates an internal power supply voltage based on an external power supply voltage, and supplies the internal power supply voltage to the internal power supply node. The internal power supply voltage generation means and the first and second internal power supply voltage generation means are operated for a predetermined period after the internal power supply voltage is lowered, and after the predetermined period has elapsed, only the first internal power supply voltage generation means is operated. And a control means.

An internal power supply circuit according to an eighth aspect is the seventh aspect.
In the internal power supply circuit, the first and second internal power supply voltage generating means each have a predetermined amplification factor, a differential amplifier circuit to which the reference voltage and the internal power supply voltage are input, an external power supply and an internal power supply circuit. A transistor provided between the power supply node and the power supply node is turned on / off by the output of the differential amplifier circuit.

An internal power supply circuit according to a ninth aspect of the present invention has an internal power supply node and a predetermined drive capability, generates an internal power supply voltage based on an external power supply voltage, and supplies the internal power supply voltage generating means to the internal power supply node. And an internal power supply voltage correcting means for supplying a voltage for correcting the internal power supply voltage to the internal power supply node based on the external power supply voltage, and the internal power supply voltage generating means has a predetermined amplification factor and a reference voltage. ON / OFF by the output of the differential amplifier circuit provided between the external power source and the internal power source node
A second transistor which is provided in parallel with the first transistor between the external power supply and the internal power supply node in the internal power supply voltage correction means and which is activated based on an external signal. And are provided.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 1 is a diagram showing the configuration of an internal power supply circuit 1001 of the present invention.

Referring to FIG. 1, internal power supply circuit 1001
Is an internal step-down circuit 113 and its control logic gate 11
9 is included.

The internal step-down circuit 113 further includes the circuit 11
5,117 are included. The control logic gate 119 further includes a control logic gate 121 for the circuit 115 and a circuit 11.
7 control logic gate 123. The control logic gate 121 for the circuit 115 includes a NAND gate 121a,
The control logic gate 12 for the circuit 117, including an inverter 121b to which the output of the NAND gate 121a is input.
3 is a NAND gate 123a and a NAND gate 123
an inverter 123b to which the output of a is input.

The external signal A is input to one input terminal of the NAND gate 121a, and the external signal φ is input to the other input terminal.
1 is input. External signal B is input to one input terminal of NAND gate 123a, and external signal φ1 is input to the other input terminal.

The output of the inverter 121b is input to the circuit 115, and the output of the inverter 123b is input to the circuit 117 to turn each circuit on or off. Circuit 1
The input terminal of 15 and the input terminal of the circuit 117 are connected to the internal power supply node 130, and the output voltage is supplied to the internal power supply.

FIG. 2 is a circuit diagram of the circuit 115 (, 117) shown in FIG. Referring to FIG. 2, circuit 115 includes a differential amplifier circuit 100 having a slightly reduced sensitivity, and a PMOS transistor 110.

The differential amplifier circuit 100 is connected to an external power supply and has a current mirror circuit 101 composed of PMOS transistors 103 and 104 and a reference voltage Vre.
an N-channel MOS transistor (hereinafter abbreviated as NMOS transistor) 105 to which f is applied to the gate electrode,
Internal power supply voltage intVcc is applied to the gate electrode N
It includes a MOS transistor 106 and an NMOS transistor 107 that turns on the differential amplifier circuit 100 when the external signal φ2 is at the H level.

The output of the differential amplifier circuit 100 is applied to the gate electrode of the PMOS transistor 110, and when the output of the differential amplifier circuit 100 is at the L level, the PMOS transistor 1
10 is turned on and the external power supply voltage extVc is applied from the source electrode.
c is supplied to the internal power supply through the internal power supply node 130 connected to the drain electrode.

The circuit 117 includes a differential amplifier circuit 100 'having a higher sensitivity than the circuit 115 and a PMOS transistor 11.
Including 0 and.

The differential amplifier circuit 100 'has the same structure as the differential amplifier circuit 100 of the circuit 115. However, NM
The OS transistor 107 is turned on when the external signal φ3 is at H level.

The sensitivity of the differential amplifier circuits 100, 100 'is
PMOS transistors 103 and 104, and NMOS
It can be adjusted by changing the sizes of the transistors 105, 106 and 107.

FIG. 3 is a timing chart showing the operation of the internal power supply circuit 1001 shown in FIG.

The internal power supply circuit 1001 of FIG. 1 will be described with reference to FIG.
Will be described. Row address strobe signal / RA
When S goes to L level and the DRAM enters the operating state, external signals φ1 and A go to H level, and the circuit 115 including the differential amplifier circuit 100 whose sensitivity is slightly lowered operates. During a period in which the word line rises, the sense amplifier operates, and the internal power supply voltage intVcc fluctuates greatly, the circuit 115
Internal power supply voltage intVcc
Do not react too sensitively to changes in. When the operation of the sense amplifier is completed and the internal power supply voltage intVcc is stable, the external signal A becomes L level and the external signal B becomes H level, and the circuit 115 including the differential amplifier circuit 100 whose sensitivity is slightly lowered. Is switched to the circuit 117 including the differential amplifier circuit 100 'having a high sensitivity, so that the circuit 117 reacts sensitively to the fluctuation of the internal power supply voltage intVcc.
By controlling internal power supply voltage intVcc in this way, fluctuations in internal power supply voltage intVcc are reduced.

As described above, the internal power supply circuit according to the first embodiment of the present invention operates two circuits each including a differential amplifier circuit having different sensitivities in two stages. It is possible to provide a high internal power supply circuit.

(2) Second Embodiment When the row address strobe signal / RAS goes to L level and the DRAM operates, the word line rises, the sense amplifier operates, and the internal power supply voltage intVcc becomes larger than the reference voltage Vref level. Will fall. Although the internal power supply circuit operates at this time, if the sensitivity of the differential amplifier circuit is too good, the internal power supply voltage intVcc may exceed the reference voltage Vref level and overshoot. In order to prevent this, it is effective to change the current flowing through the differential amplifier circuit included in the internal power supply circuit.

FIG. 4 is a circuit diagram of the internal power supply circuit 1002 of the present invention. Referring to FIG. 4, internal power supply circuit 1002
Is a differential amplifier circuit 200 and a PMOS transistor 21.
Including 0 and.

The differential amplifier circuit 200 is connected to an external power supply and has a current mirror circuit 201 composed of PMOS transistors 203 and 204, an NMOS transistor 205 having a reference voltage Vref applied to its gate electrode, and a gate electrode. The NMOS transistor 206 to which the internal power supply voltage intVcc is applied, the drain electrode of which is the source electrode of the NMOS transistor 205 and the NM
The NMOS transistor 207 is connected to the connection node 403, which is connected to the source electrode of the OS transistor 206, the source electrode is grounded, and the external signal A is applied to the gate electrode, and the drain electrode is connected like the NMOS transistor 207. An NMOS transistor 208 connected to the node 403, having a source electrode grounded and a gate electrode to which the external signal B is applied.

In the PMOS transistor 210, the source electrode is connected to the external power supply, the drain electrode is connected to the internal power supply node 130, and the gate electrode is connected to the differential amplifier circuit 200.
Output is being applied.

When the output of differential amplifier circuit 200 is at L level, PMOS transistor 210 is turned on, and external power supply voltage extVcc is supplied to internal power supply node 130 via internal power supply node 130.

In FIG. 4, when the sense amplifier is operating,
The NMOS transistor 207 is turned on by the external signal A to reduce the current flowing through the differential amplifier circuit 200 and suppress the reaction of the differential amplifier circuit 200 a little. Next, when the internal power supply voltage intVcc is stable after the operation of the sense amplifier, the NMOS transistor 208 is also turned on by the external signal B to increase the current flowing through the differential amplifier circuit 200 to increase the sensitivity of the differential amplifier circuit 200. So that it reacts faster to changes in the internal power supply voltage intVcc.

As described above, the internal power supply circuit according to the second embodiment can control the current flowing through the differential amplifier circuit included in the internal power supply circuit in two stages, so that the degree of reaction of the differential amplifier circuit can be controlled. Can be adjusted, and it is possible to provide an internal power supply circuit having high controllability of the internal power supply voltage.

(3) Third Embodiment FIG. 5 shows an internal power supply circuit 1003 according to a third embodiment of the present invention.
It is a circuit diagram of.

Referring to FIG. 5, internal power supply circuit 1003
Includes a circuit 120 and a circuit 500.

The circuit 500 includes a PMOS transistor 20.
A current mirror circuit 501 composed of 0 and 201;
An NMOS transistor 202 connected between the PMOS transistor 200 and the internal power supply node 130, and an NM
It includes a current mirror circuit 503 composed of OS transistors 204 and 205, and a PMOS transistor 203 connected between the NMOS transistor 204 and the internal power supply node 130. The transistor size of the PMOS transistor 201 is larger than that of the PMOS transistor 200.

Each of the source electrodes of the PMOS transistors 200 and 201 is connected to the external power source, and the drain electrode of the PMOS transistor 200 is connected to the drain electrode of the NMOS transistor 202. The source electrodes of the NMOS transistors 204 and 205 are grounded, and the drain electrode of the NMOS transistor 204 is PM.
It is connected to the drain electrode of the OS transistor 203. Source electrode of NMOS transistor 202 and PMO
The source electrode of the S transistor 203 is connected to the internal power supply node 130. NMOS transistor 202
Substrate is grounded and the reference voltage V is applied to the gate electrode.
ref1 is applied. PMOS transistor 20
The substrate of No. 3 is connected to the external power source, and the reference voltage Vref2 is applied to the gate electrode.

The reference voltage Vref1 is NMOS
The threshold voltage Vthn of the transistor 202 is set to a voltage higher than the internal power supply voltage intVcc. In this case, the PMOS transistors 200, 201,
The current flowing through the NMOS transistor 202 is very small.

In FIG. 5, internal power supply voltage intVcc
Is lower than the reference voltage Vref level, the circuit 120 operates similarly to the conventional internal power supply circuit to change the internal power supply voltage intVcc to the reference voltage Vr.
Restore to ef. At this time, the current mirror circuit 501 including the PMOS transistors 200 and 201 also operates, but this effect is less than that of the circuit 120.

That is, when the internal power supply voltage intVcc becomes lower than the set value, a difference of not more than the threshold voltage Vthn occurs between the internal power supply voltage intVcc and the reference voltage Vref1, and the NMOS transistor 2
02 is turned on. At this time, the current flowing through the NMOS transistor 202 is amplified by the current mirror circuit 503, a voltage is supplied from the external power supply to the internal power supply node 130 via the PMOS transistor 201, and the internal power supply voltage intVcc is boosted.

Internal power supply voltage intVcc is, for example, 3.
When set to 3V, the reference voltage Vref1 becomes
Vref1 = intVcc + Vthn≈3.3 + 0.7
= 4.0V, and the internal power supply voltage intVcc is 3.3.
When the voltage reaches V, the NMOS transistor 202 is turned off, so that the supply of voltage to the internal power supply node 130 is stopped. Therefore, internal power supply voltage intVcc is stabilized at 3.3V.

The reference voltage Vref2 is the PMOS
The threshold voltage Vthp of the transistor 203 is set to be lower than the internal power supply voltage intVcc. In this case, PMOS transistor 203, NMOS
The current flowing through the transistors 204 and 205 is very small. When the internal power supply voltage intVcc is set to 3.3V, for example, the reference voltage Vref2 becomes Vre.
f2 = intVcc- | Vthp | ≈3.3-0.7 =
It is set to 2.6V. When the internal power supply voltage intVcc becomes higher than the set value (3.3V), the internal power supply voltage i
Since there is a difference of not less than the threshold voltage Vthp between ntVcc and the reference voltage Vref2, the PMO
The S transistor 203 is turned on. At this time, P
The current flowing through the MOS transistor 203 is amplified by 203 (the NMOS transistor 205 has a larger transistor size than the NMOS transistor 204), and the internal power supply voltage intVcc is changed to the NMOS transistor 205.
To GND. When the internal power supply voltage intVcc reaches 3.3V, the PMOS transistor 203 is turned off, so that the internal power supply voltage intVcc stabilizes at 3.3V.

As described above, the third embodiment of the present invention
The internal power supply circuit according to is equipped with a circuit that raises the potential when the internal power supply voltage becomes lower than the reference voltage, as well as a circuit that raises the potential when the internal power supply voltage becomes higher than the reference voltage. It is possible to provide an internal power supply circuit having high controllability.

(4) Fourth Embodiment FIG. 6 shows an internal power supply circuit 10 according to a fourth embodiment of the present invention.
It is a figure which shows the structure of 04.

Referring to FIG. 6, internal power supply circuit 1004
Is an internal step-down circuit 613 and its control logic gate 61.
9 is included.

The internal step-down circuit 613 further includes a circuit 61.
5, 617, the control logic gate 619 further includes a control logic gate 621 for the circuit 615 and a circuit 61.
7 control logic gate 623. Circuits 615,6
Reference numeral 17 is a circuit similar to the circuit 115 (, 117) in FIG. However, the differential amplifier circuits included in the circuits 615 and 617 have low sensitivity.

The control logic gate 621 includes a NAND gate 621a and an inverter 621b to which the output of the NAND gate 621a is input.
23 is a NAND gate 623a and a NAND gate 6
An inverter 623b to which the output of 23a is input.

External signal D is input to one input terminal of NAND gate 621a, and external signal φ is input to the other input terminal.
2 is input. External signal E is input to one input terminal of NAND gate 623a, and external signal φ2 is input to the other input terminal.

The output of the inverter 621b is input to the circuit 615 and the output of the inverter 623b is input to the circuit 617 to turn on or off the respective circuits. Circuit 6
15 and the output terminal of the circuit 617 are the internal power supply node 130.
The voltage connected to and is supplied to the internal power supply node 130 to boost the internal power supply voltage intVcc.

FIG. 7 is a timing chart showing the operation of internal power supply circuit 1004 of FIG.

The operation of the internal power supply circuit 1004 of FIG. 6 will be described below with reference to the timing chart of FIG.

Row address strobe signal / RAS is L
The level of the internal power supply voltage intVcc greatly decreases until the operation of the sense amplifier is completed.
During this period, the external signals φ2, D and E are set to H level to operate the two circuits 615 and 617 (first stage). When the levels of the internal power supply voltage intVcc are almost restored to the reference voltage Vref level by the circuits 615 and 617, one circuit, for example, the external signal E is set to the L level to stop the circuit 617 so that the internal power supply voltage intVcc does not rise excessively. (Second stage).

As described above, in the internal power supply circuit 1004 according to the fourth embodiment of the present invention, since the internal voltage down converting circuit operates in the first and second stages as described above, the internal power supply voltage control capability is improved. It becomes possible to provide a high internal power supply circuit.

(5) Fifth Embodiment FIG. 8 shows an internal power supply circuit 1005 according to the fifth embodiment of the present invention.
It is a circuit diagram of.

Referring to FIG. 8, internal power supply circuit 1005
Is a differential amplifier circuit 300 and a PMOS transistor 31.
0, 810 and an internal power supply voltage correction circuit 820.

Differential amplifier circuit 300 and PMOS transistor 310 are similar to differential amplifier circuit 100 and PMOS transistor 110 of FIG. 3, respectively.

Internal power supply voltage correction circuit 820 includes inverters 830 and 840 and a PMOS transistor 850. The external signal A is input to the inverter 830, and the output of the inverter 830 is input to the inverter 840. The output of the inverter 840 is applied to the gate electrode of the PMOS transistor 850.

Next, the operation of this internal power supply circuit 1005 will be described. When the row address strobe signal / RAS goes low and the sense amplifier operates, the internal power supply voltage i
ntVcc drops significantly from the reference voltage Vref level. At this time, as in the first embodiment, the difference between the internal power supply voltage intVcc and the reference voltage Vref is detected by the differential amplifier circuit 300, the PMOS transistor 310 is turned on, and the PMO is turned on.
A voltage is supplied to the internal power supply node 130 from an external power supply connected to the source electrode of the S transistor 310, and the internal power supply voltage intVcc is boosted.

On the other hand, row address strobe signal / RA
When S becomes L level, the external signal A becomes L level,
It is input to the inverter 830. H of the inverter 830
The output of the level becomes the input of the inverter 840, and the output of the L level of the inverter 840 is the PMOS transistor 8
50 is applied to the gate electrode of the PMOS transistor 8
50 is turned on, and P is supplied from the external power source connected to the source electrode.
A voltage is supplied to the source electrode of the MOS transistor 810. The gate electrode of the PMOS transistor 810 has P
As with the MOS transistor 310, the differential amplifier circuit 300
Since the output of is applied, the PMOS transistor 8
10 is in an ON state, a voltage is supplied to internal power supply node 130 via PMOS transistor 810, and internal power supply voltage intVcc is boosted.

As described above, when both the PMOS transistors 310 and 810 operate as drivers of the internal power supply circuit 1005 and the internal power supply voltage intVcc recovers to the reference voltage Vref level, the external signal A becomes L level and the PMOS transistor 850. Turns off, P
The voltage supply to the MOS transistor 810 is stopped to prevent the internal power supply voltage intVcc from exceeding the reference voltage Vref level.

FIG. 9 is a circuit diagram of internal power supply circuit 1005 'according to the fifth embodiment of the present invention.

Referring to FIG. 9, internal power supply circuit 1005 '
Is a differential amplifier circuit 300 and a PMOS transistor 31.
0, 810 and an internal power supply voltage correction circuit 821.

The differential amplifier circuit 300 and the PMOS transistors 310 and 810 are the same differential amplifier circuit and PMOS transistors as in FIG. 8, and the connection relationship is also the same as in FIG.

Internal power supply voltage correction circuit 821 includes an inverter 831 and an NMOS transistor 851.

The external signal A is input to the inverter 831, and the output of the inverter 831 is the NMOS transistor 8
51 is applied to the gate electrode. The source electrode of the NMOS transistor 821 is connected to the external power supply, and the drain electrode is connected to the source electrode of the PMOS transistor 810. The drain electrode of the PMOS transistor 810 is connected to the internal power supply node 130, and the output of the differential amplifier circuit 300 is applied to the gate electrode.

The row address strobe signal / RAS is L
When the level becomes the level and the sense amplifier operates, the internal power supply voltage intVcc drops significantly from the reference voltage Vref level, the difference between the internal power supply voltage intVcc and the reference voltage Vref is detected by the differential amplifier circuit 300, and the PMOS transistor 310 turns on, A voltage is supplied from the external power supply connected to the source electrode of the PMOS transistor 310 to the internal power supply node 130 to boost the internal power supply voltage intVcc.

On the other hand, row address strobe signal / RA
When S becomes L level, the external signal A becomes L level,
It is input to the inverter 831. H of the inverter 831
The level output is applied to the gate electrode of the NMOS transistor, the NMOS transistor 851 is turned on, and the PMOS transistor 8 is supplied from the external power source connected to the source electrode.
A voltage is supplied to the 10 source electrodes. Since the output of the differential amplifier circuit 300 is applied to the gate electrode of the PMOS transistor 810, the PMOS transistor 81
0 is in the ON state, a voltage is supplied to the internal power supply node 130 via the PMOS transistor 810, and the internal power supply voltage intVcc is boosted. Thus, the PMOS
Both of the transistors 310 and 810 are the internal power supply circuit 10.
Operates as a driver of 05 ', internal power supply voltage intV
When cc recovers to the reference voltage Vref level, the external signal A becomes H level, the PMOS transistor 851 is turned off, the voltage supply to the PMOS transistor 810 is stopped, and the internal power supply voltage intVcc may exceed the reference voltage Vref level. To be prevented.

As described above, the fifth embodiment of the present invention
In the internal power supply circuit according to, the two PMOS transistors that operate as drivers of the internal power supply circuit can be activated in two stages and boosted so that the internal power supply voltage does not overshoot. It becomes possible to provide a circuit.

[Brief description of drawings]

FIG. 1 is an internal power supply circuit 1 according to a first embodiment of the present invention.
It is a figure which shows the structure of 001.

FIG. 2 is a circuit diagram of circuits 115 and 117 in FIG.

3 is a timing chart showing the operation of the internal power supply circuit 1000 of FIG.

FIG. 4 is an internal power supply circuit 1 according to a second embodiment of the present invention.
It is a circuit diagram of 002.

FIG. 5 is an internal power supply circuit 1 according to a third embodiment of the present invention.
It is a circuit diagram of 003.

FIG. 6 is an internal power supply circuit 1 according to a fourth embodiment of the present invention.
It is a figure which shows the structure of 004.

7 is a timing chart showing the operation of the internal power supply circuit 1004 of FIG.

FIG. 8 is an internal power supply circuit 1 according to a fifth embodiment of the present invention.
It is a circuit diagram of 005.

FIG. 9 is an internal power supply circuit 1 according to a fifth embodiment of the present invention.
It is a circuit diagram of 005 '.

FIG. 10 is a circuit diagram of a conventional internal power supply circuit 1000.

11 is a timing chart showing an operation of the internal power supply circuit 1000 shown in FIG.

[Explanation of symbols]

100, 200, 300 differential amplifier circuit, 101, 20
1,501,503 Current mirror circuit, 103,10
4,110,203,204,210,310,81
0,850 PMOS transistors, 105,106,
107, 205, 206, 207, 208, 851 N
MOS transistors, 1001, 1002, 1003
1004, 1005, 1005 'Internal power supply circuit, 11
3, 613 internal step-down circuit, 119, 619 control logic gate, 121 circuit 115 control logic gate, 1
23 control logic gate for circuit 117, 621 circuit 6
15 control logic gate, 623 circuit 617 control logic gate, 121a, 123a, 621a, 623a
NAND gates 121b, 123b, 621b, 6
23b, 830, 831, 840 inverter, 11
5,117,120,615,617 Circuit, 130
Internal power supply node, A, B, C, D, E, φ1, φ2, φ
3 External signal, / RAS row address strobe signal, intVcc internal power supply voltage, extVcc external power supply voltage, Vref reference voltage.

Claims (9)

[Claims] 1. An internal power supply circuit for generating an internal power supply voltage based on an external power supply voltage, comprising an internal power supply node, first and second drive capabilities larger than the first power supply voltage, and having an external power supply voltage An internal power supply voltage generating means for generating an internal power supply voltage based on the internal power supply node and supplying the internal power supply voltage to the internal power supply node for a predetermined period after the internal power supply voltage is lowered. An internal power supply circuit comprising: a control unit that operates the internal power supply voltage generation unit with the second drive capability after the predetermined period has elapsed. 2. An internal power supply circuit for generating an internal power supply voltage based on an external power supply voltage, the internal power supply node having a first drive capability, and generating the internal power supply voltage based on the external power supply voltage. First internal power supply voltage generating means for supplying the internal power supply node to the internal power supply node, and a second drive capability larger than the first power supply voltage, and generating an internal power supply voltage based on an external power supply voltage to generate the internal power supply node. Second internal power supply voltage generating means for supplying to the second internal power supply voltage, and the first internal power supply voltage generating means is operated for a predetermined period after the internal power supply voltage is lowered. An internal power supply circuit comprising: a control unit that operates the generation unit. 3. The first internal power supply voltage generating means has a first amplification factor, a first differential amplifier circuit to which a reference voltage and an internal power supply voltage are input, an external power supply voltage and an internal power supply voltage. Is provided between the power supply voltage and the first
A first transistor that is turned on / off according to the output of the differential amplifier circuit, and the second internal power supply voltage generation means has a second amplification factor higher than the first A second differential amplifier circuit, which receives an internal power supply voltage and detects a difference between the reference voltage and the internal power supply voltage, is provided between the external power supply voltage and the internal power supply voltage.
3. The internal power supply circuit according to claim 2, further comprising a second transistor that is turned on / off by the output of the differential amplifier circuit. 4. The internal power supply voltage generation means receives a reference voltage and an internal power supply voltage and detects a difference between the reference voltage and the internal power supply voltage, an external power supply and the internal power supply. A first transistor provided between the node and a node, the first transistor being turned on / off by an output of the differential amplifier circuit, wherein the differential amplifier circuit includes a current source and a parallel connection between the external power source and the current source. 2. The internal power supply circuit according to claim 1, further comprising a second transistor and a third transistor provided in. 5. The current source includes fourth and fifth transistors connected to one electrodes of the second and third transistors and turned on / off based on an external signal. Internal power supply circuit. 6. An internal power supply circuit that generates an internal power supply voltage based on an external power supply voltage, the internal power supply node and an internal power supply circuit that generates an internal power supply voltage based on the external power supply voltage and supplies the internal power supply voltage to the internal power supply node. Power supply voltage generation means, and internal power supply voltage correction means for supplying to the internal power supply node a voltage for correcting the internal power supply voltage generated by the internal power supply voltage generation means based on an external power supply voltage or a ground voltage. The internal power supply voltage correcting means includes first and second transistors that are activated according to the magnitude of the internal power supply voltage, and from the external power supply to the internal power supply node via the first transistor. An internal power supply circuit that supplies a voltage and draws a voltage from the internal power supply node by grounding through the second transistor. 7. An internal power supply circuit for generating an internal power supply voltage based on an external power supply voltage, the internal power supply node having a predetermined drive capability, and generating the internal power supply voltage based on the external power supply voltage. First and second internal power supply voltage generation means for supplying to the internal power supply node, and the first and second internal power supply voltage generation means are operated for a predetermined period after the internal power supply voltage is lowered, and for the predetermined period. An internal power supply circuit comprising: a control unit that operates only the first internal power supply voltage generation unit after a lapse of time. 8. The first and second internal power supply voltage generating means each have a predetermined amplification factor, a differential amplifier circuit to which a reference voltage and an internal power supply voltage are input, an external power supply and an internal power supply. The internal power supply circuit according to claim 7, further comprising a transistor that is provided between the power supply node and a transistor and that is turned on / off by an output of the differential amplifier circuit. 9. An internal power supply circuit for generating an internal power supply voltage based on an external power supply voltage, the internal power supply node having a predetermined drive capability, and generating the internal power supply voltage based on the external power supply voltage. An internal power supply voltage generating means for supplying the internal power supply node to the internal power supply node; and an internal power supply voltage correcting means for supplying a voltage for correcting the internal power supply voltage based on an external power supply voltage to the internal power supply node. The voltage generating means has a predetermined amplification factor and is provided between a differential amplifier circuit to which the reference voltage and the internal power supply voltage are input, and an output of the differential amplifier circuit provided between the external power supply and the internal power supply node. A first transistor that is turned on / off, the internal power supply voltage correction means is provided in parallel with the first transistor between an external power supply and an internal power supply node, and is based on an external signal. Activatable second transistor being, with a internal power supply circuit.