JPH0954751A - Information processing device - Google Patents

Abstract

(57) [Summary] [Purpose] To prevent malfunction of the bus that occurs when the bus cycle is shorter than the charging time of the common bus. An information processing apparatus comprising a common bus having a cycle synchronized with a clock and a plurality of units connected to the common bus, wherein information is transferred between the units by using the common bus. Before releasing the right to use the common bus, the dummy information addition output means for adding a predetermined amount of dummy information for securing the time for charging the common bus to the transfer information and outputting the transfer information; A dummy information removing means for removing the dummy information when inputting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for transferring information using a common bus, and more particularly to a technique effectively applied to an information processing apparatus using a common bus having a cycle synchronized with a clock. It is a thing.

[0002]

2. Description of the Related Art A PCI bus is well known as a common bus having a cycle synchronized with a clock.
The bus is disclosed in a commentary article "Nikkei Bytes February 1994 issue""Processor" internal bus "standard mounting of favorite PCI advances" (pages 162 to 171).

The PCI bus is a bus that transfers one clock per clock.
Based on a cycle, the bus signal line is composed of data and address signal lines, bus command and byte enable signal lines, and other bus control signal lines, and a plurality of signals use the same signal line. The time-division (multiplex) transfer method is used to switch the signal type when needed according to the bus clock.

The PCI bus does not have a terminating resistor, and the signal line contains the original signal wave and the reflected wave. The signal wave and the reflected wave are combined to generate a signal for driving the device. are doing. This reduces power consumption.

FIG. 10 shows a timing chart of burst transfer in this PCI bus.

In FIG. 10, each signal is a logical value expression, a CLK signal indicates a bus clock, an AD signal indicates address data, a C / BE # signal indicates a command byte enable, and a FRAME # signal. Indicates that the bus is in use, the IRDY # signal indicates that the data transfer on the bus master side is ready, and the TRDY # signal indicates that the data transfer on the bus slave side is ready.

In the burst transfer shown in FIG. 10, after the address and the bus command are transferred in the first cycle 1, the data and the byte enable are transferred one after another (cycles 2 to 3), and one transfer is performed per bus clock. It's timing.

Although not shown in FIG. 10, the PCI
If the bus is not ready for data transfer, IRDY
By setting the # signal or TRDY # signal to a logical value of 0, a wait cycle can be inserted during the transfer.

[0009]

SUMMARY OF THE INVENTION As a result of studying the above prior art, the present inventor has found the following problems.

The above-mentioned conventional PCI bus does not have a terminating resistor and generates a signal for driving a device by combining a signal wave and a reflected wave. Therefore, the common bus wiring length is long and the total load is large. When the capacity is heavy, there are the following problems.

The time for generating the signal for driving the device on the common bus is the time until the charging of the common bus is completed, but the total load capacity becomes heavy and the time for charging the common bus is long. Is coming.

The signal propagation time on the common bus is the time for the voltage level at the sink end to be fixed at a high level or a low level via the threshold voltage level.

Therefore, when the total load capacity of the common bus is heavy, the relationship among the bus cycle time, the charging time of the common bus, and the signal propagation time is as follows: bus cycle time ≧ time for charging the common bus> common Because of the signal propagation time on the bus, the bus cycle time is shorter than the time to charge the common bus.

Therefore, when the bus cycle becomes shorter than the charging time of the common bus as in the case where the total load capacity of the common bus is heavy, the state of the bus becomes unstable,
There is a problem that noise generated at the time of switching buses may reciprocate on the bus and cause a malfunction of the bus unexpectedly after a certain time has elapsed.

An object of the present invention is to provide a technique capable of preventing a malfunction of the bus that occurs when the bus cycle is shorter than the charging time of the common bus.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In an information processing apparatus comprising a common bus having a cycle synchronized with a clock and a plurality of units connected to the common bus, and performing information transfer between the units using the common bus, each unit Before releasing the right to use the common bus, the dummy information addition output means for adding a predetermined amount of dummy information for securing the time for charging the common bus to the transfer information and outputting the transfer information; A dummy information removing means for removing the dummy information when inputting.

[0019]

According to the above-mentioned means, the source unit outputs dummy information for ensuring the time for charging the bus after outputting the information, and at the information output destination, the source unit outputs the information to the common bus. By suppressing the input of the dummy information that is being output, the time for charging the common bus is secured and the state of the common bus can be stabilized, so that the bus cycle is Is shorter than the charging time of the common bus, it is possible to prevent the malfunction of the source unit and the like due to the waveform disturbance of the common bus signal.

The structure of the present invention will be described below together with embodiments.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a diagram for explaining the configuration of an information processing apparatus which is an embodiment of the present invention.

In FIG. 1, 1 is a unit A, 2 is a unit B, 3 is a unit C, and 100 is a common bus.

The common bus 100 includes units A to C (1 to
3) A bidirectional bus between 1) and a 1-bit LAS indicating a transfer end cycle on the bus master side (source of the bus)
It consists of a T # signal 101, a 4-byte AD signal 102 for transferring addresses and data, and a 1-byte C / BE # signal 103 for transferring bus commands and byte enables.

Units A to C of the information processing apparatus of this embodiment
(1 to 3) exchange information with each other using the common bus 100, and the arbitration logic for the right to use the common bus 100 is built in the unit A (1).

In addition to the common bus 100, the units A to C (1 to 3) include a CLK signal 104 indicating a bus clock, a REQB signal 105 indicating a request for securing the right to use the common bus 100 of the unit B, and a unit B. Common bus 100
A GRTB signal 106 indicating that it is in use, a REQC signal 107 indicating a request to secure a right to use the common bus 100 of the unit C, and a GRTC signal 1 indicating that the common bus 100 of the unit C is in use
08 are respectively connected.

The common bus 100 has a bus cycle synchronized with the CLK signal 104, and each signal of the common bus 100 has a high level, a low level, and a period of one cycle.
And one of the high-impedance voltage output states, and the pull-up resistor or the pull-down resistor is not used, so the high-impedance voltage output state is used only for one cycle in which the source unit changes.

Therefore, the cycle in the high impedance voltage output state holds the voltage output state one cycle before, and when no unit holds the right to use the common bus 100 for two cycles or more, the bus is not used. Unit A, which contains arbitration logic, guarantees the source of the bus.

In the information processing apparatus of this embodiment, the number of units is three, but the present invention can be applied if there are two or more units.

Further, in this embodiment, the last 1 of the output information
The case where the information of the bus cycle is added to the end of the output information and output will be described.

FIG. 2 is a diagram for explaining the configuration of the unit A (1) that controls the common bus 100.

As shown in FIG. 2, the unit A (1) of this embodiment has a bus arbiter logic 4 for arbitrating the right to use the common bus 100, a bus output logic 5, and a bus input logic 7.
A register 8 that holds a bus use end instruction output from the bus output logic 5 for one cycle; and a register 9 that holds a bus use end instruction output from the bus output logic 5 and outputs it to the LAST # signal 101. A register 10 that holds an address, write data, or a value of all 0s output from the bus output logic 5 and outputs the AD signal 102, and a bus command, write byte enable, or all 0s output from the bus output logic 5. Register 11 which holds the value of C / BE # and outputs it to C / BE # signal 103, 1-cycle delay register 12 of register 8, driver 13 which outputs to LAST # signal 101, driver 14 which outputs to AD signal 102, C / BE # signal 103 output driver 15 and LAST # signal 101 input AND 16
AND 17 for inputting the AD signal 102, and C / BE
The AND 18 for inputting the # signal 103, the register 19 for holding the output signal LASTAIin 113 of the AND 16 for one cycle, the register 20 for holding the output signal of the AND 17 for one cycle, and the register for holding the output signal of the AND 18 for one cycle 21, a 1-cycle delay register 22 of the register 19, an OR 23 that creates an output condition to the common bus 100, an output signal of the OR 23 is held for one cycle, and the common bus 100 (LAST # signal 101, AD signal 102, And the C / BE # signal 103) and an enable register 24 for controlling the output to the C / BE # signal 103), a one-cycle delay register 25 of the register 24, an AND-OR 26 for creating a clock condition for the output registers 9 to 11, and a common bus 10.
0 (LAST # signal 101, AD signal 102, and C /
OR 27 for suppressing the input signal from the BE # signal 103)
Consists of

Further, the bus arbiter logic 4 includes a REQA signal 109 indicating a request to secure the right to use the common bus 100 of the unit A, a GRTA signal 110 indicating that the common bus 100 is being used for the REQA signal 109 of the unit A, and a signal of the unit A. The GRTN signal 111 indicating that the common bus 100 is in use for guaranteeing the bus source, and the output signal L from the register 8
There is ASTA 112.

FIG. 3 is a diagram for explaining the configuration of the units B to C (2 to 3) that control the common bus 100.

As shown in FIG. 3, the units B to C (2 to 3) do not have the bus arbiter logic 4, and it is assumed that the units A (1) shown in FIG. And AND 28 for creating clock conditions for the output registers 9-11.

FIG. 4 is a diagram for explaining the configuration of the bus / arbiter logic 4 shown in FIG.

The bus arbiter logic 4 is a common bus 100 from units AC (1-3), as shown in FIG.
REQA to C signals (109, 10) indicating a right to use reservation request
5 or 107) and REQA to C signals (10
9, 105, 107) priority encoder 3
1 and AND-32 to 35, a register 36 indicating that the unit A is using the common bus 100 to guarantee the bus source, and that the unit A is using the common bus 100 to transfer information. 37, a register 38 indicating that the unit B is using the common bus 100 for information transfer, and a register 39 indicating that the unit C is using the common bus 100 for information transfer. And the output signals GRTB to C of the registers 38 to 39.
OR 40 of (106, 108) and registers 36 to 39
Output signals GRTN, GRTA to C (111, 110,
106, 108) or OR 41.

Each register of each unit shown in FIGS. 2-4 sets input data using the rising edge of CLK signal 104.

Next, regarding the operation of the unit A (1),
Description will be given by taking as an example the transfer when the 8-byte read request from the unit A (1) to the unit B (2) and the 4-byte read request to the unit C (3) are continuously performed.

FIG. 5 shows the units A (1) to B.
It is a timing chart figure which shows transfer at the time of making an 8-byte read request to (2) and a 4-byte read request to unit C (3) continuously.

First, the output control operation of the unit A to the common bus 100 will be described.

In cycle 0, the common bus 100 is being used by the unit B or unit C, and since the unit A requests the use of the common bus 100, the REQA signal 109 becomes a logical value 1 and the REQB to C signals (105, 107).
Remains at logical 0.

Therefore, the encoder 31 causes the REQA
The signal 109 is received, and the output of the OR 41 has a logical value of 0, so that the output of the AND 33 has a logical value of 1.

In cycle 1, the output of the AND 33 is held in the register 37, the GRTA signal 110 becomes the logical value 1, the bus output logic 5 starts preparing the output to the bus, and the OR 2
The output of 3 has a logical value of 1.

In cycle 2, the output of the bus output logic 5 causes the registers 8 and 9 to have a logical value 0 indicating that the end cycle is invalid.
To register 10 with address 0 in unit B (2)
The bus command 0 indicating the 8-byte read and the transfer tag address 0 are set in the register 11, and the OR 23
The register 24 becomes a logical value 1 by the output of, and the output buffers 13 to 15 are enabled, and the unit A outputs to the common bus 100.

Further, the REQA signal 109 becomes a logical value 0 by the logical value 1 of the GRTA signal 110, the output of the OR 30 becomes a logical value 0, and the GRTB to C signals (106, 10).
Since 8) has a logical value of 0, the output of the OR 40 has a logical value of 0 and the output of the AND 32 has a logical value of 1.

In the cycle 3, the output of the bus output logic 5 causes the registers 8 and 9 to have the logical value 1 indicating that the end cycle is valid.
To register 10 with address 1 in unit C (3)
Is set in the register 11 with a bus command 1 indicating a 4-byte read and a transfer tag address 1, and the unit A outputs it to the common bus 100.

Further, the output of the AND 32 is held in the register 36, the GRTN signal 111 becomes the logical value 1, the bus output logic 5 starts the output preparation for guaranteeing the bus source, and the output of the AND OR 26 remains the logical value 1. Is.

The register 37 is operated by the LASTA signal 112.
Are reset and the GRTA signal 110 has a logical value of zero.

In cycle 4, the output of the bus output logic 5 causes the registers 8 and 9 to have a logical value of 0 indicating that the end cycle is invalid.
, Register 0 with all 0s, register 11 with NO
A value of all 0s indicating OP is set, and the unit A (1) outputs it to the common bus 100.

Since the unit B requests the use of the common bus 100, the REQB signal 105 has a logical value of 1,
The output of the OR 32 has a logical value of 1, and the REQA and C signals (109, 107) have a logical value of 0, so the encoder 31 accepts the REQB signal 105, but the output of the OR 41 has a logical value of 1. The output of the AND 34 has a logical value of 0.

In cycle 5, the same value as in cycle 4 is set in the registers 8 to 11 from the bus output logic 5, and the unit A outputs it to the common bus 100.

Further, the output of the OR 32 causes the register 36
Is reset and the GRTN signal 111 becomes a logical value 0,
Since the output of the OR 41 has the logical value 0, the output of the AND 34 has the logical value 1 and the output of the OR 23 has the logical value 0.
By this cycle 5, the bus is charged before the bus is released.

In cycle 6, the output of the OR 23 sets the register 24 to the logical value 0, the output buffers 13 to 15 are disabled, the common bus 100 is set to the high impedance state, and released.

In cycles 7-9, unit B (2) outputs for an 8-byte read response of address 0, and in cycles 11-12, unit C (3) outputs for a 4-byte read response of address 1. Cycles 9 and 12 at this time are for charging the bus.

Next, input control from the common bus 100 of the unit A will be described.

The input data from the common bus 100 is suppressed by AND 16 to 18 when the output of the OR 27 has a logical value of 1, and one cycle additional portion (cycle 5, cycle) described in the above output is used. 9, cycle 12)
Is ignored.

The condition that the output of the OR 27 becomes the logical value 1 is
As shown in FIG. 2, registers 19, 22, 24, and 2
Since the output of 5 is the logical value 1, the register 2 can be used in the cycles 0 to 6, 9, 10, 12, and 13 shown in FIG.
The values 0 and 21 are all logical 0, and the cycles 7, 8 and
Only 11 has a logical value of 1 and is taken into the bus input logic 7.

Therefore, by adding an extra cycle as the time for charging the bus before releasing the bus, instability of the bus state is prevented, and a malfunction occurs when the bus cycle is shorter than the time for charging the bus. It can be prevented.

Next, an example of information transfer between various units in the above-described information processing apparatus of the present embodiment will be described with reference to the timing chart diagrams of the common bus 100 shown in FIGS.

6 to 8, the bus cycle is the number of cycles used for explaining the present embodiment, CLK is the signal 104, AD is the signal 102, and C / BE # is the signal 10.
3, LAST # is the signal 101. Also, the solid line indicates the logical value, and the dotted line indicates the high impedance state.

FIG. 6A is a timing chart showing an example of transfer from the unit B (2) to the unit C (3) when an 8-byte read request is made.

As shown in FIG. 6A, in cycle 2, the unit B (2) outputs the AD signal 102 to the unit C (3).
Address is output, a bus command indicating 8-byte read and a transfer tag address are output to the C / BE # signal 103, and a logical value 1 indicating that the end cycle is valid is output to the LAST # signal 101.

In cycle 3, since the LAST # signal 101 in cycle 2 has a logical value of 1, unit B (2) outputs the same value as in cycle 2.

In cycle 4, the AD signal 102, the C / BE # signal 103, and the LAST signal are switched to switch the bus output.
The # signal 101 is in a high impedance state.

In cycle 5, the unit C (3) reads data 0 of the first 4 bytes requested by the AD signal 102.
Is output, the byte enable 0 corresponding to the first 4 bytes and the transfer tag address sent in the cycle 2 are output to the C / BE # signal 103, and the LAST # signal 101 is set to a logical value 0 indicating that the end cycle is invalid. Is output.

In cycle 6, the unit C (3) outputs the next 4-byte data 1 requested to be read to the AD signal 102, and outputs the byte enable 1 corresponding to the next 4 bytes to the C / BE # signal 103. LAST # signal 101
A logical value 1 indicating that the end cycle is valid is output to.

In cycles 7-8, the same operation as in cycles 3-4 is performed.

Cycles 3 and 7 at this time are provided as time for charging the bus.

The byte enable at the time of reading may output a logical value 1 for the byte for which the reading is valid and a logical value 0 for the byte for which the reading is invalid, or all the data at the time of reading. Is valid, an undefined value may be output.

FIG. 6B is a timing chart showing another example of transfer from the unit B (2) to the unit C (3) when an 8-byte read request is made.

Cycles 1 to 4 shown in FIG. 6B are shown in FIG.
It operates similarly to (A).

In cycle 5, since the read response of the unit C (3) is not in time and the bus usage right is vacant, the unit A (1) outputs a value of 0 to the AD signal 102 to guarantee the source of the bus. A value of all 0s indicating NOOP is output to the / BE # signal 103, and a logical value 0 indicating that the end cycle is invalid is output to the LAST # signal 101.

In cycle 6, the unit A (1) outputs the same value as in cycle 5, and the bus is charged.

Cycles 7 to 11 operate similarly to cycles 4 to 8 in FIG.

FIG. 6C is a timing chart showing an example of transfer from the unit B (2) to the unit C (3) when a 4-byte read request is made.

In cycle 2 shown in FIG. 6C, the unit B (2) outputs the bus command indicating the 4-byte read to the C / BE # signal 103 and the transfer tag address, and thus the unit C (3) The read response data of 4) is 4 bytes, and is a timing chart diagram excluding the cycle 5 of FIG. 6A.

FIG. 7A is a timing chart showing an example of transfer from the unit B (2) to the unit C (3) when an 8-byte write request is made.

In cycle 2 shown in FIG. 7A, the unit B (2) outputs the address in the unit C (3) to the AD signal 102, and the C / BE # signal 103 indicates the 8-byte write bus. Output command and transfer tag address,
A logical value 0 indicating that the end cycle is invalid is output to the LAST # signal 101.

In cycle 3, the unit B (2) outputs the data 0 of the first 4 bytes requested to be written to the AD signal 102, and outputs the byte enable 0 corresponding to the first 4 bytes to the C / BE # signal 103. , LAST # signal 10
A logical value 0 indicating that the end cycle is invalid is output to 1.

In cycle 4, the unit B (2) outputs the next 4 bytes of data 1 requested to be written to the AD signal 102, and outputs the byte enable 1 corresponding to the next 4 bytes to the C / BE # signal 103. , LAST # signal 101 outputs a logical value 1 indicating that the end cycle is valid.

In cycle 5, since the LAST # signal 101 in cycle 4 has a logical value of 1, unit B (2) outputs the same value as in cycle 4, and the bus is charged.

In cycle 6, the AD signal 102, the C / BE # signal 103, and the LAST signal for switching the bus output.
The # signal 101 is in a high impedance state and the bus is released.

The byte enable at the time of writing outputs a logical value 1 for a byte to be written and a logical value 0 for a byte which is not written.

FIG. 7B is a timing chart showing an example of transfer from the unit B (2) to the unit C (3) at the time of a 4-byte write request.

In cycle 2 shown in FIG. 7B, since the unit B (2) outputs the bus command indicating the 4-byte write and the transfer tag address to the C / BE # signal 103, the write data becomes 4 It becomes a byte, and is a timing chart diagram excluding the cycle 3 in FIG.

FIG. 7C is a timing chart showing the case where the bus use right is vacant and the unit A (1) guarantees the source of the bus for 3 cycles.

In cycle 2 shown in FIG. 7C, all the values of 0 are output to the AD signal 102, and the C / BE # signal 103 is output.
A value of all 0s indicating NOOP is output, and a logical value 0 indicating that the end cycle is invalid is output to the LAST # signal 101.

In cycles 3 to 4, unit A (1) outputs the same value as cycle 2.

In cycle 5, the AD signal 102, the C / BE # signal 103, and the LAST signal for switching the bus output are used.
The # signal 101 is in a high impedance state.

FIG. 8 shows units A (1) to unit B.
FIG. 11 is a timing chart showing an example of transfer when an 8-byte write request to (2) and a 4-byte write request to unit C (3) are continuously performed.

As shown in FIG. 8, the unit A (1) outputs the logical value 0 indicating the invalidity of the end cycle to the LAST # signal 101 in the cycles 2 to 5, and the LA in the cycles 6 to 7.
A logical value 1 indicating that the end cycle is valid is output to the ST # signal 101.

The contents of the C / BE # signal 103 in the timing charts of FIGS. 5 to 8 are as shown in the table of FIG.

Therefore, as described above, the source unit outputs the dummy information for ensuring the time for charging the bus after the information is output, and at the information output destination,
By suppressing the input of dummy information that the source unit is outputting information to the common bus, the time for charging the common bus is secured and the state of the common bus can be stabilized, so the total load capacity is Like a heavy common bus,
Even when the bus cycle is shorter than the charging time of the common bus, it is possible to prevent the malfunction of the source unit due to the waveform disturbance of the common bus signal.

That is, the bus cycle can be made shorter than the charging time of the common bus.

The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0098]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

It is possible to prevent a malfunction of the bus that occurs when the bus cycle is shorter than the charging time of the common bus.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a configuration of an information processing apparatus that is an embodiment of the present invention.

FIG. 2 is a diagram for explaining a configuration of a unit A (1) of this embodiment that controls a common bus 100.

FIG. 3 is a diagram for explaining a configuration of units B to C (2 to 3) of the present embodiment that control a common bus 100.

FIG. 4 is a diagram for explaining the configuration of the bus arbiter logic 4 of the present embodiment shown in FIG.

FIG. 5 is a timing chart diagram for explaining an example of information transfer between various units in the information processing apparatus of the present embodiment.

FIG. 6 is a timing chart diagram for explaining an example of information transfer between various units in the information processing apparatus of the present embodiment.

FIG. 7 is a timing chart diagram for explaining an example of information transfer between various units in the information processing apparatus of the present embodiment.

FIG. 8 is a timing chart diagram for explaining an example of information transfer between various units in the information processing apparatus of the present embodiment.

FIG. 9 is a diagram showing the contents of a C / BE # signal 103 in the information processing apparatus of this embodiment.

FIG. 10 is a diagram for explaining a conventional PCI bus.

[Explanation of symbols]

1 ... Unit A, 2 ... Unit B, 3 ... Unit C, 4
… Bus arbiter logic, 5, 6… Bus output logic, 7…
Bus input logic, 8-12, 19-22, 24-25, 3
6-39 ... Register, 13-15 ... Output driver, 16
~ 18, 28, 32 ~ 35 ... And, 23, 27, 3
0, 40, 41 ... OR, 26 ... And-OR, 31 ... Priority encoder, 100 ... Common bus, 101
... LAST # signal, 102 ... AD signal, 103 ... C / B
E # signal, 104 ... CLK signal.

Claims (2)

[Claims] 1. An information processing apparatus comprising: a common bus having a cycle synchronized with a clock; and a plurality of units connected to the common bus, wherein information is transferred between the units using the common bus. Each unit adds dummy information addition output means for adding a predetermined amount of dummy information to the transfer information for ensuring a time for charging the common bus before releasing the right to use the common bus, and the common bus. An information processing apparatus, comprising: dummy information removing means for removing the dummy information when inputting from the. 2. The information processing apparatus according to claim 1, wherein the dummy information addition output means adds the last one bus cycle of transfer information to the end of the transfer information and outputs it. The information processing apparatus according to claim 1, wherein the dummy information removing unit includes a unit that suppresses information input for the last one bus cycle of transfer information.