JPH0950398A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device on which plural pieces of data are written in parallel independently of locations and by which the consistency of data with time, when readout is performed, is maintained. SOLUTION: Write to memory circuits 3, 4 is performed by using write address signals 7, 8, write data signals 10, 11 and write signals 16, 17 in parallel. At this time, information in the memory circuit on which the final write is performed is stored in a control circuit 5. When the readout is performed, a readout address signal 9 and a readout signal 15 are inputted to both memory circuits 3, 4, and readout data signals 12, 13 are outputted, respectively. The information stored in the control circuit 5 corresponding to an address represented by the readout address signal 9 is outputted as a selection signal 18, and a selection circuit 6 selects and outputs data written finally out of two pieces of readout data according to the signal 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device having a plurality of write ports.

[0002]

2. Description of the Related Art Generally, a storage device such as an LSI memory is
One set of input / output data lines or two sets of input-only and output-only data lines are prepared. Then, in a cycle that requires a certain period, only one operation of writing or reading can be performed. With such a storage device, it is not possible to write to two different locations or address spaces at the same time. If two pieces of data are to be simultaneously written in different locations, there is a large restriction that the processing must be divided into a plurality of cycles and performed in time division. Therefore, there has been a problem that the processing performance is deteriorated.

In order to improve the processing performance of writing to such a memory, for example, an interleave method or a method of forming the memory into a plurality of banks has been used. However, these have the constraint that their usage is predetermined for each memory location, so
It is not a fundamental solution. For example, Japanese Patent Publication 61-3
In Japanese Patent No. 5625, there is a description of a multiple operation memory system which has a plurality of memory blocks and can be accessed randomly at the same time.

FIG. 6 is a block diagram showing an example of a conventional storage device. In the figure, 91-1 to 91-N are memory blocks, 92-1 to 92-N are control blocks, 93-1 to
93-N is a selection circuit. Multiple memory blocks 91
-1 to 91-N include a plurality of control blocks 92-1 to 92-
Controlled by -N, the output of each memory block is selected by the selection circuits 93-1 to 93-N and output. Therefore, parallel operation is possible. However, each memory block 91-1 has a different location, and switches the memory block to be accessed by the upper address of the given addresses. Therefore, there is a restriction that access to the same memory block cannot be performed, and perfect parallel operation cannot be performed.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and it is possible to write a plurality of write data completely in parallel independently of the location, and at the time of reading, the last It is an object of the present invention to provide a storage device in which the uniformity of data over time, that is, the data written in is read out, is maintained.

[0006]

According to a first aspect of the present invention, in a storage device having a plurality of write ports,
A plurality of slave storage means having the same address structure, and a control means for storing information specifying in which slave storage means the data last written for each storage unit of the plurality of slave storage means is stored, The present invention is characterized by comprising selection means for selecting information read out corresponding to an address given from the plurality of secondary storage means based on the information stored in the control means.

According to a second aspect of the invention, in the memory device according to the first aspect, the slave memory means has one write circuit and n (n ≧ 1) read circuits, It is characterized in that it is provided with only the above-mentioned number of secondary storage means and n selection means.

According to a third aspect of the present invention, in a storage device, a plurality of storage devices according to the second aspect are provided, and corresponding write ports of the storage devices are commonly connected. .

[0009]

According to the first aspect of the present invention, since the plurality of slave storage means have the same address structure, writing is independently performed in parallel from the plurality of write ports regardless of location. be able to. At this time, with respect to the storage unit in which the writing is performed, only the sub-storage unit in which the data is actually written holds the valid data among the plurality of sub-storage units.
In the other secondary storage means, only past data that has not been erased by writing remains. Therefore, in the case of reading, it is necessary to read from the secondary storage unit that holds valid data. The control unit stores, for each storage unit of the plurality of secondary storage units, information that identifies in which secondary storage unit the last written data exists. Then, the selection means is controlled based on the stored information, and the data read out from the slave storage means in which the data is finally written in the storage unit is selected and output. This makes it possible to maintain the uniformity of the read data over time.

According to a second aspect of the present invention, a sub memory unit having one write circuit and n (n ≧ 1) read circuits is used by the number of write ports. By providing the selecting means, it is possible to configure a memory device having as many write ports and n read ports as the slave memory means.

Further, as in the invention described in claim 3,
A plurality of storage devices according to claim 2 are provided, and the respective corresponding write ports of the storage devices are commonly connected,
It is possible to increase the number of read ports as a whole.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first storage device according to the present invention.
It is a block diagram showing an embodiment. In the figure, 1 is the first
Selection circuit, 2 is a second selection circuit, 3 is a first memory circuit, 4 is a second memory circuit, 5 is a control circuit, 6 is a third selection circuit, 7 is a first write address signal, 8 is the second
Write address signal, 9 is a read address signal,
10 is a first write data signal, 11 is a second write data signal, 12 is a first read data signal, 13
Is a second read data signal, 14 is an output signal, 15 is a read signal, 16 is a first write signal, and 17 is a second
Is a write signal, and 18 is a selection signal.

A first write address signal 7 and a read address signal 9 are input to the first selection circuit 1, and either one is selected by a read signal 15 and output as an address of the first memory circuit 3. To do. That is, when the read signal 15 is input, the read address signal 9 is selected and output as the address of the first memory circuit 3. When the read signal 15 is not input, the first write address signal 7
Is output as the address of the first memory circuit 3.

A second write address signal 8 and a read address signal 9 are input to the second selection circuit 2, and either one is selected by a read signal 15 and output as an address of the second memory circuit 4. To do. That is, when the read signal 15 is input, the read address signal 9 is selected and output as the address of the second memory circuit 4. When the read signal 15 is not input, the second write address signal 8
Is output as the address of the second memory circuit 4.

The memory circuit 3 and the memory circuit 4 are the same memory device having the same address structure. The memory circuit 3 receives the first write signal 16 and receives the first write signal 16.
The data of the first write data signal 10 is written to the address received from the selection circuit 1 of FIG. When the read signal 15 is input, the data written at the address received from the first selection circuit 1 is read and output as the first read data signal 12. When the second write signal 17 is input, the memory circuit 4 receives the second write signal 17.
The data of the second write data signal 11 is written to the address received from the selection circuit 2 of FIG. When the read signal 15 is input, the data written at the address received from the second selection circuit 2 is read and output as the second read data signal 13.

The control circuit 5 stores the last-written memory circuit for each address. When the first write signal 16 is input, it is stored that the data of the address indicated by the first write address signal 7 is held in the first memory circuit. Further, when the second write signal 17 is input, it is stored that the data of the address indicated by the second write address signal 8 is held in the second memory circuit. Then, when the read address signal 9 is input, a selection signal 18 indicating which address circuit holds the data of the address is output to the third selection circuit 6 according to the stored information.

The third selection circuit 6 outputs the first read data signal 12 output from the first memory circuit 3 and the second memory circuit 4 in response to the selection signal 18 from the control circuit 5. The selected second read data signal 13 is selected and output as the output signal 14.

Next, an example of operation in the first embodiment of the storage device of the present invention will be described. First, writing to the first memory circuit 3 can be performed by applying the first write address signal 7, the first write data signal 10, and the first write signal 16. At this time, since the read signal 15 which is a selection signal for the first selection circuit 1 is inactive, the first write address signal 7 is selected.

Similarly, writing to the second memory circuit 4 can be performed by applying the second write address signal 8, the second write data signal 11, and the second write signal 17. At this time, since the read signal 15 which is a selection signal for the second selection circuit 2 is inactive, the first write address signal 7 and the second write address signal 8 are respectively selected.

As described above, when writing data, the first memory circuit 3 and the second memory circuit 4 can be independently supplied with an address, data, and a write signal. Therefore, the write operation is performed in parallel. You can

First memory circuit 3 and second memory circuit 4
And have the same address structure. Therefore, when the parallel writing as described above is performed, the contents of the first memory circuit 3 and the second memory circuit 4 are different even at the same address. However, it is generally assumed that only the same data is held at the same address, and the software is built in such a way. In order to maintain such data uniformity, when writing is performed for a certain address, the data updated by the writing needs to be the data of that address. According to the present invention, by holding the last written memory circuit for each address, it is possible to identify in which memory circuit the data of each address is stored.

Information used for identifying such a memory circuit is stored in the control circuit 5. The control circuit 5 includes a first write address signal 7, a second write address signal 8, a first write signal 16 and a second write signal 17.
Is also input to the control circuit 5. Then, at the time of writing to the first memory circuit 3, the fact that the data is stored in the first memory circuit 3 at the address indicated by the first write address signal 7
At the time of writing to, the control circuit 5 holds information indicating that data has been stored in the second memory circuit 4 for the address indicated by the second write address signal 8.

Further, at the time of reading, the following operation is performed. Read address signal 9 and read signal 1
5 is input to both the first memory circuit 3 and the second memory circuit 4, and data is read as the first read data signal 12 and the second read data signal 13, respectively. At this time, since the read signal 15 which is a selection signal for the first selection circuit 1 and the second selection circuit 2 is active, the read address signal 9 is selected. The first read data signal 12 and the second read data signal 13 are input to the selection circuit 6. On the other hand, the read address signal 9 is also input to the control circuit 5. As described above, the control circuit 5 has
Information indicating in which memory circuit data is stored is stored. The control circuit 5 follows the information stored corresponding to the address indicated by the read address signal 9,
The selection signal 18 is sent to the selection circuit 6. The selection circuit 6 is
The selection signal 18 selects either the first read data signal 12 or the second read data signal 13 and outputs it as the output signal 14. In this way,
Of the data read simultaneously from the plurality of memory circuits, the last written data is read, and the temporal uniformity of the data is maintained.

FIG. 2 is a circuit configuration diagram showing an example of the control circuit 5 according to the first embodiment of the present invention. 2 in the figure
Reference numeral 1 is a first address decoder, 22 is a second address decoder, 23-1 to 23-N are OR circuits, and 24-1 and 2-2.
4-N is a latch circuit, and 25 is a selection circuit.

The first address decoder 21 and the second address decoder 22 receive an n-bit first write address signal 7 and a second write signal 17 when the first write signal 16 and the second write signal 17 are input, respectively. The address inputted by the write address signal 8 of 2 is decoded,
Activate one of the signal lines. N = 2 ^m signal lines are provided corresponding to the address space of the memory.

The OR circuits 23-1 to 23-N include a first address decoder 21 and a second address decoder 22.
Corresponding to each of the N signal lines output from
It is provided individually. Then, the first address decoder 2
When one of the signal lines output from the first and second address decoders 22 becomes active, the enable signal is output to the corresponding latch circuit 24-1 to 24-N.

The latch circuits 24-1 to 24-N include a first address decoder 21 and a second address decoder 2 respectively.
Corresponding to each of the N signal lines output from 2,
N pieces of signal lines are provided, the signal line from the first address decoder 21 is connected as a data input, and the OR circuit 23-
The outputs of 1-23-N are connected as enable inputs. When the enable signals are input from the OR circuits 23-1 to 23-N, the data from the first address decoder 21 is latched.

The selection circuit 25 includes latch circuits 24-1 and 24-2.
The signals respectively output from 4-N are input,
One of them is selected according to the read address signal 9 and output as a selection signal 18.

The operation of the above control circuit 5 will be described. The operation during writing is as follows. The first address decoder 21 and the second address decoder 22 are
The first write address signal 7 and the second write address signal 8 are input and decoded, respectively, and any one output signal of the N output lines is activated.
However, these output signals activate the output signals only when the first write signal 16 and the second write signal 17, which are enable inputs, are active.

Each of the OR circuits 23-1 to 23-N
Calculates the logical sum of the output signals of the corresponding first address decoder 21 and the corresponding second address decoder 22, and outputs the input enable signal to the corresponding latch circuits 24-1 to 24-N. That is, when an active output signal is output from either the first address decoder 21 or the second address decoder 22, the enable signal is input to the corresponding latch circuit.

The output signals of the corresponding first address decoder 21 are input to the latch circuits 24-1 to 24-N. When the enable signals are input from the OR circuits 23-1 to 23-N, the output signal from the first address decoder 21 at that time is latched. That is, when the latch circuit is enabled by the output signal from the first address decoder 21, the output signal “1” from the first address decoder 21 is latched and the second address decoder 22 outputs the latched signal. When the latch circuit is enabled by the output signal of, the output signal from the first address decoder 21 is normally not present, so that "0" is latched. Therefore, the latch circuits 24-1 to 24-N at a certain time have a value “1” for each address space of the memory when the data is written in the first memory circuit 3 last, and the second memory lastly. When written in the circuit 4, the value “0” is held.

At the time of reading, the read address signal 9
Is input to the selection circuit 25 as a selection signal for the latch circuits 24-1 to 24-N. Then, the latch circuits 24-1 to 24-1
Of the output signals of 24-N, only one signal is selected by the selection circuit 25 and output as the selection signal 18 of the third selection circuit 6.

Incidentally, in the above-mentioned first embodiment,
The memory circuits 3 and 4 may be composed of a semiconductor memory such as DRAM or SRAM, or a storage device such as a magnetic disk device, an optical disk device, a register file, or a FIFO memory.

In the above-described first embodiment, the case where the number of write ports is two is shown, but the number of write ports is not limited to this, and the number of write ports may be three or more. In this case, memory circuits are arranged by the number of write ports, and independent write ports are provided for each. An address selection circuit is also provided corresponding to each memory circuit. At this time, the read address may be common. Then, the read data signal line of each memory circuit is input to the common selection circuit 6, and the control circuit 5
Either of them may be selected by the selection signal 18 from. When the control circuit 5 is configured in the same manner as the configuration shown in FIG. 2, for example, the address decoders are provided by the number of memory circuits, and the OR circuits 23-1 to 23-1.
23-N and the latch circuits 24-1 to 24-N may be configured by replacing them with storage elements that store which of the address decoders has an active output signal.

FIG. 3 is a block diagram showing a second embodiment of the storage device of the present invention. In the figure, 31 and 32 are storage devices, 33 is a first write address signal, and 34 is a second
Write address signal, 35 is a first write signal,
36 is a second write signal, 37 is a first write data signal, 38 is a second write data signal, 39 is a first
Read address signal, 40 is the first read signal,
41 is a second read address signal, 42 is a second read signal, 43 is a first output signal, and 44 is a second output signal.

In the above-described first embodiment, only the write port is parallelized and there is only one read port. The second embodiment shows an example in which the read ports are also parallelized.

The storage devices 31 and 32 are the first storage device shown in FIG.
The storage device has the same configuration as the storage device according to the embodiment. First write address signal 33, second write address signal 34, first write signal 35, second write signal 36, first write data signal 37, second
The write data signal 38 of 1 is commonly input to the storage devices 31 and 32. Thereby, for example, the storage device 3
The first memory circuit of No. 1 and the first memory circuit of the storage device 32 have the same content, and the second memory circuit of the storage device 31 and the second memory circuit of the storage device 32 have the same content. Becomes Further, by writing, the storage device 3
The information stored in the control circuits 1 and 32 is also the same.

At the time of reading, by supplying the first read address signal 39 and the first read signal 40 to the memory device 31, the data is read from the memory device 31 and output as the first output signal 43. . In addition, by giving the second read address signal 41 and the second read signal 42 to the storage device 32, the storage device 32
Data is read out and output as the second output signal 44. Since this read operation is performed independently in each storage device 31, 32, it can be performed in parallel.

As described above, the information for selecting the read data stored in the control circuits of the storage devices 31 and 32 is the same. Therefore, if the configuration is such that the selection signal can be output individually to each of the storage devices 31 and 32, the control circuit can be shared.

In the example shown in FIG. 3, the number of output ports is two, but the number of output ports may be three or more and the same configuration can be achieved. In this case, the storage devices shown in FIG. 1 may be arranged by the number of output ports and signals for writing may be shared. Of course, the number of write ports may be three or more, and in that case, each unit may be configured by arranging the memory circuits in each storage device by the number of write ports as described above.

FIG. 4 is a block diagram showing a third embodiment of the storage device of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. 51 is the first memory circuit,
52 is a second memory circuit, 53 and 54 are selection circuits, 55
Is a first read address signal, 56 is a second read address signal, 57 is a first read signal, and 58 is a second read address signal.
Read signal, 59 is the first read data signal, 6
0 is the second read data signal, 61 is the third read data signal, 62 is the fourth read data signal, 63 is the first selection signal, 64 is the second selection signal, and 65 is the first output signal. , 66 are second output signals. The third embodiment shows a configuration example in which a memory circuit having a plurality of reading mechanisms is used to increase the number of output ports.

The first memory circuit 51 and the second memory circuit 52 have one write mechanism and two write mechanisms, and have the same address configuration. In the first memory circuit 51, the first write address signal 7
The write data signal 10 and the first write signal 16 are input and writing is performed. In addition, the first read address signal 55 and the first read signal 57 are input, the data is read and output as the first read data signal 59, and the second read address signal 5
6. The second read signal 58 is input, the data is read and output as the second read data signal 60. The second write address signal 8, the second write data signal 11, and the second write signal 17 are input to the second memory circuit 52 and writing is performed. In addition, the first read address signal 55 and the first read signal 57 are input, the data is read and output as the third read data signal 61, and the second read address signal 56 and the second read signal are output. The signal 58 is input, the data is read, and the fourth read data signal 6
It is output as 2. Note that in FIG. 4, address selection circuits corresponding to the first selection circuit 1 and the second selection circuit 2 shown in FIG. 1 are incorporated in the first memory circuit 51 and the second memory circuit 52. However, the illustration is omitted.

The control circuit 5 stores the last-written memory circuit for each address. When the first read address signal 55 is input, a first selection signal 63 indicating which address circuit holds the data of the address is output to the selection circuit 53 according to the stored information. When the second read address signal 56 is input, the second selection signal 64 is output to the selection circuit 54 according to the stored information.

The selection circuit 53 is responsive to the selection signal 63 from the control circuit 5 to output the first read data signal 59 output from the first memory circuit 51 and the second memory circuit 5.
Any one of the third read data signals 61 output from 2 is selected and output as the first output signal 65. Similarly, the selection circuit 54 uses the selection signal 64 from the control circuit 5.
According to the above, either the second read data signal 60 output from the first memory circuit 51 or the fourth read data signal 62 output from the second memory circuit 52 is selected, and the second read data signal 62 is selected. The output signal 66 is output.

The operation of the third embodiment will be described. The operation at the time of writing is the same as that of the first embodiment described above. The read operation includes the first read address signal 55, the data read operation by the first read signal 57, the second read address signal 56, and the second read address signal 56.
Each of the data read operations by the read signal 58 is performed in the same manner as in the first embodiment.
However, these two read operations are independently performed in parallel.

According to such a memory device, it is possible to read data in parallel by the first read address signal 55 and the second read address signal 56 which are independent of each other, and the memory device as a whole has two write ports. A storage device having two read ports can be realized.

In the third embodiment, a memory circuit having two write mechanisms is used, but by using a memory circuit having three or more write mechanisms, the number of read ports can be increased to the number of write mechanisms. Can be increased.

Furthermore, in the same way as the number of read ports is increased by using the plurality of storage devices shown in the first embodiment in the above-described second embodiment, this third embodiment is also performed. It is possible to increase the number of read ports by using a plurality of storage devices. In this case, if the number of read mechanisms of the memory circuit is p and the number of storage devices to be arranged is q, a storage device having p × q read ports can be configured. Further, by using the storage device shown in the first embodiment and the storage device shown in the third embodiment, it is possible to configure a storage device having an arbitrary number of read ports. Note that the number of write ports is determined by the number of memory circuits arranged in each of the plurality of storage devices.

FIG. 5 is a block diagram showing a fourth embodiment of the storage device of the present invention. In the figure, 71 and 72 are storage devices, 73 is a multiplier, 74 is an adder, 75 to 78 are register files, and 79 to 82 are selection circuits. This fourth
In the embodiment, a specific example is shown in which a storage device configured by arranging a plurality of the storage devices described in the above-described third embodiment is used and configured together with an arithmetic unit. In FIG. 5, only data signals are shown, and address signals and write signals are omitted.

The storage devices 71 and 72 have the same structure as in FIG. 4, and register files 75 and 7 are used as memory devices.
6 and 77,78 are used. The register files 75 to 78 have one writing mechanism and two reading mechanisms. The storage device 71 is the register file 7
5, 76 and the selection circuits 79 and 80, and the storage device 72 includes the register files 77 and 78 and the selection circuits 81 and 8.
2 has two write ports and two read ports. The two storage devices 71 and 72 constitute a storage device having two write ports and four read ports as a whole.

The multiplier 73 receives the two values and outputs the multiplication result. Further, the adder 74 receives two values and outputs the addition result. Here, the output of the multiplier 73 is commonly connected to the respective first write ports of the storage devices 71 and 72, and the output of the adder 74 is commonly connected to the respective second write ports. Also, of the four read ports, the outputs of the two read ports of the storage device 71 are connected to the inputs of the multiplier 73,
The outputs of the two read ports of the storage device 72 are added to the adder 7
4 inputs.

An example of a specific operation in the above-described fourth embodiment will be described. Register file 75 of FIG.
78 are at least R1 to R as addresses, respectively.
It is assumed to have 6.

Now, let us consider a case in which the following calculation is carried out. (R1 × R2) × (R4 + R5) → R6 When this operation is performed using the multiplier 73 and the adder 74 shown in FIG. 5, for example, the following binomial operation may be performed. (1) R1 × R2 → R3 (2) R4 + R5 → R6 (3) R3 × R6 → R6

In a microprocessor or the like which can perform only sequential processing, the operations are performed in this order, but in the configuration shown in FIG. 5, the multiplier 73 and the adder 7 are used.
4 can operate in parallel. Since (1) and (2) are independent calculations, the processing speed can be improved by performing the calculations in parallel. (3)
Cannot be processed unless the results of (1) and (2) are obtained, so that it is not possible to perform parallel operation with (1) or (2).

Either R1, R2, R4, or R4 is added to either of the register files 75 and 77 or 76 and 78.
It is assumed that R5 is stored. In the storage device 71,
R1 and R2 are read, and in the storage device 72, R4 and R5 are read. These four readings are performed in parallel. Read R1,
The data of R2 is input to the multiplier 73, the operation (1) is performed, and the operation result is written to the register file 75 of the storage device 71 and the register file 77 of the storage device 72. At this time, it is stored in the control circuit that the data of R3 is written in the register file 75 and the register file 77.

In parallel with this, read R4 and R5
Is input to the adder 74, the operation (2) is performed, and the operation result is stored in the register file 76 of the storage device 71.
And R6 of the register file 78 of the storage device 72. At this time, it is stored in the control circuit that the data of R6 is written in the register file 76 and the register file 78.

In this way, after the operations (1) and (2) are carried out in parallel, the operation (3) is carried out. In the storage device 71, the data of R3 and R6 are read. At this time, for R3, register file 75
Since it is stored in the control circuit that was written in
Of the data read from the register files 75 and 76, the data read from the register file 75 is selected and input to one of the multipliers 73. At this time,
If the data read from the register file 76 is used, the calculation result of (1) is not reflected,
An error will occur in the calculation result. By storing the register file written last for each address in the control circuit, such a problem is avoided and the temporal uniformity of data is maintained. Similarly for R6,
Since the data written in the register file 76 is stored in the control circuit, the data read from the register file 76 is selected from the data read from the register files 75 and 76, and the other of the multipliers 73 is selected. Entered in.

The multiplier 73 multiplies the two values and outputs the result. The calculation result is written in the register file 75 of the storage device 71 and the register file 77 of the storage device 72 in R6. At this time, it is stored in the control circuit that the data of R6 is now written in the register file 75 and the register file 77. Then R
When 6 is read, the data read from the register file 75 or the register file 77 is selected. Therefore, the calculation result of (3) is correctly selected instead of the calculation result of (2).

As described above, in the fourth embodiment,
By using a storage device having two write ports and four read ports, four values required for operation are read in parallel, operation is performed in parallel, and two operation results are written in parallel. It enables high-speed processing by parallel processing. Of course, it goes without saying that the configuration shown in FIG. 5 is one application example and is not limited to such a usage method.

[0060]

As is apparent from the above description, according to the present invention, when writing to the storage device, the
Since writing can be performed simultaneously in three different locations or address spaces, and processing does not have to be performed in time division, the processing speed can be improved. At this time, since the uniformity of data over time is maintained, it is guaranteed that the last written data for each address will be read.

Further, unlike the conventional interleave method and the method of forming the memory into a plurality of banks, there is no restriction that the usage is predetermined for each memory location, and the same address configuration is used for all. Since it has, the memory can be used flexibly.

Further, when the parallelization of the writing and the parallelization of the reading are attempted at the same time as the parallelization of the writing, there is an effect that the reading processing is speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a storage device of the present invention.

FIG. 2 is a circuit configuration diagram showing an example of a control circuit 5 according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of a storage device of the present invention.

FIG. 4 is a block diagram showing a third embodiment of a storage device of the present invention.

FIG. 5 is a block diagram showing a fourth embodiment of a storage device of the present invention.

FIG. 6 is a block diagram showing an example of a conventional storage device.

[Explanation of symbols]

1 ... 1st selection circuit, 2 ... 2nd selection circuit, 3 ... 1st memory circuit, 4 ... 2nd memory circuit, 5 ... Control circuit, 6
... third selection circuit, 7 ... first write address signal,
8 ... Second write address signal, 9 ... Read address signal, 10 ... First write data signal, 11 ... Second
Write data signal, 12 ... first read data signal, 13 ... second read data signal, 14 ... output signal, 15 ... read signal, 16 ... first write signal,
17 ... Second write signal, 18 ... Selection signal, 21 ... First address decoder, 22 ... Second address decoder, 23-1 to 23-N ... OR circuit, 24-1 to 24-
N ... Latch circuit, 25 ... Selection circuit, 31, 32 ... Storage device, 33 ... First write address signal, 34 ... Second write address signal, 35 ... First write signal, 3
6 ... 2nd write signal, 37 ... 1st write data signal, 38 ... 2nd write data signal, 39 ... 1st read address signal, 40 ... 1st read signal, 4
1 ... 2nd read address signal, 42 ... 2nd read signal, 43 ... 1st output signal, 44 ... 2nd output signal, 51 ... 1st memory circuit, 52 ... 2nd memory circuit, 53 , 54 ... Selection circuit, 55 ... First read address signal, 56 ... Second read address signal, 57 ...
First read signal, 58 ... Second read signal, 59
... first read data signal, 60 ... second read data signal, 61 ... third read data signal, 62 ... fourth read data signal, 63 ... first selection signal, 64
... second selection signal, 65 ... first output signal, 66 ... second
Output signal, 71, 72 ... storage device, 73 ... multiplier, 7
4 ... Adder, 75-78 ... Register file, 79-8
2 ... Selection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Nobuaki Miyagawa 2274 Hongo, Ebina City, Kanagawa Prefecture Fuji Xerox Co., Ltd. (72) Reiji Aihara 1-4-2, Kagamiyama, Higashi Hiroshima City, Hiroshima Prefecture 72 ) Inventor Mitsumasa Koyanagi Aoba, Aoba-ku, Sendai City, Miyagi Prefecture, Aoba (No house number), Tohoku University

Claims (3)

[Claims] 1. In a storage device having a plurality of write ports, a plurality of slave storage means having the same address structure and which slave storage device is the last written data for each storage unit of the plurality of slave storage means. Control means for storing information specifying whether or not it exists in the means, and information read out corresponding to the address given from the plurality of secondary storage means is selected based on the information stored in the control means. A storage device, comprising: a selecting unit for performing the operation. 2. The slave storage means has one write circuit and n (n ≧ 1) read circuits, and the slave storage means is provided by the number of write ports and n selection means. The storage device according to claim 1, wherein: 3. A plurality of storage devices according to claim 2,
A storage device characterized in that the corresponding write ports of each storage device are connected in common.