JPH0945863A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stop a leakage current caused by a parasitic MOS transistor by a method wherein a metal wiring or a polycrystalline silicon wiring used for feeding a GND voltage or a SUB voltage is arranged on a field oxide film between N-type diffusion layers composed in a voltage clamp element. SOLUTION: A terminal 11 is connected to an N-type diffusion layer 16 with a metal wiring 13, and a common discharge wire 12 is connected to an N-type diffusion layer 15 and a P-type diffusion layer 17. Metal wirings 21 and 23 are connected to the common discharge wire 12 and kept at a SUB voltage level when the power is supplied. A metal wiring 21 is arranged covering the field oxide film 24. When a latchup measurement is carried out, a voltage higher than a maximum rated voltage is applied to a metal wiring 22. An electrical field 27 formed by the metal wiring 22 when the voltage is applied is blocked by the metal wiring 21 kept at a SUB voltage level, so that no channel is formed under the field oxide film 24, and a leakage current is restrained from being induced by a parasitic MOS transistor.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device that prevents the generation of parasitic MOS transistors during latch-up measurement.

[0002]

2. Description of the Related Art Heretofore, as a technique for electrostatic discharge protection of this type, there is one disclosed in Japanese Patent Application No. 5-188802. This technique has a circuit configuration as shown in FIG. 4, in which terminals 11a and 11b are an input terminal, an output terminal, and a VCC.
All pad terminals such as terminals and GND terminals are shown.
All of these terminals 11a, 11b are connected to a common discharge line 12 passing near each terminal by a parallel element of voltage clamp elements 71-a, b ... And diodes 72-a, b. 11a and 11b are internal circuits 7
3 is connected.

In the semiconductor integrated device having the above structure, when an electrostatic pulse is applied between the arbitrary terminals 11a and 11b, the voltage clamp elements 71-a and 71c are respectively provided.
-B and the diodes 72-a and 72-b are discharged. For example, when a positive electrostatic pulse is applied to the terminal 11a and a negative electrostatic pulse is applied to the terminal 11b, the electrostatic pulse applied to the terminal 11a is the voltage clamp element 71-a → common discharge line 12 → diode. It is discharged to the terminal 11b via the path 72-b. Conversely, when a positive electrostatic pulse is applied to the terminal 11b, the electrostatic pulse applied to the terminal 11b passes through the path of the voltage clamp element 71-b → the common discharge line 12 → the diode 72-a to the terminal 11a. Is discharged.

That is, the discharge paths are determined for the case where an electrostatic pulse of arbitrary polarity is applied between arbitrary terminals, and at least one voltage clamp element and one forward diode element are used. Is discharged.

FIG. 3A is a diagram showing a mask pattern in the conventional technique. In the figure, the voltage clamp element 71 (71-a, 71-b) and the diode element 72 (72-a, 72-b) shown in FIG.
16 and the P-type diffusion layer 17. Here, the metal wirings 13, 14 and the N-type diffusion layers 15, 16 and P
The contact opening pattern with the mold diffusion layer 17 is omitted. Reference numeral 11 is a terminal (pad), and 18 is a scribe wiring.

FIG. 3B is a sectional view taken along the line AA of FIG. In the figure, the voltage clamp element 71 is constituted by an NPN bipolar transistor formed by the N type diffusion layers 15 and 16 and the P type semiconductor substrate 26, and the diode 72 is constituted by the N type diffusion layer 16 and the P type diffusion layer 17. Has been done. Field oxide films 24 and 25 are provided between the N type diffusion layers 15 and 16 and between the N type diffusion layer 16 and the P type diffusion layer 17.

The metal wiring 21 (14) shown in FIG. 3B is a wiring for connecting the N-type diffusion layer 15 and the common discharge line 12, and the metal wiring 22 (13) is the N-type diffusion layer 16 and. The wiring for connecting the terminal 11 and the metal wiring 23 (1
Reference numeral 4) is a wiring for connecting the P-type diffusion layer 17 and the common discharge line 12.

In the above-mentioned electrostatic breakdown protection operation, these metal wirings 21, 22 and 23 serve as a discharge path for an electrostatic pulse of an arbitrary polarity applied to an arbitrary terminal 11, so that the discharge is smoothly performed. It must be as low resistance as possible to get it done.

[0009]

A latch-up breakdown voltage test is one of the required reliability tests for semiconductor devices. In the latch-up withstand voltage test, the absolute maximum rated voltage ×
A voltage of 1.2 V or higher is applied to investigate the occurrence of latch-up. The above voltage is 5.5V or more when the absolute maximum rated voltage is 3.3V, and the absolute maximum rated voltage is 5.0V.
Is 8.4V or more.

When the above-mentioned latch-up withstand voltage test is performed in the conventional semiconductor integrated device, the terminal 11 shown in FIG.
Is connected to The above voltage is applied to the metal wiring 22 shown in FIG. 3B via the metal wiring 13, and the electric field 2 as shown in FIG.
7 is generated, and the electric field 27 causes the N-type diffusion layer 15 and N
A channel is generated under the field oxide film 24 between the type diffusion layers 16 and the parasitic MOS transistor 71 (71a, 71a,
71b), a leak current flows from the N-type diffusion layer 16 to the N-type diffusion layer 15, and the original power-current operation until latch-up could not be confirmed.

Also, in the automatic latch-up measuring device, the occurrence of latch-up is judged by the current value.
There is a problem that a latch-up occurrence is erroneously determined due to the leak current of the S transistor 71.

An object of the present invention is to provide a semiconductor device which prevents a leak current from being generated by a parasitic MOS transistor in an electrostatic breakdown protection element during latch-up measurement.

[0013]

To achieve the above object, a semiconductor device according to the present invention has a metal terminal, a common discharge line, and a protection element, and prevents generation of a leak current due to a parasitic MOS transistor. In the semiconductor device, a plurality of metal terminals are provided on the semiconductor substrate,
The common discharge line is disposed so as to pass in the vicinity of the metal terminal, and is commonly connected to each of the metal terminals, and the protection element is at least a part of the metal terminals of the plurality of metal terminals. Is provided corresponding to the above, and the metal terminal and the common discharge line are connected to protect the metal terminal from electrostatic breakdown.

At least a part of the common discharge line is connected to the semiconductor substrate.

At least a part of the metal terminals is directly connected to the common discharge line.

The protection element is composed of a voltage clamp element and a diode element.

Further, the protection element has a metal wiring or a polycrystalline silicon wiring arranged on the field oxide film between the diffusion layers forming the semiconductor element, and the metal wiring or the polycrystalline silicon wiring has a low potential. It has become.

A metal wiring or a polycrystalline silicon wiring is arranged on the field oxide film between the diffusion layers forming the protection element, and the metal wiring or the polycrystalline silicon wiring has a low potential, and any metal input from a terminal is inputted. Blocks the electric field generated by polar potentials.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1A is a plan view showing a semiconductor integrated device according to Embodiment 1 of the present invention. In the figure, the terminal 11 is connected to the N-type diffusion layer 1 by the metal wiring 13.
The common discharge line 12 is connected to the N-type diffusion layer 15 and the P-type diffusion layer 17 by the metal wiring 14.

FIG. 1 (b) is a sectional view taken along the line AA of FIG. 1 (a). Here, the metal wirings 21 and 23 are the common discharge line 12
It is connected to the. Although the common discharge line 12 is a scribe line in the conventional example and embodiment of the present specification, it may be a GND line as in Japanese Patent Application No. 5-188802. When power is applied to the scribe wiring 18, the scribe wiring 18 is at a SUB level, and its voltage is about -1.5V to -2V, which is a low voltage. The above-mentioned metal wiring 21 and metal wiring 23 connected to the common discharge line become SUB level when power is supplied. Here, the metal wiring 21 is arranged so as to cover the upper portion of the field oxide film 24. Metal wiring 2
2 is connected to the terminal 11, which is a voltage level of an arbitrary polarity applied to the terminal 11.

In the semiconductor device having the electrostatic breakdown protection circuit having the above-described structure, when the latch-up measurement is performed, the voltage higher than the maximum rated voltage is applied to the metal wiring 22. Since the electric field 27 generated at this time is shielded by the metal wiring 21 at the SUB level as shown in FIG. 1B, a channel is generated below the field oxide film 24 due to the electric field 27. No leakage current is generated by the parasitic MOS transistor.

The internal circuit which is not the protective element will be described. When the terminal 11 is an input / output pad, the power supply voltage of the internal circuit is the maximum rated voltage defined in the latch-up measuring method. Parasitic M due to
No leak current is generated by the OS transistor. When the terminal 11 is a power source, a voltage higher than the maximum rated voltage is supplied to the internal circuit. Therefore, if the distance between the N-type diffusion layers in the internal circuit is equal to or less than that of the N-type diffusion layers in the protection element, the above-mentioned leakage current due to the parasitic MOS transistor occurs.

(Second Embodiment) FIG. 2A is a plan view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA of FIG. 1A. . In the figure, the polycrystalline silicon wiring 31 is set to the GND potential, covers the field oxide film 24, and blocks the electric field 27 from the metal wiring 22 to prevent generation of a parasitic MOS transistor.

According to this embodiment, the N-type diffusion layers 15 and 1 are
6 and the metal wirings 21, 22 connected to the P-type diffusion layer 17
Since the widths of 23 can be made equal, there is an advantage that variations in resistance in the discharge path can be eliminated.

[0026]

As described above, according to the present invention, in the semiconductor device having the electrostatic breakdown protection circuit, the GND potential or the SUB potential is provided on the field oxide film between the N type diffusion layers forming the voltage clamp element. Since the metal wiring or the polycrystalline silicon wiring that has been formed is arranged, the electric field generated by the potential of any polarity input from the terminal can be blocked, the operation of the parasitic MOS transistor can be prevented, and the leakage current can be prevented. By doing so, the original power-current operation can be confirmed during the latch-up measurement.
Further, it is possible to prevent an erroneous determination of the occurrence of latch-up in the automatic latch-up measuring device.

[Brief description of drawings]

1A is a plan view showing a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along line AA of FIG. 1A.

2A is a plan view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 2B is a sectional view taken along line AA of FIG. 2A.

3A is a plan view showing a semiconductor device according to a conventional example, and FIG. 3B is a sectional view taken along line AA of FIG. 3A.

FIG. 4 is a block diagram for explaining the circuit operation of the protection element shown in FIG.

[Explanation of symbols]

 11 terminals (pads) 12 common discharge line 13, 14, 21, 22, 23 metal wiring 15, 16 N-type diffusion layer 17 P-type diffusion layer 18 scribe wiring 24, 25 field oxide film 26 substrate 31 polycrystalline silicon wiring 71 voltage Clamp element 72 Diode element 73 Internal circuit

Claims (5)

[Claims] 1. A semiconductor device having a metal terminal, a common discharge line, and a protection element, in which generation of a leak current due to a parasitic MOS transistor is prevented, wherein a plurality of metal terminals are provided on a semiconductor substrate. The common discharge line is disposed so as to pass near the metal terminal and is commonly connected to each of the metal terminals, and the protection element is at least one of the plurality of metal terminals. A semiconductor device provided corresponding to a metal terminal of a part, and connecting the metal terminal and the common discharge line to protect the metal terminal from electrostatic breakdown. 2. The semiconductor device according to claim 1, wherein at least a part of the common discharge line is connected to the semiconductor substrate. 3. At least a part of the metal terminals is
The semiconductor device according to claim 1, wherein the semiconductor device is directly connected to the common discharge line. 4. The protection element comprises a voltage clamp element and a diode element.
Or the semiconductor device according to 3. 5. The protection element has a metal wiring or a polycrystalline silicon wiring arranged above a field oxide film between diffusion layers forming a semiconductor element, and the metal wiring or the polycrystalline silicon wiring has a low potential. The semiconductor device according to claim 4, wherein: