JPH0944438A - Multiple processing method of synchronous type input / output instructions - Google Patents

Abstract

(57) [Abstract] [Purpose] When a synchronous type input / output instruction is issued from a plurality of instruction processors, the speed is increased by processing the instructions in a multiplexed manner. [Structure] The instruction processor 1 that has acquired the boot information storage area 8 stores boot information in the area 8 and identification information (command processor number) in the area 10. The instruction processor 1 activates input / output to the input / output processor 4 via the interface control device 2. The input / output processor 4 returns the activation response, activates the channel 6 and the device,
Report I / O interrupts. Now interface 2
The channel path 5 is opened, and the input / output instruction from another processor 1 can be activated. I / O processor 4
However, until the end notification is written in the storage area 11 corresponding to the instruction processor 1, the instruction processor 1 polls the storage area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for multiplex processing of synchronous type input / output instructions issued from a plurality of instruction processors.

[0002]

2. Description of the Related Art Synchronous type input / output instructions generally consist of an input / output activation from an instruction processor to an input / output processor and an input / output activation response which is a response from the instruction processor , It consists of an input / output interrupt that reports the end of an instruction, and is named because the instruction processor and the input / output processor execute instructions in synchronization. Since this hardware interface is occupied from the start to the end of one synchronous type input / output instruction, only one synchronous type input / output instruction can be executed at the same time.

In order to process synchronous type input / output instructions in a multiple manner, each instruction processor and the above-mentioned interface between each input / output processor are independently provided to execute synchronous type input / output instructions from a plurality of instruction processors. There is a method of doing the above in parallel, but as the number of instruction processors and I / O processors increases, the amount of hardware becomes enormous.

On the other hand, an asynchronous type input / output instruction is such that when an instruction processor registers an instruction in a queue, it advances to the next instruction, and the input / output processor asynchronously reads the instruction from the queue and executes the instruction. The output instruction can be processed, but the time from the activation of the instruction to its execution is uncertain.

FIG. 4 is a diagram showing a conventional data processing system. 1 is a plurality of instruction processors that analyze a program and perform input / output instruction activation and termination processing for the input / output processor, 2 is an interface control device that connects one instruction processor to one input / output processor, and 3 is an instruction A selector for selecting a processor, a plurality of input / output processors for accepting and executing activation of an input / output instruction and reporting the completion thereof, a channel path control unit for selecting and activating a channel, and a device for activating 6 A channel, 7 is a storage device accessible from both the instruction processor 1 and the input / output processor 4, 8 is a storage area for startup information for synchronous input / output instructions common to a plurality of instruction processors, and 9 is asynchronous with synchronous type input / output instructions. It is a program with type input / output instructions. A device (not shown) or another data processing system is connected to each channel 6.

FIG. 5 is a diagram for explaining the flow of processing of a conventional synchronous type input / output instruction. The operation will be described assuming that n instruction processors execute synchronous type input / output instructions at the same time, for example. The same applies when a plurality of n instruction processors simultaneously execute input / output instructions or when a plurality of instruction processors sequentially execute input / output instructions.

The n instruction processors 1 first request acquisition of the synchronous input / output instruction activation information storage area 8 on the storage device 7. For example, it is assumed that the instruction processor 1a has acquired this storage area 8. The instruction processor 1a stores command information and instruction information of a device to be activated in the storage area 8 as activation information for synchronous input / output instructions.

After that, the instruction processor 1a issues a selection signal for selecting the input / output processor 4 and input / output activation to the interface control device 2. The selector 3 of the interface control device 2 selects, for example, the input / output processor 4a and sends the input / output activation 201. I / O processor 4a
The channel path control unit 5 of the
The input / output activation response 202 is returned to the instruction processor 1a via the, and then the channel path control unit 5 refers to the activation information in the storage area 8 on the storage device 7, selects the channel 6, and activates the channel. To do.

The channel 6 starts the designated device, executes the processing 203 of the synchronous type input / output instruction, and when the processing in this channel 6 and the device is completed, the channel 6
Reports an end interrupt to the channel path control unit 5. In response to this, the channel path control unit 5 sends an input / output interrupt 204 to the instruction processor 1a via the interface control device 2.
Report. The instruction processor 1a uses the input / output interrupt 204
When it receives, the end report 205 is executed for the program 9.

As described above, the interface controller 2 and the channel path controller 5 are occupied by one instruction processor from the acceptance of the input / output activation to the reporting of the input / output interrupt, and thus the first instruction processor. After the end of the input / output instruction, the second instruction processor operates, and similarly, the nth instruction processor is sequentially executed. Therefore, the processing capacity of this data processing system is equivalent to the case where n-1 instruction processors are stopped and one instruction processor executes n synchronous type input / output instructions. Even if it is composed of multiple instruction processors, sufficient processing performance cannot be obtained.

[0011]

As the number of instruction processors increases, the number of I / O instructions issued also increases at the same time. Asynchronous type I / O instructions have been developed to cope with this, and many instructions can be executed with a small amount of hardware. It can be processed. However, in recent years, since processing speed is required, it has become necessary to perform high-speed processing again using synchronous type input / output instructions. For this reason, even in a system that has mainly processed asynchronous type instructions until now, it was necessary to process synchronous type input / output instructions from multiple instruction processors. Since another synchronous type input / output instruction cannot be executed until the output instruction is completed, another instruction processor is made to wait and there is a problem that it cannot process at high speed.

An object of the present invention is to provide a synchronous processing method for synchronous type input / output instructions, which is speeded up by processing the synchronous type input / output instructions when a plurality of instruction processors issue the synchronous type input / output instructions. To do.

[0013]

In order to achieve the above object, in the present invention, a synchronous type input / output instruction (hereinafter referred to as an input / output instruction) is activated and an end process of the instruction is executed for an input / output processor. A plurality of instruction processors, a channel path control unit that receives the activation of the input / output instruction, returns a response to the instruction processor, selects a channel based on the activation information and activates the device, and a device based on the activation information. And a plurality of input / output processors each having a plurality of channels for activating the input / output instructions and executing the processing of the input / output instructions, and interface control means for connecting between the instruction processor and the input / output processor selected by the instruction processor. A data processing system comprising the plurality of instruction processors and a storage unit which is accessed by the plurality of input / output processors. In the method for multiplex processing of input / output instructions issued from the plurality of instruction processors, a method for writing start information and instruction processor identification information among the plurality of instruction processors in the storage means One instruction processor is selected, the input / output activation of the channel path control means in the input / output processor selected by the first instruction processor is instructed, and the first instruction processor is instructed in response to the input / output activation. While returning a response, the channel and the device are activated based on the activation information, and in response to the activation of the device, the channel path control unit notifies the first instruction processor of the input / output interrupt, and the input / output interrupt is notified. At the time of being notified, the interface control means and the channel path control means are opened to another instruction processor. It is.

Further, when the channel is activated, the identification information is read from the storage means and stored in the channel, and is designated by the identification information in the channel in response to the end of the processing in the device. Information including an end notification is stored in an area in the storage unit, and the first instruction processor notified of the input / output interrupt stores information including the end notification in the area assigned to the instruction processor. It is characterized in that the area is polled until it is stored.

[0015]

When the instruction processor issues a synchronous type input / output instruction to the input / output processor and the input / output processor accepts the activation, the interface between the instruction processor and the input / output processor is opened so that the instruction processor Allows another synchronous type input / output instruction to be activated. The instruction processor performs polling until an end report is input to the storage area, the input / output processor executes the processing of the received synchronous type input / output instruction, and stores the end notification in the storage area after the processing is completed. When the instruction processor receives the end notification,
Terminate the synchronous type I / O command. As a result, while the input / output processor is executing the processing of one synchronous type input / output instruction, it is possible to accept the start of the synchronous type input / output instruction from another instruction processor and execute the processing. Can be processed in multiples up to the number of instruction processors.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a data processing system of the present invention. The instruction processor 1 and the interface control device 2 are the same as the conventional ones described in FIG. In the present invention, the storage device 7 is provided with the storage area 11 corresponding to the instruction processor and the storage area 10 for the identification information (instruction processor number) of the instruction processor in the storage area 8 for the boot information. Further, in the channel 6 of the input / output processor 4, an area 12 for storing the identification information of the instruction processor and the device information is provided.

Storage area 11 corresponding to each instruction processor
For example, the instruction processor 1a corresponds to the storage area 11a, the instruction processor 1b corresponds to the storage area 11b, and the storage area is assigned to each instruction processor.

FIG. 3 shows a storage area 11 assigned to each instruction processor. Each storage area 11 stores information 21 for notifying the end of the synchronous type input / output command, information 22 for the execution result of the command (for example, data transfer, message transfer success, failure) and the like. Further, the address of the storage area assigned to each instruction processor is a fixed address.

The identification information storage area 10 in the storage device 7 is used by the instruction processor 1 to notify the input / output processor 4 of the identification information (processor number). That is, when the instruction processor 1 activates a synchronous type input / output instruction, it stores the identification information of the instruction processor in the identification information storage area 10, and the input / output processor 4
When the synchronous type input / output instruction is received, the identification information 10 of this instruction processor is read.

FIG. 2 is a diagram for explaining the processing flow of the synchronous type input / output instruction of the present invention. As in the case of the conventional example, the operation of this embodiment will be described assuming that n instruction processors simultaneously execute the synchronous type input / output instructions.

Similarly to the above, the n instruction processors 1 first request acquisition of the storage area 8 of the synchronous input / output instruction activation information on the storage device 7. For example, if the instruction processor 1a can acquire the storage area 8, the instruction processor 1a stores the command information and the instruction information of the device to be activated as the activation information for the synchronous input / output instruction in the storage area 8 and also stores the identification information. The instruction processor number is stored in the storage area 10.

After that, the instruction processor 1a issues a selection signal for the input / output processor 4 and the input / output activation 101 to the interface control device 2. The selector 3 of the interface controller 2 selects, for example, the input / output processor 4a and sends an input / output activation. The channel path control unit 5 of the input / output processor 4 a returns the input / output activation response 102 to the instruction processor 1 a via the interface control device 2, and then the channel path control unit 5 stores the data in the storage area 8 on the storage device 7. With reference to the activation information, the channel 6 is selected and the channel is activated.

The channel 6 directly reads the boot information from the boot information storage area 8 on the storage device 7 to obtain the identification information 10 of the instruction processor 1a. Alternatively, as another embodiment, when the channel is activated, the activation information is received from the channel path control unit 5 to obtain the identification information 10 of the instruction processor 1a. Then, upon obtaining the identification information of the instruction processor 1a, the channel 6 stores the identification information of the instruction processor 1a and the activated device information in the storage unit 12 inside the channel 6.

When the channel 6 activates the designated device, the channel path controller 5 reports the activation success, and the channel path controller 5 reports the input / output interrupt 103 to the instruction processor 1a via the interface controller 2. To do. Instruction processor 1 that received input / output interrupt 103
The a starts polling 104 for the storage area 11a until the end notification information is stored in the storage area 11a corresponding to the instruction processor 1a. The activated device and channel start executing the process 105 of the synchronous type input / output instruction.

On the other hand, when the input / output interrupt 103 is reported from the channel path controller 5 of the input / output processor 4,
The interface controller 2 between the instruction processor 1a and the input / output processor 4 and the channel path controller 5 are opened,
It becomes possible to execute input / output activation of a synchronous type input / output instruction from another instruction processor. For example, if the instruction processor 1b can obtain the storage area 8 in the same manner as described above, the instruction processor 1b will acquire the storage area 8
The boot information (command information and device information) is written (overwritten with the previous information), and the number of the instruction processor 1b is written in the storage area 10. Then, as described above, the selection signal of the input / output processor 4 and the input / output activation are output to the interface control device 2.

Therefore, while the activated device is processing and executing the input / output instructions, the input / output activation of the synchronous type input / output instructions from the other instruction processors is executed one after another.

When the processing in the device is completed, the channel 6 is completed in the storage area 11a corresponding to the instruction processor 1a based on the identification information of the instruction processor corresponding to the device stored in the storage area 12. The notification information and the execution result information 106 are stored. When the instruction processor 1a polling the storage area 11a reads the information of the end notification and the information of the execution result from the storage area 11a, the instruction processor 1a executes the end report 107 to the processor 9. When access to the storage device conflicts due to polling by an instruction processor and writing of start information by another instruction processor, polling is prioritized.

Thereafter, in the same manner, synchronous type input / output instructions issued from other instruction processors are executed in parallel and in multiples. As a result, in the data processing system of the present invention,
It is possible to obtain a processing capacity which is almost equal to that of n instruction processors executing one synchronous type input / output instruction at the same time.

[0029]

As described above, according to the present invention, the synchronous type input / output instructions can be processed in multiples up to the number of instruction processors, so that each instruction processor and each input / output processor are independent. It is not necessary to provide the dedicated hardware described above, and it is possible to process efficiently and at high speed with a small amount of hardware. In addition, in one synchronous type input / output instruction, the effect becomes more remarkable as the processing execution time in the device is longer.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data processing system of the present invention.

FIG. 2 is a diagram illustrating a flow of processing of a synchronous type input / output instruction of the present invention.

FIG. 3 shows a storage area allocated for each instruction processor.

FIG. 4 is a diagram showing a conventional data processing system.

FIG. 5 is a diagram illustrating a flow of processing of a conventional synchronous type input / output instruction.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 instruction processor 2 interface control device 3 selector 4 input / output processor 5 channel path control unit 6 channel 7 storage device 8 startup information storage area 9 program 10 instruction processor identification information storage area 11 storage area corresponding to instruction processor 12 instruction processor Area for storing device identification information and device information

Claims (2)

[Claims] 1. A plurality of instruction processors that execute a synchronous type input / output instruction (hereinafter referred to as “input / output instruction”) and end processing of the instruction to an input / output processor, and a start of the input / output instruction. , A channel path control means for returning the response to the instruction processor and selecting and activating a channel based on activation information, and a plurality of channels for activating a device based on the activation information to execute processing of the input / output instruction A plurality of input / output processors each having an instruction processor, an interface control means for connecting between the instruction processor and an input / output processor selected by the instruction processor; And a storage means accessed from the input / output processor of the input / output processor, the input / output issued from the plurality of instruction processors. A method of processing output instructions in a multiplexed manner, wherein, of the plurality of instruction processors, a first instruction processor in which activation information and information for identifying the instruction processor are written in the storage means is selected, and the first instruction processor is selected. Input / output activation of the channel path control means in the input / output processor selected by the instruction processor is instructed, a response is returned to the first instruction processor in response to the input / output activation, and a channel is generated based on the activation information. And a device is activated, and in response to the activation of the device, the channel path control unit notifies the first instruction processor of an input / output interrupt, and at the time when the input / output interrupt is notified, the interface control unit and the channel A method of multiprocessing synchronous type input / output instructions, characterized in that the path control means is opened to another instruction processor. 2. The identification information is read from the storage means and stored in a channel when the channel is activated,
In response to the end of the process in the device, the information including the end notification is stored in the area in the storage unit designated by the identification information in the channel, and the first input / output interrupt is notified. 2. The synchronous type input / output instruction according to claim 1, wherein the instruction processor polls the area assigned to the instruction processor until information including the end notification is stored in the area. Multiprocessing method.