JPH0936127A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability of a semiconductor device and to make the high-speed operation of the device possible. SOLUTION: A semiconductor device is provided with a first semiconductor region 3, which is formed in a layer, which is same as a layer on a semiconductor substrate 1, on a semiconductor substrate 2 in such a way that the region 3 is surrounded with insulating parts 4 and has a first conductivity type, a first semiconductor layer 5, which is formed in such a way as to cover the region 3, is formed in such a way that the layer 5 is extendedly provided to regions, where are adjacent to this region 3 and at least the first semiconductor regions of the parts 4, and has a second conductivity type different from the first conductivity type, and a second semiconductor region 18, which is formed in the surface region of the layer 5 and has a first conductivity type.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method, and more particularly to a bipolar transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, high-speed silicon bipolar technology has been developed in order to realize a high-speed LSI, and a technology for forming a transistor using two-layer polycrystalline silicon has been proposed. A method of manufacturing this transistor will be described with reference to FIG. FIG.
(A) is a part 5 of the external base region of the transistor
a ', a plan view showing the positional relationship between the opening inner wall 15 and the emitter region 18, FIG. 6 (b) is a cross-sectional view of the transistor shown in FIG. 6 (a) taken along the cutting line AA', and FIG. 6
(C) is a sectional view taken along the line BB '.

First, a high-concentration n-type buried layer 2 is formed on a silicon substrate 1, and a collector epitaxial layer 3 is grown on this buried layer 2. Then, a groove is formed in the epitaxial layer 3 and an insulating film is embedded in the groove to form the element isolation region 4.

Next, a polycrystalline silicon film 10 to be a base extraction electrode is formed, and a p-type impurity is implanted into this polycrystalline silicon film 10. After that, the oxide film 11 and the nitride film 12 are sequentially deposited by the CVD method. Lithography is used to form the nitride film 1 to form the emitter region.
2, an opening is formed in the oxide film 11 and the polycrystalline silicon film 10 so that the epitaxial layer 3 is exposed, and then impurities are diffused from the polycrystalline silicon film 10 into the epitaxial layer 3 by a thermal diffusion method to form the external base region 5a. Form. At this time, the opening is formed inside the element region, but it is necessary to allow a margin for alignment in the lithography process, and the external base region 5a and the base lead electrode 1 are formed.
Since it is necessary to make contact with 0, the distance X1 shown in FIG. 6 is required.

After that, p-type impurities are ion-implanted into the exposed epitaxial layer to form an internal base region 5b. Next, an oxide film is deposited on the entire surface, and anisotropic etching is performed to form the opening inner sidewall 15. This forms an emitter opening. After depositing the polycrystalline silicon layer 17 so as to fill the emitter opening, an n-type impurity is injected into the polycrystalline silicon layer 17 and heat-treated to diffuse the impurity into the internal base region to form the emitter region 18. Form. Next, the emitter extraction electrode 17 is formed by patterning the polycrystalline silicon layer 17 containing n-type impurities into a predetermined shape.

The transistor manufactured by such a method has a high cutoff frequency because the emitter layer 18 and the base layer 5b can be thinned. Therefore, it is suitable for high-speed operation and is widely used. However, in order to obtain higher speed operation, it is necessary to achieve a high cutoff frequency and reduce the parasitic capacitance.

Now, considering the plane area of the external base region 5a in the transistor shown in FIG. 6, this is only necessary for connecting the base extraction electrode 10 and the internal base region 5b, and the actual transistor operation. In addition to the above, the capacitance between the base and the collector is increased, so it is necessary to reduce the capacitance as much as possible. Therefore, a structure as shown in FIG. 7 has been proposed. Here, FIG. 7A is a plan view of the transistor, FIG. 7B is a cross-sectional view taken along the cutting line AA ′ of this transistor, and FIG. 7C is taken along the cutting line BB ′. FIG. As described above, the AA ′ direction has the same structure as the transistor structure shown in FIG. 6B, but the BB ′ direction shortens the length of the element region, and the base extraction electrode 10 serving as a diffusion source of the external base region 5a. Is cut on the element isolation oxide film 4, so that the external base region 5a is not formed. Therefore, the base-collector capacitance is reduced, which is effective for high-speed operation. However, in this structure, carriers emitted from the emitter region 18 in the vicinity of the element isolation oxide film 4 flow into the collector region 3 along the interface with the oxide film 4 as shown by the arrow in FIG. It was easy to occur and had a problem in reliability.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device including a bipolar transistor which can operate at high speed and has high reliability, and a method for manufacturing the same.

[0009]

A semiconductor device according to the present invention includes a first semiconductor region of a first conductivity type formed in the same layer on a semiconductor substrate so as to be surrounded by an insulating portion.
Different from the first conductivity type formed so as to cover the first semiconductor region and extend to at least a region adjacent to the first semiconductor region of the first semiconductor region and the insulating portion. A first conductivity type second semiconductor region; and a first conductivity type second semiconductor region formed on a surface region of the first semiconductor layer on the first semiconductor region. It is characterized by

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a first epitaxial layer of the first conductivity type on a semiconductor substrate on which a buried layer of the first conductivity type is formed, and the first method. Forming a groove in the epitaxial layer and burying a first insulating film in the groove to electrically isolate the first epitaxial layer; and using a selective epitaxial technique for controlling lateral growth, the first epitaxial layer is formed. Forming a second epitaxial layer of a second conductivity type different from the first conductivity type in a region on the epitaxial layer and a part of the region on the first insulating film adjacent to this region; After the step, a step of forming a second insulating film on the second epitaxial layer in a region covering the first epitaxial layer, and a step of depositing a conductor film and patterning it into a predetermined shape. By forming a third insulating film on the entire surface and patterning the third insulating film and the conductor film, a third insulating film and a conductor film are formed on the region covering the first epitaxial layer on the second insulating film. No. 1 opening, a side wall made of an insulating material is formed on the side surface of the first opening, and the second insulating film is selectively etched until the second epitaxial layer is exposed. Forming a second opening in the second insulating film;
And a step of depositing a semiconductor film containing an impurity of the first conductivity type so as to fill the second opening, and performing heat treatment to solid-phase diffuse the impurities of the semiconductor film into the second epitaxial layer. Forming a semiconductor region of a first conductivity type in the second epitaxial layer,
It is characterized by having.

[0011]

According to the semiconductor device of the present invention configured as described above, the first semiconductor region serving as the base layer covers the first semiconductor region serving as the collector region and the first semiconductor region serving as the collector region. Since it is formed on the insulating portion, it is possible to eliminate the external base region, which was necessary in the conventional case, which makes it possible to reduce the collector region, that is, the base-collector capacitance, High speed operation can be performed. Further, since the base layer covers the boundary between the collector region and the insulating portion, carriers output from the second semiconductor region serving as the emitter region hardly flow into the collector region along the boundary of the insulating portion,
Reliability can be improved.

According to the method of manufacturing a semiconductor device of the present invention configured as described above, the second epitaxial layer serving as the base layer is adjacent to the region on the first epitaxial layer serving as the collector region and this region. Since it is formed in a partial region on the first insulating film using a selective epitaxial technique for controlling lateral growth, it is possible to eliminate the external base region required in the conventional case, As a result, the collector area can be reduced, that is, the collector-base capacitance can be reduced, and high-speed operation can be performed. Further, since the base layer covers the boundary between the collector region and the first insulating film, carriers output from the semiconductor region serving as the emitter region do not flow to the collector region along the first insulating film, improving reliability. can do.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. The semiconductor device of this embodiment is an npn-type bipolar transistor, a plan view of which is shown in FIG. 2A, and a cutting line AA ′ in FIG.
1 shows a cross section taken along line B-B 'in FIG. 2A, and FIG. 2B shows a cross section taken along line B-B' in FIG.
In the semiconductor device of this embodiment, a high-concentration n-type buried layer 2 is formed on a p-type silicon substrate 1, and an n-type collector separated by a device isolation insulating film 4 is formed on the buried layer 2. Region 3 and n-type collector contact region 3a are formed.

The collector region 3 is formed on the collector region 3.
A p-type base region 5 is formed so as to cover the collector contact region 3a, and an n-type collector lead electrode 7 is formed on the collector contact region 3a.

An n-type emitter region 18 is formed on the surface of the base region 5, and an etching stopper 9 made of an insulating film is provided on the base region 5 so as to surround the emitter region 18.

A base lead electrode 10 made of polycrystalline silicon doped with, for example, p-type impurities is provided so as to be connected to the base region 5, and an n-type impurity is doped so as to be connected with the emitter region 18. An emitter extraction electrode 17 made of polycrystalline silicon is provided. The base extraction electrode 10 and the emitter extraction electrode 17 are electrically insulated by the etching stopper film 9 and the side wall 15 made of an insulating film.

An oxide film 11 and a nitride film 12 are laminated so as to cover the base extraction electrode 10 and the collector extraction electrode 7. The oxide film 11 and the nitride film 12 have a base extraction electrode 10 and a base electrode 24, respectively. An opening 21 for making contact and an opening 22 for making contact between the collector extraction electrode 7 and the collector electrode 25 are provided. Also, the emitter extraction electrode 1
An emitter electrode 23 is connected to 7. In addition, the collector contact region 3 is provided without providing the collector extraction electrode 7.
The collector electrode 25 may be directly connected to a.

In the semiconductor device of this embodiment, the base region 5 is formed on the collector region 3 so as to cover the collector region 3.
As a result, the collector region can be made smaller than in the conventional case. This makes the base
The capacitance between collectors can be reduced and high speed operation becomes possible. Further, since the base region 5 extends also over the element isolation region 4, unlike the conventional case, carriers emitted from the emitter region 18 do not flow into the collector region 3 along the boundary surface of the element isolation region 4 and reliability is improved. Will improve.

Further, in the above-mentioned embodiment, the polycrystalline silicon doped with the impurity is used for the base extraction electrode 10. However, by using the refractory metal, the base resistance can be lowered and the noise can be reduced. Can be reduced.

An embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. The manufacturing method of this embodiment is to manufacture the bipolar transistor shown in FIGS. 1 and 2. First, as shown in FIG. 3A, a high concentration is formed on a p-type silicon substrate 1 by using an ordinary diffusion technique. The n-type buried layer 2 is formed, and the n-type collector epitaxial layer 3 to be the collector region 3 and the collector contact region 3a (see FIG. 1) is grown on the buried layer 2. After that, a groove is formed in the epitaxial layer 3,
By embedding an insulating film in this groove, the element isolation region 4
Are formed (see FIG. 3A). By this element isolation region 4, the element region (active region) of the bipolar transistor is formed.
Is isolated and the collector region 3 and collector contact region are separated.

Next, as shown in FIG. 3B, the silicon crystal films 5 and 7 to be the base region 5 and the collector extraction electrode 7 (see FIG. 1) are formed on the collector region 3 and the collector contact region 3a by the selective epitaxial technique. Grow. At this time, the silicon crystal films 5 and 7 are single crystal silicon, and the single crystal silicon films 5 and 7 are laterally grown on the element isolation region 4 by a predetermined distance Y.
When the single crystal silicon films 5 and 7 are grown, a predetermined pressure,
Diborane B ₂ H ₆ is mixed at a temperature and a gas flow rate to dope the single crystal silicon films 5 and 7 to p-type. After that, the single crystal silicon film 7 is doped to be n-type. As a result, the single crystal silicon film 5 becomes a base region, and the single crystal silicon film 7 becomes a collector extraction electrode. Further, for example, by adding monogermane GeH ₄ at a predetermined pressure, temperature and gas flow rate, it is possible to form the single crystal silicon films 5 and 7 in the SiGe layer.

Next, as shown in FIG. 3C, an etching stopper film 9 is formed by depositing and patterning an insulating film on the base region (base layer) 5. The etching stopper film 9 has a large selection ratio with respect to the material of the side wall 15 described later, and is made of a material such as SiO ₂ which is removed by wet etching in order to prevent the underlying base layer 5 from being damaged. It is desirable to use.

After that, as shown in FIG. 3D, a polycrystalline silicon film 10 having a predetermined thickness is deposited by the CVD method or the like, and p-type impurities such as boron are ion-implanted. Instead of depositing the polycrystalline silicon film 10 and ion-implanting p-type impurities, a polycrystalline silicon film that is already doped with p-type impurities may be deposited. Further, instead of the polycrystalline silicon film, a film made of a refractory metal such as tungsten may be deposited. Conductive polycrystalline silicon film 1
After patterning 0, an oxide film 11 and a nitride film 12 having a predetermined thickness are sequentially deposited by the CVD method (FIG. 3).
(D)).

Next, as shown in FIG. 4A, the nitride film 1 on the element region (active region) is formed by photolithography.
2, the oxide film 11 and the polycrystalline silicon film 10 have openings 1
4 is formed. After that, as shown in FIG. 4B, an insulator made of, for example, SiN is deposited to a predetermined thickness, and is etched using anisotropic etching such as RIE to form a side wall 15 in the opening 14. Then, Fig. 4
As shown in (c), the exposed etching stopper film 9 is selectively removed by wet etching or the like to form an opening 16 for forming an emitter region. Thereafter, as shown in FIG. 4D, a polycrystalline silicon film 17 is deposited on the entire surface, n-type impurities such as arsenic are ion-implanted, and heat-treated to diffuse into the base epitaxial layer 5 to form the emitter region 18. To form.

The polycrystalline silicon film 17 is deposited and n
Instead of implanting n-type impurities, a polycrystalline silicon film already doped with n-type impurities may be deposited, or a silicon crystal doped with n-type impurities may be epitaxially grown.

After that, the polycrystalline silicon film 17 is patterned to form the emitter extraction electrode 17. Then, an insulating film (not shown) is deposited on the entire surface by a known technique, an opening is provided in the insulating film, the nitride film 12, and the insulating film 11, and a metal film (not shown) is deposited so as to fill the opening. Then, by patterning this metal film, an emitter electrode, a base electrode, and a collector electrode are formed.

In the manufacturing method of this embodiment, by forming the base layer 5 by the epitaxial technique capable of controlling the lateral growth, it is possible to eliminate the external base region required in the conventional case. Therefore, the collector region 3 can be made smaller than in the conventional case. As a result, the base-collector capacitance can be reduced and high speed operation can be performed. Further, since the base layer 5 covers the boundary between the collector region 3 and the device isolation region 4, carriers from the emitter region 18 do not flow into the collector region 3 along the boundary surface of the device isolation region 4.
Reliability is improved.

Although the etching stopper film 9 is formed of an insulating material in the above embodiment, it is formed of an oxide film 9a containing impurities of the same type as the impurities forming the base region 5, as shown in FIG. By adding a heat step,
The solid phase diffusion layer 6 may be formed in the base region 5. As a result, the base resistance can be made lower than that in the above embodiment, noise can be reduced, and circuit performance can be improved. The heating step may be combined with the heating step for forming the emitter region.

Although the npn type bipolar transistor has been described in the above embodiment, the pnp type bipolar transistor can be manufactured in the same manner.

[0030]

As described above, according to the present invention, it is possible to obtain a highly reliable device capable of high speed operation.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a configuration diagram of an embodiment of a semiconductor device according to the present invention.

FIG. 3 is a cross sectional view of a manufacturing process of the embodiment of the method for manufacturing the semiconductor device according to the present invention.

FIG. 4 is a sectional view of a manufacturing process of the embodiment of the method for manufacturing the semiconductor device according to the present invention.

FIG. 5 is a sectional view showing the configuration of another embodiment of the semiconductor device according to the present invention.

FIG. 6 is a configuration diagram of a conventional semiconductor device.

FIG. 7 is a configuration diagram of a conventional semiconductor device.

[Explanation of symbols]

1 p-type silicon substrate 2 n ⁺ buried layer 3 collector epitaxial layer (collector region) 3a collector contact region 4 element isolation region 5 base region (base layer) 5a external base region 5b internal base region 6 solid phase diffusion region 9 etching stopper film 9a Oxide film containing impurities 10 Polycrystalline silicon film (base extraction electrode) 11 Oxide film 12 Nitride film 14 Opening 15 Side wall 16 Opening 17 Emitter extraction electrode (polycrystalline silicon film) 18 Emitter region 21, 22 Opening 23 Emitter electrode 24 Base Electrode 25 Collector electrode

Claims (5)

[Claims] 1. A first semiconductor region of a first conductivity type formed in a same layer on a semiconductor substrate so as to be surrounded by an insulating portion, and the first semiconductor region so as to cover the first semiconductor region. A first semiconductor layer of a second conductivity type different from the first conductivity type formed so as to extend to the semiconductor region and at least a region of the insulating portion adjacent to the first semiconductor region; A second semiconductor region of the first conductivity type formed on the surface region of the first semiconductor layer on the first semiconductor region, and a semiconductor device. 2. A first insulating film formed on the first semiconductor layer so as to surround the second semiconductor region, and formed so as to be electrically connected to the first semiconductor layer. A lead layer and a second semiconductor layer of a first conductivity type formed on the second semiconductor region so as to be electrically insulated by an insulating film. The semiconductor device according to claim 1. 3. The first insulating film is an oxide film containing impurities of a second conductivity type, and the first semiconductor layer has a diffusion layer formed by solid phase diffusion from the oxide film. The semiconductor device according to claim 2, wherein: 4. A step of forming a first epitaxial layer of the first conductivity type on a semiconductor substrate on which a buried layer of the first conductivity type is formed, and forming a groove in the first epitaxial layer, Isolation of the first epitaxial layer by embedding a first insulating film in the groove; and a region on the first epitaxial layer and a region on the first epitaxial layer using a selective epitaxial technique for controlling lateral growth. A step of forming a second epitaxial layer of a second conductivity type different from the first conductivity type in a partial region on the adjacent first insulating film, and, after this step, the second epitaxial layer Forming a second insulating film on a region of the layer covering the first epitaxial layer, and forming a third insulating film on the entire surface after depositing a conductor film and patterning it into a predetermined shape When, Patterning the third insulating film and the conductor film to form a first opening on a region of the second insulating film that covers the first epitaxial layer; and Forming a sidewall made of an insulating material on a side surface of the opening; and selectively etching the second insulating film until the second epitaxial layer is exposed to form a second opening in the second insulating film. And a step of depositing a semiconductor film containing a first conductivity type impurity so as to fill the first and second openings, and a heat treatment is performed to remove impurities of the semiconductor film from the second film. And a step of forming a first conductivity type semiconductor region in the second epitaxial layer by solid-phase diffusion into the epitaxial layer. 5. The second insulating film is made of an oxide film containing impurities of the second conductivity type, and a diffusion layer is formed in the second epitaxial layer by solid phase diffusion from the oxide film by heat treatment. The manufacturing method according to claim 4, further comprising: