JPH0935201A - Reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a clock corresponding to a frequency difference in regenerative signals between heads by setting a value of reference data in accordance with an azimuth of the head at the time of controlling a clock generating operation by using a comparision result between a clock count value and the reference data value. SOLUTION: A phase error between the regenerative signal inputted to an input terminal 101 and a VCO 105 is inputted to a loop filter 103 to be averaged, and then a signal having a voltage of canceling the phase error between the regenerative signal and the output of the VCO 106 is inputted to the VCO 106. Then, the output of the VCO 106 is inputted to a count circuit 118, and for a certain time, i.e., a time commensurate with a period for tracing one track by a rotary head, the number of clocks outputted from the VCO 106 is counted by the circuit 118, and its result is outputted to a positive input terminal of a digital subtractor 119. The output of a register 121 or a register 122 to be supplied via a switch 123 is inputted to a negative input terminal of the subtractor 119.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus, and more particularly, to an apparatus for reproducing a clock from a digital signal reproduced from a recording medium.

[0002]

2. Description of the Related Art It has been known that a device for transmitting (recording / reproducing) data at high speed, such as a digital VTR, uses a phase locked loop (hereinafter, PLL) when extracting a clock from a received data sequence. I have.

FIG. 13 shows the configuration of such a PLL circuit.

In FIG. 13, a signal reproduced from a tape (not shown) is input to the phase comparator 102, and the phase difference from the clock output from the voltage controlled oscillator (hereinafter VCO) 106 is detected. The output of the phase comparator 102 is input to the VCO 106 via the loop filter 103 and outputs a signal having a frequency corresponding to the output voltage of the loop filter as a clock.

That is, when the phase of the reproduced digital signal changes due to uneven rotation of the rotary head (not shown) or expansion / contraction of the tape, the phase difference between the phase difference with the generated clock is detected by the phase comparator 102.
Detected by the VCO 106 via the loop filter 103.
By controlling the oscillation frequency by feeding back to, it is possible to generate a clock that follows the phase fluctuation of the reproduced digital signal.

[0006]

Now, consider the case of performing high-speed reproduction, that is, so-called picture search.

In the digital VTR, since high density recording is usually performed, guard bandless recording is performed by heads having different azimuth angles.

Therefore, although there is no problem during normal reproduction, the speed component in the direction orthogonal to azimuth differs depending on the azimuth angle during picture search. For example, the frequency of the reproduction signal reproduced from the plus azimuth head and the minus azimuth Depending on the search speed, the frequency of the reproduction signal reproduced from the head of the one becomes farther away from the one having a higher frequency and the other becomes closer to the lower frequency.

Therefore, conventionally, in the case of two types of azimuth, the frequency of the reproduction signal is normally reproduced by controlling the rotational speed of the drum so that the average value of the relative speeds of the two heads with respect to the tape becomes constant. I was trying to get closer to the frequency of time.

However, even with such control, the frequency difference of the reproduced signal due to the two azimuth differences becomes ± 1% of the oscillation frequency in the 100 times search, for example, when the search becomes faster, and the PLL is locked. There was a problem of getting out of the range.

Therefore, an accurate clock cannot be generated during a high speed search, and a good reproduction signal cannot be obtained.

Further, only a low speed search can be performed in order to obtain a good reproduction signal.

In view of the above problems, it is an object of the present invention to provide an apparatus capable of obtaining a clock that accurately follows the reproduction signal frequency even in the case of high speed search or the like.

[0014]

SUMMARY OF THE INVENTION In order to solve the conventional problems and achieve the above object, the present invention provides a reproducing means for reproducing a signal from a recording medium by a plurality of heads having different azimuth angles. Generating means for generating a clock phase-synchronized with the reproduction signal; counting means for counting the clock generated by the generating means; comparing means for comparing the count value of the counting means with the value of the reference data; The control means controls the generating operation of the generating means by using the output of the means, and the setting means for setting the value of the reference data according to the azimuth angle of the head.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, the case where the present invention is applied to a digital VTR will be described. FIG. 1 is a block diagram showing the structure of a reproducing system of such a digital VTR.

In FIG. 1, the magnetic tape 1 is alternately traced by the magnetic heads 3a and 3b mounted on the rotary drum 2 with a phase difference of about 180 ° to reproduce a digital signal, and via the switch SW. The signal is output to the amplifier 4, amplified here, and output to the reproduction equalization circuit 5. Although the video signal for one frame is recorded on 10 tracks in the digital VTR in the present embodiment, it is needless to say that it is not limited to this.

The reproduction equalization circuit 5 is an equalization circuit for compensating for signal characteristic changes in the magnetic recording / reproduction system, and performs so-called integral equalization. The equalized reproduction signal is output to the A / D converter 6.

Sampled by the A / D converter 6,
The signal converted into the digital signal is used in the clock generation circuit 1
It is output to 4 and is delayed by 2 clocks by the delay circuit 7, and subtracted from the original signal by the subtractor 8. Here, converting the reproduced digital signal into a digital signal by the A / D converter 6 means that even if the reproduced signal supplied from the switch SW is a digital signal, its amplitude varies in an analog manner. The A / D converter 6 again converts a signal having such an analog amplitude into a digital signal of one sample and a plurality of bits, and the Viterbi decoding circuit 9 at the subsequent stage converts the signal to "1" or "0". It is restored to a binary signal.

By such a subtracting operation, the integral equalized waveform is converted into a waveform having a PR (1,0, -1) characteristic, and the Viterbi decoding circuit 9 performs maximum likelihood decoding. PR (1,0,
The combination of the -1) method and Viterbi decoding is often used in a digital VTR or the like that uses high-density magnetic recording, avoids poor low-frequency characteristics (S / N, waveform distortion, etc.) of the magnetic recording system, and prevents transmission errors. Can be kept to a minimum.

The clock generation circuit 14 generates an operation clock for each part of the device in addition to the clock used in the A / D converter 6, and its detailed operation will be described later.

The reproduced data reconstructed by the Viterbi decoding circuit 9 is corrected by the error correction circuit (ECC circuit) 10 using the parity data added at the time of recording to correct the error generated in the transmission path, and is output to the image decoding circuit 11. It The image decoding circuit 10 expands the information amount of the reproduction data compressed at the time of recording and outputs it to the D / A converter 12. D / A converter 12
Converts the input digital data into analog data and outputs the analog data via the output terminal 13.

A head switching signal generation circuit 15 generates a switching signal (hereinafter referred to as SWP) for the heads 3a and 3b on the basis of a signal (PG) indicating the rotational phase of the rotary drum (rotary head), and switches SW and Output to the clock generation circuit 14.

Now, the relationship between the head and the tape and the change in the frequency of the reproduction signal during the search will be described.

When azimuth recording is performed in which the gaps of the heads 3a and 3b in FIG. 1 are inclined at different angles with respect to the head scanning direction, the following unique phenomenon is observed.

FIG. 2 is a view of the tape 1 as viewed from the magnetic medium surface. The tape running direction, the head scanning direction, and the head 3 are shown.
It is assumed that the azimuth angle of a is −α °, the azimuth angle of the magnetic head 3b is + α °, and the track inclination angle is θ °, as shown in the figure.

At the time of normal reproduction (playback is performed by running the tape at the same speed as during recording) with respect to the track recorded at the track inclination angle θ ° during recording, the head 3a scans the track 1A of negative azimuth. , The traveling speed of the tape 1 and the rotational speed of the rotary drum 2 are controlled so that the head 3b scans the plus azimuth track 1B.

Next, when performing a search in the forward direction, the loci scanned by the heads 3a and 3b are as shown by the broken lines in FIG. In this case, since the scanning direction of the heads 3a and 3b and the running direction of the tape 1 are forward, the heads 3a and 3b are
The relative speed between b and tape 1 becomes smaller than that during normal reproduction. Therefore, the frequency of the reproduction signal becomes low.

Further, enlarged views of the head and the track at this time are shown in FIGS.

In FIGS. 4 and 5, the line in each track indicates each bit of the recorded data, and Pa and Pb.
Indicates the pitch of bit intervals in tracks 1A and 1B, respectively.

As shown in FIG. 4, during normal reproduction, the pitch Pa of the reproduction bit interval of the head 3a which is minus azimuth and the pitch Pb of the reproduction bit interval of the head 3b which is plus azimuth were equal to each other, whereas in the positive direction. At the time of searching, as shown in FIG.
A difference occurs between a and Pb, and the frequency of the reproduction signal from the negative azimuth head 3a becomes higher than the frequency of the reproduction signal from the positive azimuth head 3b.

FIG. 6 shows the frequency of the reproduced signal with respect to the change in the search speed when the drum rotation speed is constant.

In FIG. 6, in the search in the forward direction, the frequency of the reproduction signal of the minus azimuth head rises at a steeper angle than the frequency of the reproduction signal of the plus azimuth head, and both frequencies increase as the speed increases. In addition, the negative search shows almost the opposite tendency.

In the present embodiment, an apparatus for generating an optimum clock that follows the frequency of the reproduction signal from each head even when there is a difference in the frequency of the reproduction signal due to the difference in azimuth of the head will be described.

FIG. 7 shows the clock generation circuit 14 shown in FIG.
3 is a block diagram showing a configuration example of FIG.

In FIG. 7, the phase error between the reproduction signal input to the input terminal 101 and the VCO 106 is input to the loop filter 103 and averaged to reproduce the reproduction signal and VCO1.
The PLL loop in which a signal having a voltage that cancels the phase error with the output of 06 is input to the VCO 106 is the same as the above-described conventional example.

The features of the present embodiment will be described below.

The output of the VCO 106 oscillated as described above is input to the counting circuit 118. Counting circuit 1
Reference numeral 18 denotes a period within a certain time, for example, a period corresponding to a period in which the rotary head traces one track (hereinafter referred to as Ttr, which is 1/300 seconds here: shown in FIG. 8A).
The number of clocks output from the VCO 106 is counted, and the result is output to the positive input terminal of the digital subtractor 119. The output of the register 121 or the register 122 supplied via the switch 123 is input to the negative input terminal of the subtractor 119.

The register 121 is a register for plus azimuth, and the register 122 is a register for minus azimuth, which is output to the subtractor 119 via a switch 123 which is switched according to the head reproducing the signal.

Reference numeral 124 denotes a timing generation circuit, which receives a head switching signal (hereinafter referred to as SWP) output from the head switching signal generation circuit 15 of FIG.
The timing signals shown in (b) to (e) are generated.
Note that FIG. 8A is a diagram showing a state of the envelope of the reproduction signal.

The counting circuit 118 is reset at the timing shown in FIG. 8B, and counts the number of clocks in the period for tracing one track.

Further, the switch 123 switches according to the signal shown in FIG. 8 (c). That is, in FIG. 8C, it is connected to the register 121 side during the high level and connected to the register 122 side during the low level.

First, during normal reproduction, the speed setting circuit 12
The register rewriting circuit 12 outputs a signal indicating that by 3
6 is output. During normal reproduction, the register rewriting circuit 126 sets fce as the center frequency of the clock extracted from the reproduced digital signal containing jitter.
The same value of nt × Ttr is written in each register 121 and 122. Therefore, if the VCO 106 is oscillating at fcent, the output of the subtractor 119 becomes zero.

Further, at the time of search reproduction, similarly, the speed setting circuit 125 outputs a signal indicating the running speed of the tape to the register rewriting circuit 126. Then, the register rewriting circuit 126 determines a value corresponding to the change in the frequency shown in FIG. 6 for each head according to the input tape running speed, and writes it in the registers 121 and 122.

Therefore, the subtractor 119 outputs the frequency difference between the reproduced signal and the generated clock in consideration of the influence of the azimuth angle of the reproducing head even during the search reproduction.

The output of the subtractor 119 is adjusted in level by the coefficient unit 120 as described later, and is output to the negative input terminal of the digital subtractor 110.

On the other hand, the output of the loop filter 103 is output to the adder 104 and the low pass filter (hereinafter referred to as LPF) 108 as described above. LPF10
Reference numeral 8 denotes a filter as a prefilter for sampling by the register 109, and the output of the register 109 is output to the positive input terminal of the subtractor 110. Here, the register 109 has the timing shown in FIG.
The output of the LPF 108 is sampled at the timing of t.

The subtractor 110 subtracts the output of the coefficient unit 120 from the output of the LPF 108 and outputs it to the integrator 111.

The integrator 111 is an adder 112 and a limiter 1
13, registers 115, 116 and switches 114, 1
It is composed of 17. Then, each time a clock is input to the registers 115 and 116, the value input from the subtractor 113 is added until the upper and lower limit values are reached.

Here, the register 115 is a register for plus azimuth, and the register 116 is a register for minus azimuth, and the value output from the switch 114 according to the clocks shown in FIGS. 8D and 8E, respectively. Written.

Further, the switches 114 and 117 are switched according to the signal shown in FIG. 8C, like the switch 123 described above. That is, when the signal in FIG. 8C is high level, it is connected to the register 115 side, and when it is low level, it is connected to the register 116 side.

In this way, by controlling the rewriting operation of the register according to the head reproducing the signal,
The registers 115 and 116 perform the rewriting operation only when the reproduction signal from the corresponding azimuth head is obtained, and hold the value in other periods.

The output of the integrator 111 is output to the adder 104.

Next, the operation of clock generation in this embodiment will be described.

First, in the portion where the reproduction envelope in FIG. 8 is obtained, the phase of the reproduction signal and the output clock of the VCO 106 is a phase comparison circuit (Phase Comparator: P).
C) 102, compared by the loop filter 103, averaged and output to the VCO 106 via the adder 104, and the oscillation output signal of the VCO 106 is output from the output terminal 107 to the A / D converter 6 It is output as the clock used in.

Next, the reproduction envelope is obtained,
That is, a case will be described in which the oscillation frequency of the VCO is about to decrease due to some external factor while the phase comparison circuit 102, the loop filter 103, and the PLL of the VCO 106 are phase-locked during the Ttr period. In this case, since a phase difference occurs between the input signals of the phase comparison circuit 102 during the period when the reproduction envelope is obtained, the output voltage of the phase comparison circuit 102 decreases and the output voltage of the loop filter 103 increases. Then, control is performed so that the output clock of the VCO 106 and the clock of the reproduction signal have the correct phase.

In this way, the phase error with the reproduced clock due to the error in the oscillation frequency of the VCO 106 is corrected,
In this state, the output of the loop filter 103 has also risen and is out of the center of the lock range of the PLL. Therefore, if it is attempted to further correct the phase error with the reproduced clock from this state, the PLL is likely to be out of lock with respect to the phase change.

Therefore, in the present embodiment, the path of the LPF 108 to the integrator 111 to the adder 104 detects the phase error with a time constant slower than that of the loop of the PLL to detect the tendency of the output of the loop filter 103. , Loop filter 1
Loop filter 10 by adding to the output of 03.
The output of the loop filter 103 is always PLL by making the output of the 3rd output biased by the output of the integrator 111.
It holds the center of the rock range. Hereinafter, this operation will be described.

Since the register 109 operates at the timing of Ttr, that is, 300 Hz as described above, the LPF 108 operates.
The cut-off frequency is 150 Hz, and the response speed is very low. Therefore, the output of the LPF 108 does not change much even in the period without the reproduction envelope, and when the output voltage of the loop filter 103 increases due to the phase error between the VCO 106 and the reproduction signal, the output of the register 109 also increases accordingly. .

Therefore, the register 11 in the integrator 111 is
The value of 5,116 changes in the positive direction, resulting in integrator 1
The output from 11 to the adder 104 becomes large. Integrator 1
Since the output of 11 is equal to the error signal output from the loop filter 103 during the Ttr period, the loop filter 103
The error signal corresponding to the output from can be separated by the integrator 111. That is, the loop filter 10
Where the integrator 111 is to be controlled by increasing the output of 3
Is controlled by the output of the loop filter 103.
Can always be kept at the center of the lock range of the PLL.

When the output of the adder 104 becomes large, VC
The oscillation frequency of O106 becomes high as described above, and when the phase difference between the reproduction signal and the clock disappears, the registers 115 and 116 do not change. During this time, the VCO
Since the oscillation frequency of 106 does not change, the error signal is not output from the subtractor 119, and thus the output of the register 109 is directly output as the output of the subtractor 110.

Here, the count circuit 118 and the register 1
The operation clock of 09 is set to the Ttr period, that is, 300 Hz. This is because the output of the integrator 111 is added to the adder 104 in the part without the reproduction envelope to obtain the part with the envelope, that is, the reproduction signal. This is to prevent the disturbance of the PLL due to the instantaneous change of the input voltage of the VCO 106 in the existing portion. In addition, in the case where the envelope is always obtained, if the operation is performed during the reproduction of a signal that is not a valid signal (for example, a video signal or an audio signal), an image or an audio based on the frequency fluctuation is generated. Disturbance can be minimized.

Next, the frequency control by the counting circuit 118 and the registers 121, 122 will be described. It should be noted that this system changes the value of the registers 121 and 122 by changing the values of the registers 121 and 122 when the frequency of the signal that will be reproduced from the magnetic tape 1 changes as described above.
It is used to change the center frequency of the CO 106.

As described above, during the Ttr period, the counting circuit 118 counts the clocks output from the VCO 106 and outputs the count value at the timing when the timing signal Ttr is input. The register 12 supplied by the subtractor 119 via the switch 123
The output of 1,122 is subtracted. The output of the subtractor 119 is averaged by the integrator 111 via the coefficient unit 120 and the subtractor 110, and is output to the VCO 106 via the adder 104, forming a feedback loop. That is, the feedback loop automatically controls the oscillation frequency of the VCO 106, so-called AFC operation.

Further, in the present embodiment, as described above, the value to be written in the register is changed according to the two heads having different azimuths, and the value is selectively supplied to the subtractor 119 according to the timing when each head traces the tape. By supplying, the center frequency of the VCO 106 can be automatically controlled to a frequency corresponding to each head in consideration of the azimuth angle.

Here, the gain of the coefficient unit 120 is set so that the same gain is obtained between the start and the goal when the exit of the loop filter 103 is the start and the subtractor 110 is the goal. It is possible to prevent the influence of the phase fluctuation / frequency fluctuation from reaching the integrator 111.

That is, the gain of the path of the loop filter 103-adder 104-D / A converter 105-VCO 106-counting circuit 118-subtractor 119-coefficient unit 120 is the same as that of the loop filter 103-LPF 108-register 109. Set so that it is equal to the gain.

As described above, in the present embodiment, the phase comparison circuit 102 within the clock Ttr period.
~ Loop filter 103 ~ Adder 104 ~ VCO 106
Of the loop filter by performing the normal phase control by the PLL of FIG. 1 to obtain the clock, and operating the feedback loop of the LPF 108-register 109-integrator 111-adder 104-VCO 106 at each timing of the clock Ttr. The output tendency of 103 is detected, and the loop filter 10 by the phase error between Ttr is detected.
By compensating for the deviation of the output voltage of 3 (the input voltage of the VCO 106), it becomes possible to always keep the PLL loop at the center of the lock range. Therefore, it is possible to prevent the PLL from being easily detached with respect to the change in the oscillation frequency of the VCO 106.

Further, the counter 118 causes the VCO 106 to
The output of the VCO 106 is counted and the outputs of the registers 121 and 122 are subtracted to detect an error in the oscillation frequency of the VCO 106 in the period Ttr, and this is detected.
Since the output subtracted from the output of No. 3 is integrated to obtain the average value of the frequency error and the oscillation frequency of the VCO 106 is controlled, it is possible to prevent the oscillation frequency of the VCO from changing due to temperature change or temporal change. it can.

Further, as described above, the register for setting the oscillation target frequency and the register for integration are provided in accordance with the azimuth of the head, so that the frequency of the reproduction clock is changed due to the difference in the azimuth angle during search. Is P
It is possible to generate an appropriate clock according to the difference in the frequency of the reproduction signal between the heads without deviating from the lock range of LL.

In this embodiment, the output of the loop filter 103 is averaged by the LPF 108 and integrated by the integrator 111 to detect the tendency in the output of the loop filter 103. For example, the MSB of the output data of the register 109 is detected. Can be detected by counting with an up-down counter, and other methods can also be used.

Next, as a second embodiment of the present invention, Ttr
A case will be described in which the operation performed by the clock is performed by program processing of the microcomputer.

FIG. 9 is a diagram showing the configuration of a clock generation circuit as a second embodiment of the present invention.

In FIG. 9, the output of the LPF 108 is output to the input port of the microcomputer 202, and V
The output of the CO 106 is frequency-divided by the prescaler 201 and output to the built-in counter of the microcomputer 202. In this case, the counter can be externally attached, but the number of parts can be further reduced by using a microcomputer with a built-in counter.

Here, the operation of the microcomputer 202 will be described with reference to the flowchart of FIG. Note that the registers A and B in FIG. 9 have the same functions as the registers 121 and 122 in FIG. 7, respectively, and the registers C and D have the same functions as the registers 115 and 116.

First, Ttr is input from the timing generation circuit 124 at the timing of the break of the envelope.
The input of tr starts the operation of the microcomputer 202.
When Ttr is input, first, the value of the counter is read (step S1), and further, the azimuth of the head currently reproducing the signal is supplied from the timing generation circuit 124 to the SWP.
It is determined by (step S2). Then, in the case of the plus azimuth head, that is, the head 3b, the value of the register A is subtracted from the count value (step S3), and in the case of the minus azimuth head, that is, the head 3a, the value of the register B is subtracted from the count value. Yes (Step S
4). Next, a coefficient corresponding to the coefficient unit 120 in FIG. 7 is multiplied (step S5), and further multiplied by -1 (step S6), and then the loop filter output also output from the LPF 109 at the timing of Ttr is added (step S).
7).

Then, as in step S2, the azimuth of the head is confirmed (step S8), and in the case of plus azimuth, this value and the value of the register C are added (step S6), and minus azimuth is determined. In this case, the value of the register D is added (step S10).

Then, it is judged whether or not the added result exceeds the limit range (step S11), and if it exceeds the limit range, it is replaced with the limit value and stored in the registers C and D (steps S12, S13, S14). , S1
5, S16), and outputs this limit value.

If the limit value is not exceeded, the value is stored in the register A and output (steps S13, S14, S15, S16).

As described above, in the present embodiment, Ttr
Since the deviation of the output voltage of the loop filter 103 due to the phase error between the two is compensated by the microcomputer, the number of parts can be further reduced.

Since the operation of compensating for the deviation of the input voltage of the VCO 106 due to the phase error between Ttr as described above has a slow operation speed of 300 Hz, it is configured to be performed during the idle time of other operations of the microcomputer. As a result, it is possible to increase the number of parts.

Further, in the digital VTR shown in FIG. 1, the PR (1,0, -1) process is performed after the A / D conversion, but the present invention is not limited to this and, for example, after being reproduced. Alternatively, the reproduction equalization circuit may perform the equalization process.

In the above-mentioned embodiment, the device for reproducing the signal by alternately tracing the tape by the two heads mounted on the drum with a phase difference of 180 ° and having different azimuth angles has been described. In addition to this configuration, two heads with different azimuth angles are provided close to each other,
A digital VTR in which a tape is simultaneously traced by these two heads to record / reproduce signals is known.

The case where the present invention is applied to such a VTR will be described below.

FIG. 11 is a block diagram showing the structure of the present embodiment, and the same components as those in FIG. 1 are designated by the same reference numerals.

In FIG. 11, heads 3a, 3b and 3c, 3d having different azimuth angles are provided close to each other on the drum 2. Also, the heads 3a, 3b
And 3c and 3d are arranged with a phase difference of 180 °. The heads 3c and 3d have the same azimuth angle as the heads 3a and 3b.

The signals reproduced by the heads 3a and 3c are supplied to the amplifier 4a through the switch SW1 and amplified, and then equalized by the reproduction equalization circuit 5a. Then, the A / D converter 6a uses the clock from the clock generation circuit 14 to convert it into a digital signal of one sample multiple bits again, and supplies the digital signal to the clock generation circuit 14, the delay circuit 7a, and the subtractor 8a.

On the other hand, the signals reproduced by the heads 3b and 3d are supplied to the amplifier 4b through the switch SW2, amplified, and then equalized by the reproduction equalization circuit 5b. The A / D converter 6b uses the clock from the clock generation circuit 14 to convert the digital signal into a digital signal of one sample multiple bits again, and supplies the digital signal to the clock generation circuit 14, the delay circuit 7b, and the subtractor 8b.

These reproduction equalization circuits 4a to amplifiers 5a to A
The system of the / D converter 6a to the delay circuit 7a to the subtractor 8a and the system of the reproduction equalization circuit 4b to the amplifier 5b to the A / D converter 6b to the delay circuit 7b to the subtractor 8b have different azimuth angles. It is a system for processing the signal reproduced from the head, and can be designed with optimum equalization characteristics and signal processing characteristics according to the head of each azimuth.

PR (1,2) output from the delay circuit 8b
The signals having the 0, -1) characteristic are restored to 1, 0 signals, that is, 1-sample 1-bit signals by the Viterbi decoding circuits 9a, 9b, respectively.

Here, the output of the Viterbi decoding circuit 9b is delayed by the delay circuit 17 by a time corresponding to the time for reproducing one track, and is output to the switch SW3.

The switch SW3 switches according to the SWP output from the head switching signal generation circuit 15, and selectively outputs the output signal from the Viterbi decoding circuit 9a and the output signal from the delay circuit 17 to the ECC circuit 10. To do.

The following operation is similar to that of the above-mentioned embodiment.

Next, the clock generation circuit 1 in FIG.
4 will be described.

In this embodiment, in order to generate a clock synchronized with the signal reproduced from the head of each azimuth, two systems of the clock generation circuit shown in FIG. 7 are provided for each azimuth.

That is, in FIG. 12, the overall operation in each system is almost the same as that in FIG. 7, but in FIG. 12, the signal output from the A / D converter 6a is input to the terminal 101, A clock synchronized with the reproduction signal from the minus azimuth head is output from the terminal 107. The signal output from the A / D converter 6b is input to the terminal 101 ', and a clock phase-synchronized with the reproduction signal from the positive azimuth head is output from the terminal 107'.

Therefore, in FIG. 12, the register 1
21 and 122 are provided in separate systems, and the register 115
And 116 were provided in separate systems.

That is, in FIG. 12, by the register rewriting circuit 126, as shown in FIG. 6, the register 121 is written with a value according to the frequency fluctuation with respect to the reproduction speed of the reproduction signal by the head of minus azimuth, Further, the register 122 is written with a value according to the fluctuation of the frequency with respect to the reproduction multiple speed of the reproduction signal by the plus azimuth head.

At this time, the timing generation circuit 124
8E, the signal shown in FIG. 8E is output to the register 115, and the output signal of the limiter 113 is written to the register 115 at this timing. Further, the signal shown in FIG. 8D is output to the register 116, and the register 116 outputs the limiter 1 at this timing.
The output signal of 13 'is written.

As described above, in this embodiment, a plurality of clock generation circuits are provided for heads of different azimuths, and in each system, a register for setting the oscillation target frequency and a register for integration as described above. Even when the tape is traced by a plurality of heads having different azimuth angles at the same time to reproduce the signal, the frequency of the reproduction clock is locked by the PLL due to the difference in the azimuth angle during search. It is possible to generate an appropriate clock according to the difference in the frequency of the reproduction signal between the heads without deviating from the range.

In the above embodiment, the reproduction signal and VC
Although the digital phase comparison circuit is used to detect the phase error between the output of O and the output of O, any means may be used as long as it detects the phase error between the output of the reproduction signal and the output of the VCO.

Further, in the above-mentioned embodiment, the case where the present invention is applied to the digital VTR has been described, but the present invention is not limited to this, and a system for transmitting / recording / reproducing a digital signal, for example, an electric wave or an optical signal is used. It is also applicable to communication by means of the like, optical disks, etc., and has the same operation and effect.

[0103]

As apparent from the above description, in the present invention, when the clock generation operation is controlled by using the result of comparison between the clock count value and the reference data value, the reference data Since the value is set according to the azimuth angle of the head, the frequency of the reproduction clock does not deviate from the PLL lock range due to the difference in the azimuth angle during search, and the frequency of the reproduction signal between the heads is An appropriate clock can be generated according to the difference.

Further, in another invention of the present application, the detection output of the frequency error of the clock output from the PLL and the output of the loop filter are integrated, and the integrated output and the output of the loop filter are added to perform voltage-controlled oscillation. Since the frequency error detection operation is changed according to the azimuth angle of the head while inputting to the means, it is possible to keep the oscillation frequency of the voltage controlled oscillation means stable without being affected by temperature changes, changes over time, and the like. it can.

Further, it is possible to always keep the loop of the PLL at the center of the lock range and generate a clock having a frequency according to the reproduction signal from each head regardless of the difference in the azimuth angle of the head.

Further, according to still another invention of the present application, since a plurality of generating means for generating clocks which are phase-synchronized with the plurality of heads and have different frequencies are provided, the plurality of heads can be used to control the recording medium from the recording medium. Even when the signals are reproduced at the same time, it is possible to generate the optimum clock for processing the reproduced signals from the respective heads.

Therefore, in any of the inventions of the present application,
A good signal can be reproduced from all heads.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a track and a head in the embodiment of the invention.

FIG. 3 is a diagram showing a relationship between a track and a head at the time of searching in the embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between recording data and a head during normal reproduction.

FIG. 5 is a diagram showing a relationship between print data and a head during a search.

FIG. 6 is a diagram showing a change in frequency of a reproduction signal with respect to a tape transport speed.

FIG. 7 is a diagram showing a configuration of a clock generation circuit in FIG.

8 is a timing chart for explaining the operation of the circuit of FIG.

9 is a diagram showing another configuration of the clock generation circuit in FIG.

FIG. 10 is a flowchart for explaining the operation of the circuit shown in FIG.

FIG. 11 is a block diagram showing another configuration of a digital VTR as an embodiment of the present invention.

12 is a diagram showing the configuration of the clock generation circuit in FIG. 11. FIG.

FIG. 13 is a diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 102 phase comparison circuit 103 loop filter 106 voltage controlled oscillation circuit 118 count circuit 111 integrator 125 speed setting circuit 126 register rewriting circuit 202 microcomputer

Claims (22)

[Claims] 1. A reproducing means for reproducing a signal from a recording medium by a plurality of heads having different azimuth angles, a generating means for generating a clock phase-synchronized with the reproduced signal, and a clock for generating the clock by the generating means. Counting means, comparing means for comparing the count value of the counting means with the value of the reference data, control means for controlling the generating operation of the generating means using the output of the comparing means, and the azimuth angle of the head. And a setting means for setting the value of the reference data according to the above. 2. The clock generating means includes a phase difference detecting means for detecting a phase difference between the clock and the reproduction signal, a loop filter for inputting an output of the phase difference detecting means, and an output of the loop filter. The reproducing apparatus according to claim 1, further comprising an oscillating unit that outputs a signal of a corresponding frequency as the clock. 3. The control means detects a tendency of an output of the first addition means for adding the output of the comparison means and an output of the loop filter, and shows the tendency. A detecting means for outputting a signal; and a second adding means for adding the output of the loop filter and the output of the detecting means, wherein the output of the second adding means is input to the voltage controlled oscillation means. The playback device according to claim 2, wherein the playback device is a playback device. 4. The detecting means includes a low-pass filter that suppresses a high-frequency component of the output of the loop filter, and an integrating means that integrates the output of the low-pass filter. The playback device according to 1. 5. An output of the second adding means is a digital signal, and a D / A converting means for converting the output of the second adding means into an analog signal and outputting the analog signal to the oscillating means is provided. The playback device according to claim 3, wherein the playback device is a playback device. 6. The reproducing apparatus according to claim 3, wherein the detecting unit detects the tendency by accumulating outputs of the second adding unit. 7. The detecting means holds the outputs of the first adding means, respectively, and holds a plurality of holding means according to the azimuth angle, and outputs of the plurality of holding means and the first adding means. 4. The third addition means for adding the output and the third addition means, wherein the second addition means adds the output of the third addition means and the output of the loop filter. Playback device. 8. The reproduced signal is a signal whose amplitude fluctuates in an analog manner, and the reproduced signal is sampled using the clock generated by the generating means and converted into a digital signal of one sample multi-bit A. The reproducing apparatus according to claim 1, further comprising a / D converting unit. 9. The reproducing apparatus according to claim 1, wherein the setting unit further changes a value of the reference data according to a transfer speed of the recording medium. 10. The control means controls the generating means to generate clocks having different frequencies according to the azimuth angle of the head.
A playback device according to claim 1. 11. The reproducing apparatus according to claim 10, wherein the reference data is data for setting a frequency of the clock to a desired frequency. 12. A reproducing means for reproducing a signal from a recording medium by a plurality of heads having different azimuth angles, a generating means for generating a clock phase-synchronized with the reproduced signal, and a frequency detecting means for detecting a frequency of the clock. And a means for controlling the generating operation of the generating means using the output of the frequency detecting means, and a means for controlling the detecting operation of the frequency detecting means according to the azimuth angle of the head. 13. The means for controlling the generating operation has a detecting means for detecting the tendency of the output of the frequency detecting means, and controls the frequency of the clock according to the output of the detecting means. The reproducing device according to claim 12. 14. The frequency detection means includes a counter that counts the clock for a predetermined period, a register that holds a comparison value, and comparison means that compares the comparison value with the count value of the counter. 13. The reproducing apparatus according to claim 12, wherein the control means changes the comparison value according to the azimuth angle of the head. 15. A phase difference detection for reproducing a signal from a recording medium by a plurality of heads having different azimuth angles and detecting a phase difference between a voltage controlled oscillator and an output clock of the voltage controlled oscillator and an input signal. Means for generating a clock phase-synchronized with the reproduction signal by PLL means comprising means and a loop filter, wherein an oscillation frequency error of the voltage controlled oscillation means is detected and integrated with an output of the loop filter, A reproducing apparatus, characterized in that the integrated output and the output of the loop filter are added and input to the voltage controlled oscillation means, and the detection operation of the oscillation frequency error is changed according to the azimuth angle of the head. 16. The reproducing apparatus according to claim 15, further comprising a microcomputer that performs the operation of detecting the oscillation frequency error, the integrating operation, and the changing operation. 17. A reproducing means for sequentially reproducing a signal by tracing a tape-shaped recording medium with a plurality of heads, a generating means for generating a clock phase-synchronized with the reproduced signal, and a frequency detecting means for detecting a frequency of the clock. Means, a means for controlling the generating operation of the generating means by using the output of the frequency detecting means, and a means for controlling the detecting operation of the frequency detecting means according to the head tracing the tape-shaped recording medium. A playback device including. 18. The frequency detection means includes a counter that counts the clock for a predetermined period, a register that holds a comparison value, and comparison means that compares the comparison value with the count value of the counter. 18. The reproducing apparatus according to claim 17, wherein the control means changes the comparison value according to the azimuth angle of the head. 19. A reproducing means for reproducing a signal from a recording medium by using a plurality of heads, and a plurality of generating means for generating clocks of different frequencies respectively in phase synchronization with the signals reproduced by the plurality of heads. A playback device including. 20. A plurality of phase difference detecting means for detecting a phase difference between a signal reproduced from the plurality of heads and a clock corresponding to the plurality of reproduced signals, and the phase difference detecting means. 20. A plurality of loop filters to which respective outputs of the above are respectively inputted, and a plurality of oscillating means for outputting a signal of a frequency corresponding to the outputs of the plurality of loop filters as the clock respectively. Playback device. 21. A plurality of equalizing means for equalizing signals reproduced from the plurality of heads, respectively, and clocks generated by the plurality of generating means are output from the plurality of equalizing means, respectively. A plurality of conversion means for sampling the reproduction signal and converting it into a digital signal of one sample and a plurality of bits, and a plurality of conversion means for giving characteristics of PR (1,0, -1) to the digital signals converted by the conversion means, respectively. The reproduction apparatus according to claim 19, further comprising a processing unit. 22. Each of the plurality of generating means has a detecting means for detecting a frequency error of the plurality of clocks by a different detecting operation.
9. The reproducing device according to item 9.