JPH0934736A - Operation switching controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute respective operations at high speed while switching the plural mutually different operations when performing access from plural data processors to plural data storage means. SOLUTION: In a majority operating mode, among data resulted from the processing of MPU 11-15, the data according to majority are selected by a data bus majority circuit 54, the selected data ate transferred through bidirectional selectors 41-45 to memory blocks 61-65 as common data and at the time of a parallel operating mode, the data of the MPU 11-15 are respectively independently transferred through the bidirectional selectors 41-45 to the memory blocks 61-65.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation switching controller, and more particularly, to an operation suitable for accessing a plurality of memory blocks by switching a majority operation and a parallel operation of a plurality of computers constituting a data processing device. Regarding the switching controller.

[0002]

2. Description of the Related Art Conventionally, a plurality of MPUs (Micro Processors) have been used.
Unit) having a plurality of MPUs
When accessing a memory, parallel distributed processing that causes each MPU to perform separate processing and majority processing that causes each MPU to perform the same processing are performed. For example,
As shown in FIG. 3, when placed in a system having five MPUs, the MPUs 301 to 305 have local memories 31 respectively.
1 to 315, load different software to each local 311 to 315, and buffers 321 to 325.
Parallel distributed processing is performed to exchange data with the main memory 330 via the. When executing a majority decision process, the software of the same process is loaded in each local memory 311 to 315, and each MPU 301 to 305 is loaded.
The method of exchanging the processing result of (3) between MPUs and taking the majority logic by software is adopted.

In executing the majority decision process, FIG.
As shown in FIG. 5, the five MPUs 401 to 405 are connected to the main memory 420 via the majority decision circuit 410, and the designated data of the data of each MPU 401 to 405 is selected by the majority decision circuit 410, and the selected data is used as a basis. A method of accessing the main memory 420 is adopted.

As a technique related to this type of technique, there is, for example, JP-A-60-247739.

[0005]

However, among the prior arts, the one in which the majority decision process is performed by software requires a long time to perform the majority decision calculation process, and it is difficult to perform the majority decision process at high speed. Further, in the case where the majority voting circuit 410 is used as the hardware when executing the majority voting process, the majority voting operation and the parallel operation cannot be switched and executed.

Therefore, an object of the present invention is to provide an operation switching controller capable of switching a plurality of different operations and executing each operation at high speed when a plurality of data processing devices access a plurality of data storage means. Especially.

[0007]

According to a first aspect of the present invention, (a) Data selection for fetching data from a plurality of data processing devices and selecting and outputting data according to a designated logic from the plurality of data. Means, (b) a plurality of first data transfer means for respectively transferring the data selected by the data selection means to the plurality of storage means in the first operation mode, and (c) each data processing device and each in the second operation mode. A plurality of second data transfer means for forming a plurality of data transmission systems connecting to the storage means and executing data transfer between each data processing device and each storage means for each data transmission system;
(D) The operation switching controller is provided with a plurality of access means for accessing the data in the designated storage area of each data storage means according to each operation mode.

That is, in the first aspect of the invention, in the first operation mode, the data according to the designated logic among the data from the respective data processing devices is selected as the common data,
The selected data is transferred to each storage means, and in the second operation mode, the data transfer between each data processing device and each storage means is independently performed for each data transmission system.

According to the second aspect of the invention, (a) data selecting means for respectively receiving data from a plurality of data processing devices and selecting and outputting data according to the majority decision among the plurality of data; and (b) a majority decision operation. A plurality of first data transfer means for respectively transferring the data selected by the data selection means to the plurality of storage means in the mode, and (c) a plurality of data transmission systems connecting the respective data processing devices and the respective storage means in the parallel operation mode. A plurality of second data transfer means for forming data transfer between each data processing device and each storage means for each data transmission system, and (d) designation of each data storage means according to each operation mode. The operation switching controller is provided with a plurality of access means for accessing data in the storage area.

That is, according to the second aspect of the invention, in the majority operation mode, the data according to the designated logic among the data from the respective data processing devices is selected as the common data, and the selected data is transferred to the respective storage means. In the parallel operation mode, however, the data transfer between each data processing device and each storage means is performed independently for each data transmission system.

According to the third aspect of the invention, (a) data selecting means for respectively receiving data from a plurality of data processing devices and selecting and outputting data according to a designated logic among the plurality of data, and (b) A plurality of first data transfer means for respectively transferring the data selected by the data selection means to the plurality of storage means in the first operation mode; and (c) a designated data storage means of the plurality of data storage means in the first operation mode. Each data processing device by forming a plurality of data transmission systems connecting the data processing device and each storage device in the second operation mode, and buffer means for taking in the data from the data processing device and transferring the data to each data processing device. And a plurality of second data transfer means for executing data transfer between the data storage means and each data storage means, and (e) each data transfer means according to each operation mode. Switching operation and a plurality of access means for accessing the data storage area of the designated storage means is provided in the controller.

That is, in the third aspect of the invention, in the first operation mode, among the data from the respective data processing devices, the data according to the designated logic is selected as the common data,
The selected data is transferred to each storage unit, the data from the designated storage unit is transferred to each data processing unit via the buffer unit, and the data is transferred between each data processing unit and each storage unit in the second operation mode. Is performed independently for each data transmission system.

In the invention according to claim 4, (a) data selecting means for respectively receiving data from a plurality of data processing devices and selecting and outputting data according to a majority decision among the plurality of data, and (b) a majority decision operation. A plurality of first data transfer means for respectively transferring the data selected by the data selection means to the plurality of storage means in the mode, and the data from the designated storage means of the plurality of data storage means in the majority operation mode (C) A buffer means for transferring data to each data processing device, and (c) a plurality of data transmission systems connecting each data processing device and each storage device in the parallel operation mode are formed to store data between each data processing device and each storage device. A plurality of second data transfer means for executing transfer for each data transmission system, and (d) designation of each data storage means according to each operation mode. Switching operation and a plurality of access means for accessing the data of 憶 area is provided to the controller.

That is, in the invention described in claim 4, in the majority operation mode, the data according to the designated logic among the data from each data processing device is selected as common data, and the selected data is transferred to each storage means. Then, the data from the designated storage means is transferred to each data processing device via the buffer means, and in the parallel operation mode, the data transfer between each data processing device and each storage means is performed independently for each data transmission system. The feature is that it is executed.

In the invention according to claim 5, a plurality of first
The data transfer means and the plurality of second data transfer means are characterized in that each first data transfer means and each second data transfer means are integrated.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to Examples.

FIG. 1 is an overall configuration diagram of a computer system using a controller according to an embodiment of the present invention, and FIG. 2 is a block configuration diagram showing specific contents of the controller shown in FIG.

In FIG. 1 and FIG. 2, the computer system comprises a plurality of, for example, five MPUs as data processing devices.
11 to 15, memory blocks 61 to 6 as storage means
5 and the controller 10, the controller 10 includes the MPUs 11 to 15 and the memory blocks 61 to 61.
It is arranged between 65 and. The controller 10 is M
A data transmission system that connects the PUs 11 to 15 and the memory blocks 61 to 65 is configured, and also data transfer means and access means are configured.

The controller 10 includes five decoders 21.
˜25, five selectors 31 to 35, five bidirectional selectors 41 to 45, an address / control signal majority circuit 51,
Decoder 52, Bach 53, Data bus majority circuit 54
It is provided with.

The address / control signal majority circuit 51 has M
Address / control signals 101 to 105 from the PUs 11 to 15
Is taken in, the majority operation is performed on these signals, and the address / control signal 130 according to the majority decision is output to the decoder 52. The decoder 52
The buffer enable control signal is output to the buffer 53 according to the control signal 130, and the bidirectional selector control signal 141 is output.
To 145 are output to the bidirectional selectors 41 to 45, and the address signal 150 is output to the selectors 31 to 35. The buffer 53 serves as a buffer unit for each M.
When the PUs 11 to 15 read data from the memory blocks 61 to 65, the data of the designated memory block is fetched via the bidirectional selectors 41 to 45, and this data is used as the data bus signals 111 to 115 for each MPU 11 to 115.
It is designed to be transferred to 115.

The data bus majority decision circuit 54 is configured as a data selection means, takes in the data bus signals 111 to 115 from the MPUs 11 to 15, performs a majority decision operation of these signals, and makes a data bus signal 12 according to the majority decision.
0 is transferred to each of the bidirectional selectors 41 to 45.

The decoders 21 to 25 take in the address / control signals 101 to 105 from the MPUs 11 to 15, output the control signals 161 to 165 to the bidirectional selectors 41 to 45, and output the address signals 171 to 175 to the selectors 31 to 35.
It is designed to output to. Each of the selectors 31 to 35 takes in a majority / parallel operation mode setting signal (hereinafter referred to as an operation mode signal) 180, selects the address signal 150 in the majority operation mode (first operation mode), and selects the parallel operation mode ( In the second operation mode), the address signals 171 to 175 are selected, and the selected address signals 181 to 185 are sent to the memory blocks 61 to 6 respectively.
5, and the data stored in the designated storage area of each of the memory blocks 61 to 65 is accessed. That is, the address / control signal majority circuit 51, the decoder 52, the decoders 21 to 25, and the selectors 31 to 35.
Are to constitute access means.

The bidirectional selectors 41 to 45 fetch the operation mode setting signal 180, select the bidirectional selector control signals 141 to 145 and the data bus signal 120 in the majority operation mode, and change the data bus signal 120 to the data bus signal 191. To 195, the data bus signals 191 to 195 are fetched from the memory blocks 61 to 65, and these signals are transferred to the buffer 53 as the data bus signal 121. Further, in the parallel operation mode, the bidirectional selectors 41 to 45 take in the control signals 161 to 165 and the data bus signals 111 to 115, and set the data selected by these signals as the data bus signals 191 to 195 in the memory blocks 61 to 65. It is designed to be transferred to. That is, the bidirectional selectors 41 to 45 constitute first data transfer means and second data transfer means, respectively.

Next, the operation of the embodiment of the present invention will be described.

First, when the operation mode setting signal 180 instructs the processing in the majority operation mode, the selector 3
The address signal 150 is selected by 1 to 35. Then, when the data bus signals 111 to 115 related to the data calculated by the MPUs 11 to 15 are output, the majority calculation of these signals is performed in the data bus majority circuit 54, and the data bus signal 120 according to the majority decision is output to each MPU.
Data bus signals common to 11 to 15 are transferred to the memory blocks 61 to 65 via the bidirectional selectors 41 to 45. At this time, the selectors 31 to 35 output the address signals 181 to 185 according to the same address signal 150, so that the memory blocks 61 to 65 can be treated as a large integrated memory.

On the other hand, when the data is read from the memory blocks 61 to 65, the data bus signal 121 selected by the bidirectional selectors 41 to 45 is passed through the buffer 53 as the data bus signals 111 to 115 and the MPUs 11 to 15 are generated.
Transferred to

Next, when the operation mode setting signal 180 instructs processing in the parallel operation mode, the select 31
Address signals 171 to 175 are selected by
Control signals 161 to 16 by the bidirectional selectors 41 to 45
5 and the data bus signals 111 to 115 are selected, and the bidirectional selectors 41 to 45 form a data transmission system that independently connects the MPUs 11 to 15 and the memory blocks 61 to 65. That is, the MPUs 11 to 15 and the memory blocks 61 to 65 perform parallel operations in a one-to-one correspondence.

According to this embodiment, the operation mode setting signal 1
Based on 80, the majority operation and the parallel operation can be switched and the majority operation can be executed at high speed, which can contribute to speeding up of data processing.

As described above, according to the invention described in claim 1, in the first operation mode, the data according to the designated logic among the data from the respective data processing devices is selected as the common data. Since the selected data is transferred to each storage means and the data transfer between each data processing device and each storage means is executed independently for each data transmission system in the second operation mode, the operation mode setting signal The first operation and the second operation can be switched based on the above, and the first operation can be executed at high speed, which can contribute to speeding up of data processing.

According to the second aspect of the invention, in the majority operation mode, the data according to the designated logic among the data from each data processing device is selected as the common data, and the selected data is stored in each storage means. In the parallel operation mode, the data transfer between each data processing device and each storage means is independently executed for each data transmission system. Therefore, the majority operation and the parallel operation are performed based on the operation mode setting signal. It is possible to perform switching, and it is possible to execute a majority operation at high speed, which can contribute to speeding up of data processing.

Further, according to the invention described in claim 3, in the first operation mode, the data according to the designated logic among the data from the respective data processing devices is selected as the common data,
The selected data is transferred to each storage unit, the data from the designated storage unit is transferred to each data processing unit via the buffer unit, and the data is transferred between each data processing unit and each storage unit in the second operation mode. Is performed independently for each data transmission system, the first operation and the second operation can be switched based on the operation mode setting signal, and the first operation can be executed at high speed. It can contribute to speeding up.

According to the invention described in claim 4, that is, in the invention described in claim 4, in the majority operation mode,
Of the data from each data processing device, the data according to the designated logic is selected as common data, the selected data is transferred to each storage means, and the data from the designated storage means is transferred to each data via the buffer means. In the parallel operation mode, the data transfer between each data processing device and each storage means is performed independently for each data transmission system, so that the majority operation is performed in parallel with the majority operation based on the operation mode setting signal. The operation can be switched and the majority operation can be executed at high speed, which can contribute to speeding up of data processing.

Further, according to the invention of claim 5, a plurality of first data transfer means and a plurality of second data transfer means are constituted by integrating each first data transfer means and each second data transfer means. Therefore, it is possible to contribute to simplification of the configuration.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a computer system that employs an operation switching controller according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram for explaining specific contents of the controller shown in FIG.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a block diagram of another conventional example.

[Explanation of symbols]

 10 controller 11-15 MPU 21-25 decoder 31-35 selector 41-45 bidirectional selector 51 address / control signal majority circuit 52 decoder 53 buffer 54 data bus majority circuit 61-65 memory block

Claims (5)

[Claims] 1. A data selection means for respectively fetching data from a plurality of data processing devices and selecting and outputting data according to a designated logic among the plurality of data, and a data selection means in the first operation mode. A plurality of first data transfer means for respectively transferring data to a plurality of storage means, and a plurality of data transmission systems for connecting the respective data processing apparatuses and the respective storage means in the second operation mode are formed, and the respective data processing apparatuses are formed. And a plurality of second data transfer means for executing data transfer between each of the storage means for each data transmission system, and accessing data in a designated storage area of each of the data storage means according to the operation mode. And a plurality of access means for performing the operation switching controller. 2. A plurality of data selecting means for respectively receiving data from a plurality of data processing devices and selecting and outputting data according to a majority decision among the plurality of data, and a plurality of data selected by the data selecting means in a majority operation mode. A plurality of first transfers to respective storage means
A data transfer means and a plurality of data transmission systems connecting the respective data processing devices and the respective storage means in the parallel operation mode are formed to transfer data between the respective data processing devices and the respective storage means. Operation comprising a plurality of second data transfer means to be executed for each system, and a plurality of access means for accessing data in a designated storage area of each of the data storage means in accordance with each of the operation modes Switching controller. 3. Data selection means for respectively receiving data from a plurality of data processing devices and selecting and outputting data according to a designated logic among the plurality of data, and selection by the data selection means in the first operation mode. A plurality of first data transfer means for respectively transferring data to a plurality of storage means, and data from a designated data storage means of the plurality of data storage means in the first operation mode is taken in and this data is processed by each of the data processing devices. And a buffer means for transferring the data to the storage means, and a plurality of data transmission systems for connecting the data processing devices and the storage means in the second operation mode to transfer data between the data processing devices and the storage means. A plurality of second data transfer means to be executed for each data transmission system, and designation of each data storage means according to each operation mode. Operation switch controller characterized by comprising a plurality of access means for accessing the data area. 4. Data selecting means for respectively receiving data from a plurality of data processing devices and selecting and outputting data according to a majority decision among the plurality of data, and a plurality of data selected by the data selecting means in a majority operation mode. A plurality of first transfers to respective storage means
Data transfer means, buffer means for taking in data from a designated data storage means of the plurality of data storage means in the majority operation mode, and transferring this data to each data processing device, and each data processing in the parallel operation mode A plurality of second data transfer means for forming a plurality of data transmission systems connecting the device and the respective storage means, and for executing data transfer between the respective data processing devices and the respective storage means for each data transmission system; An operation switching controller comprising: a plurality of access means for accessing data in a designated storage area of each data storage means according to each operation mode. 5. The plurality of first data transfer units and the plurality of second data transfer units are configured by integrating the first data transfer units and the second data transfer units. The operation switching controller according to claim 1, claim 2, claim 3, or claim 4.