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JPH0933940A - Mount structure for semiconductor chip for driving display panel - Google Patents

Mount structure for semiconductor chip for driving display panel

Info

Publication number
JPH0933940A
JPH0933940A JP7178418A JP17841895A JPH0933940A JP H0933940 A JPH0933940 A JP H0933940A JP 7178418 A JP7178418 A JP 7178418A JP 17841895 A JP17841895 A JP 17841895A JP H0933940 A JPH0933940 A JP H0933940A
Authority
JP
Japan
Prior art keywords
display panel
electrode
semiconductor chip
input
fpc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7178418A
Other languages
Japanese (ja)
Inventor
Yasushi Kaneko
金子  靖
Takayuki Nagashima
孝行 長嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP7178418A priority Critical patent/JPH0933940A/en
Publication of JPH0933940A publication Critical patent/JPH0933940A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Liquid Crystal (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve connection reliability by reducing a cross phenomenon by the reduction of input resistance and preventing a connection part from being broken by the reinforcement of an auxiliary substrate. SOLUTION: The mount structure consists of an FPC 5 which has metal, wiring, a display panel substrate 1 which has a display driving connection electrode, a semiconductor chip 7 which has an input projection electrode 8 and an output projection electrode 9 adhered to the metal wiring 6 and display driving connection wiring with conductive adhesives 10 over both the FPC 5 and display panel substrate 1, and an auxiliary substrate 3 which is backed over both the FPC 5 and display panel substrate 1 and reinforces the abutting parts of both. Then the auxiliary substrate 3 has an upper-stage part and a lower-stage part which are different in height because of a step; and the metal wiring 6 is adhered and fixed to the upper-stage part and the display driving connection electrode 2 is adhered and fixed to the lower stage part so that the both are almost in level with each other.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、液晶表示、エレクトロ
ルミネセンス(EL)表示、発光ダイオード(LED)
表示などの表示パネル基板と半導体チップとの接続構造
に関し、特にフレキシブル印刷基板(以下、FPCと記
載)を用い、表示パネル基板に半導体チップを直接接続
するCOG法(Chip On Glass)による半
導体チップの実装構造に関する。
The present invention relates to a liquid crystal display, an electroluminescence (EL) display, a light emitting diode (LED).
Regarding a connection structure between a display panel substrate such as a display and a semiconductor chip, in particular, a flexible printed substrate (hereinafter referred to as FPC) is used, and the semiconductor chip is directly connected to the display panel substrate by a COG method (Chip On Glass). Regarding mounting structure.

【0002】[0002]

【従来の技術】表示パネルへの半導体チップを実装する
従来例としては、TAB法(TapeAutomate
d Bonding)によってパッケージ化されたTC
P(Tape Carrier Package)を表
示パネル基板に実装する方法がある。また、COG法
(Chip On Glass)により半導体チップを
直接表示パネル基板に接続し、電源および入力信号に関
わる表示パネル基板上の配線にFPCを実装する構造が
ある。
2. Description of the Related Art As a conventional example for mounting a semiconductor chip on a display panel, a TAB method (Tape Automate) is used.
TC packaged by d Bonding)
There is a method of mounting P (Tape Carrier Package) on a display panel substrate. Further, there is a structure in which a semiconductor chip is directly connected to a display panel substrate by a COG method (Chip On Glass), and an FPC is mounted on wirings on the display panel substrate related to a power supply and an input signal.

【0003】しかし、FPCと表示パネル基板との間の
接続において、100μm以下の接続ピッチが必要な場
合は、半導体チップ全面実装が可能なCOG法が用いら
れる。 以下、図6を用いて従来のCOG法について説
明する。図6は、表示パネル基板1上に半導体チップ7
とFPC5とを、COG法を用いて接続した状態の断面
形状を示す模式拡大図である。
However, when a connection pitch of 100 μm or less is required for the connection between the FPC and the display panel substrate, the COG method is used, which allows the semiconductor chip to be entirely mounted. The conventional COG method will be described below with reference to FIG. FIG. 6 shows a semiconductor chip 7 on the display panel substrate 1.
FIG. 3 is a schematic enlarged view showing a cross-sectional shape of a state in which the FPC5 and the FPC5 are connected using the COG method.

【0004】半導体チップ7に入力突起電極8と出力突
起電極9をメッキ法や真空蒸着法で銅や金の金属を用い
て形成する。つぎに前記入力突起電極8と出力突起電極
9の先端部にエポキシ系の接着剤に導電粒を混入した導
電性接着剤10を印刷法やディップ法で塗布する。その
後双眼顕微鏡を用いて半導体チップ7と表示パネル基板
1との位置を合わせ、ガラスからなる表示パネル基板1
に配置した表示駆動接続電極2および入力接続電極21
にそれぞれ出力突起電極9および入力突起電極8を接続
する。前記表示駆動接続電極2および入力接続電極21
は、酸化インジュウムスズ(以下、ITOと記載)など
の透明導電膜で構成されている。
An input protruding electrode 8 and an output protruding electrode 9 are formed on a semiconductor chip 7 by using a metal such as copper or gold by a plating method or a vacuum evaporation method. Next, a conductive adhesive 10 in which conductive particles are mixed in an epoxy adhesive is applied to the tips of the input protruding electrode 8 and the output protruding electrode 9 by a printing method or a dipping method. After that, the semiconductor chip 7 and the display panel substrate 1 are aligned with each other by using a binocular microscope, and the display panel substrate 1 made of glass is aligned.
Display drive connection electrode 2 and input connection electrode 21 arranged in
The output projecting electrode 9 and the input projecting electrode 8 are connected to. The display drive connection electrode 2 and the input connection electrode 21
Is composed of a transparent conductive film such as indium tin oxide (hereinafter referred to as ITO).

【0005】さらに熱処理を行い導電性接着剤10を硬
化させる。これにより出力突起電極9と表示駆動接続電
極2および入力突起電極8と入力接続電極21は良好な
電気的接続が得られる。その後半導体チップ7と表示パ
ネル基板1の隙間にエポキシ系などの有機系材料からな
る絶縁樹脂11を流し込み、熱処理を行い絶縁樹脂11
を硬化させる。次にFPC5の金属配線6と表示パネル
基板1の入力接続電極21とを位置合わせして、熱硬化
性樹脂シートに導電粒を混入した異方導電性シートを用
いて、入力接続電極21の外周部に当たるFPC接続部
と金属配線6を接続する。
Further, heat treatment is performed to cure the conductive adhesive 10. As a result, good electrical connection can be obtained between the output projecting electrode 9 and the display drive connecting electrode 2, and between the input projecting electrode 8 and the input connecting electrode 21. After that, an insulating resin 11 made of an organic material such as an epoxy resin is poured into a gap between the semiconductor chip 7 and the display panel substrate 1 and heat treatment is performed.
Cure. Next, the metal wiring 6 of the FPC 5 and the input connection electrode 21 of the display panel substrate 1 are aligned with each other, and an anisotropic conductive sheet in which conductive particles are mixed in a thermosetting resin sheet is used to form the outer periphery of the input connection electrode 21. The metal wiring 6 is connected to the FPC connection part corresponding to the part.

【0006】以上の方法で実装されたFPC5の金属配
線6の抵抗値は1オーム以下と小さいが、入力接続電極
21は抵抗の高いITOで形成されているので、入力抵
抗が数十オーム以上になってしまう。従って半導体チッ
プ7へ入力する電源電圧が安定せず、表示画像により電
源電圧が変動し、表示パターン以外の表示が影響を受け
るクロストーク現象が発生し易くなる。
The resistance value of the metal wiring 6 of the FPC 5 mounted by the above method is as small as 1 ohm or less, but since the input connection electrode 21 is made of ITO having high resistance, the input resistance is tens of ohms or more. turn into. Therefore, the power supply voltage input to the semiconductor chip 7 is not stable, the power supply voltage fluctuates depending on the displayed image, and the crosstalk phenomenon that affects the display other than the display pattern is likely to occur.

【0007】そこでこの問題を解決するために半導体装
置7の入力突起電極8とFPC5の金属配線6を導電性
接着剤10を用いて直接接着する方法が考えられる。以
下図7を用いてその例について説明する。ガラスからな
る表示パネル基板1上の表示駆動接続電極2とFPC5
上の金属配線6を双眼顕微鏡を用いて位置合わせを行
い、表示パネル基板1とFPC5とを接着剤4を介して
接着する。接着剤4は熱硬化性のエポキシ系接着剤など
で液状、フィルム状のどちらでも良い。この時表示パネ
ル基板1上の表示駆動接続配線2の面とFPC5上の金
属配線6の面に段差が形成される。
In order to solve this problem, a method of directly bonding the input protruding electrode 8 of the semiconductor device 7 and the metal wiring 6 of the FPC 5 with the conductive adhesive 10 can be considered. An example thereof will be described below with reference to FIG. 7. Display drive connection electrode 2 and FPC 5 on display panel substrate 1 made of glass
The upper metal wiring 6 is aligned using a binocular microscope, and the display panel substrate 1 and the FPC 5 are bonded to each other via the adhesive 4. The adhesive 4 is a thermosetting epoxy adhesive or the like, and may be liquid or film-like. At this time, a step is formed between the surface of the display drive connection wiring 2 on the display panel substrate 1 and the surface of the metal wiring 6 on the FPC 5.

【0008】次に半導体チップ7上に入力突起電極8と
出力突起電極19をメッキ法などで銅や金の金属を用い
て形成する。この時入力突起電極8と出力突起電極19
とに段差ができるように出力突起電極19の高さを入力
突起電極8の高さより大きくする。この段差の値は金属
配線6を有するFPC5の厚さと前記接着剤の厚さを加
えたものと同一になるように形成する。次に入力突起電
極8と出力突起電極19の先端部にエポキシ系の接着剤
に導電粒を混入した導電性接着剤10を印刷法やディッ
プ法で塗布する。その後双眼顕微鏡を用いて半導体チッ
プ7と表示パネル基板1に配置した表示駆動接続電極2
とFPC上の金属配線6との位置を合わせを行い、表示
駆動接続電極2および金属配線6にそれぞれ出力突起電
極19および入力突起電極8を接続する。さらに熱処理
を行い導電性接着剤10を硬化させる。これにより出力
突起電極19と表示駆動接続電極2および入力突起電極
8と金属配線6は良好な電気的接続が得られる。
Next, the input projecting electrodes 8 and the output projecting electrodes 19 are formed on the semiconductor chip 7 by plating or the like using a metal such as copper or gold. At this time, the input protruding electrode 8 and the output protruding electrode 19
The height of the output projecting electrode 19 is made larger than the height of the input projecting electrode 8 so that there is a step. The step difference is formed so as to have the same value as the thickness of the FPC 5 having the metal wiring 6 and the thickness of the adhesive. Next, a conductive adhesive 10 in which conductive particles are mixed with an epoxy adhesive is applied to the tip ends of the input protruding electrode 8 and the output protruding electrode 19 by a printing method or a dipping method. After that, the display drive connection electrodes 2 arranged on the semiconductor chip 7 and the display panel substrate 1 using a binocular microscope.
Are aligned with the metal wiring 6 on the FPC, and the output projecting electrode 19 and the input projecting electrode 8 are connected to the display drive connection electrode 2 and the metal wiring 6, respectively. Further, heat treatment is performed to cure the conductive adhesive 10. As a result, good electrical connection can be obtained between the output protruding electrode 19, the display drive connecting electrode 2, the input protruding electrode 8 and the metal wiring 6.

【0009】以上の方法によれば入力抵抗は数オーム以
下に低減される。従って半導体チップ7へ入力する電源
電圧が安定し、表示パネルのクロストーク現象が改善さ
れることになる。しかしながら半導体チップ7の入力突
起電極8の高さが5〜20μmにたいして出力突起電極
19の高さが110〜130μmと非常に高くなってし
まう。この出力突起電極19の加工は可能であるが、電
極としての安定性、導電性接着剤の塗布方法および量産
性を考慮すると好ましくない。
According to the above method, the input resistance is reduced to several ohms or less. Therefore, the power supply voltage input to the semiconductor chip 7 is stabilized, and the crosstalk phenomenon of the display panel is improved. However, the height of the input protruding electrode 8 of the semiconductor chip 7 is 5 to 20 μm, and the height of the output protruding electrode 19 is 110 to 130 μm, which is extremely high. The output protruding electrode 19 can be processed, but it is not preferable in consideration of the stability as an electrode, the method of applying the conductive adhesive, and the mass productivity.

【0010】そこで出力突起電極の高さと入力突起電極
の高さをと同一として、かつ入力突起電極8と金属配線
6を直接接着する方法が考えられる。以下図8を用いて
その例について説明する。半導体チップ7に入力突起電
極18と出力突起電極9をメッキ法や真空蒸着法で銅や
金の金属を用いて形成する。つぎに前記出力突起電極9
の先端部にエポキシ系の接着剤に導電粒を混入した導電
性接着剤10を印刷法やディップ法で塗布する。その
後、双眼顕微鏡を用いて表示パネル基板1の表示駆動接
続電極2と、半導体チップ7に設けた出力突起電極9と
を、入力突起電極18が表示パネル基板1の外部に出る
ようにして双眼顕微鏡を用いて位置合わせを行う。つづ
いて半導体チップ7を加圧して、表示パネル基板1に仮
接続した状態で導電性接着剤10を加熱し硬化させる。
Therefore, a method in which the height of the output protruding electrode and the height of the input protruding electrode are made the same and the input protruding electrode 8 and the metal wiring 6 are directly bonded can be considered. An example thereof will be described below with reference to FIG. The input projecting electrodes 18 and the output projecting electrodes 9 are formed on the semiconductor chip 7 by using a metal such as copper or gold by a plating method or a vacuum deposition method. Next, the output projection electrode 9
A conductive adhesive 10 in which conductive particles are mixed with an epoxy-based adhesive is applied to the tip of the sheet by a printing method or a dipping method. After that, the display drive connection electrodes 2 of the display panel substrate 1 and the output projecting electrodes 9 provided on the semiconductor chip 7 are arranged so that the input projecting electrodes 18 are exposed to the outside of the display panel substrate 1 by using a binocular microscope. Align using. Subsequently, the semiconductor chip 7 is pressed to heat and cure the conductive adhesive 10 while it is temporarily connected to the display panel substrate 1.

【0011】次に半導体チップ7の出力突起電極9の周
辺領域にエポキシ系や、ゴム系などの有機材料からなる
絶縁樹脂11を注入したのち加熱し硬化させる。この工
程では、入力突起電極18の周辺に絶縁樹脂11がまわ
り込まないように注意する。次にFPC5に異方導伝性
シート12を仮接着する。また半導体チップ7は下向き
の状態でFPC5の金属配線6と半導体チップ7の入力
突起電極18との位置合わせを行う。つづいてFPC5
側から異方導伝性シート12を熱圧着してFPC5と半
導体チップ7を接着する。これによって金属配線6と入
力突起電極18が接続される。最後に図示はしていない
がエポキシ系や、ゴム系樹脂をFPC5と半導体チップ
7の周辺に形成し各接続部を保護する。以上の方法によ
れば出力突起電極9の高さは5〜20μmにすることが
できる。しかしながらこの実装構造も製造工程中あるい
は完成後に外力が加わった場合接続部が破損する危惧が
あり、量産性の面で好ましくない。
Next, an insulating resin 11 made of an organic material such as epoxy or rubber is injected into the peripheral area of the output bump electrode 9 of the semiconductor chip 7 and then heated and cured. In this step, care should be taken so that the insulating resin 11 does not go around the input protruding electrode 18. Next, the anisotropically conductive sheet 12 is temporarily adhered to the FPC 5. Further, the semiconductor chip 7 is aligned downward with the metal wiring 6 of the FPC 5 and the input protruding electrode 18 of the semiconductor chip 7. Continued FPC5
The anisotropically conductive sheet 12 is thermocompression bonded from the side to bond the FPC 5 and the semiconductor chip 7 together. As a result, the metal wiring 6 and the input protruding electrode 18 are connected. Finally, although not shown, an epoxy resin or a rubber resin is formed around the FPC 5 and the semiconductor chip 7 to protect each connection portion. According to the above method, the height of the output protruding electrode 9 can be set to 5 to 20 μm. However, this mounting structure is also unfavorable in terms of mass productivity because there is a risk that the connecting portion will be damaged if an external force is applied during or after the manufacturing process.

【0012】[0012]

【発明が解決しようとする課題】そこで本発明の課題
は、表示パネルへ半導体チップをCOG法によって実装
する場合において、FPCの金属配線と半導体チップの
入力突起電極とを直接接続し、かつ表示パネルに外力が
加わった場合でも破損しないよう接続部を補強すること
により高い接続信頼性を備え、量産性に優れた半導体チ
ップの実装構造を提供することにある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to directly connect the metal wiring of the FPC and the input projecting electrode of the semiconductor chip to the display panel when the semiconductor chip is mounted on the display panel by the COG method. It is to provide a mounting structure of a semiconductor chip that has high connection reliability by reinforcing the connection portion so as not to be damaged even when an external force is applied to it, and is excellent in mass productivity.

【0013】[0013]

【課題を解決するための手段】上記の課題を解決するた
めに本発明の表示パネル駆動用半導体チップの実装構造
は、金属配線を有するフレキシブル印刷基板と、表示パ
ネルの一部を構成し周辺部に表示駆動接続電極を有する
表示パネル基板と、前記フレキシブル印刷基板および前
記表示パネル基板の両者にまたがり前記金属配線および
前記表示駆動接続配線にそれぞれ導電性接着剤により接
着されている入力突起電極および出力突起電極を有する
半導体チップと、前記フレキシブル印刷基板および前記
表示パネル基板の両者にまたがって裏打ちされ両者の当
接部を補強する補助基板とからなる実装構造であって、
前記補助基板は段差により高さの異なる上段部および下
段部を有し、前記金属配線および前記表示駆動接続電極
が、ほぼ同一平面上に並ぶように前者を上段部に後者を
下段部にそれぞれ接着固定していることを特徴とする。
In order to solve the above-mentioned problems, a mounting structure of a semiconductor chip for driving a display panel of the present invention has a flexible printed board having metal wiring and a peripheral portion which constitutes a part of the display panel. A display panel substrate having a display drive connection electrode, and an input projecting electrode and an output which are spread over both the flexible printed circuit board and the display panel substrate and are bonded to the metal wiring and the display drive connection wiring by a conductive adhesive respectively. A mounting structure comprising a semiconductor chip having a protruding electrode, and an auxiliary substrate which is lined across both the flexible printed substrate and the display panel substrate and reinforces the contact portion between the two,
The auxiliary substrate has an upper portion and a lower portion having different heights due to steps, and the former is bonded to the upper portion and the latter is bonded to the lower portion so that the metal wiring and the display drive connection electrode are arranged on substantially the same plane. It is characterized by being fixed.

【0014】[0014]

【作用】上段部と下段部からなる段差を有する補助基板
の下段部に表示駆動接続電極を有する表示パネル基板を
接着し、次に上段部に金属配線を有するFPCを接着す
る。この時、表示駆動接続電極と金属配線がほぼ同一平
面上に並ぶように補助基板の段差を表示パネル基板の厚
さとFPCの厚さとの差と同じ値に設定する。次にFP
Cおよび表示パネル基板の両者にまたがり金属配線およ
び表示駆動接続配線にそれぞれ半導体チップ上の入力突
起電極および出力突起電極を導電性接着剤により接続す
る。この結果、金属配線と入力突起電極は導電性接着剤
を介して直接接続され半導体チップへの入力接続抵抗を
小さくし、入力する電源電圧を安定化することでクロス
トーク現象を抑えることができる。さらに補助基板がF
PCおよび表示パネル基板の両者にまたがって裏打ち
し、金属配線と入力突起電極および表示駆動接続配線と
出力突起電極のそれぞれの接続部を補強する実装構造と
なっている。この結果、半導体チップの実装工程中また
は完成後に誤って加わる外力に対しても接続部の破損を
防止することができ接続信頼性を向上させることが可能
となる。
The display panel substrate having the display drive connection electrodes is adhered to the lower portion of the auxiliary substrate having the step formed by the upper portion and the lower portion, and then the FPC having the metal wiring is adhered to the upper portion. At this time, the step difference of the auxiliary substrate is set to the same value as the difference between the thickness of the display panel substrate and the thickness of the FPC so that the display drive connection electrode and the metal wiring are arranged on substantially the same plane. Next FP
The input projecting electrode and the output projecting electrode on the semiconductor chip are respectively connected to the metal wiring and the display drive connecting wiring across both C and the display panel substrate by a conductive adhesive. As a result, the metal wiring and the input projecting electrode are directly connected through the conductive adhesive to reduce the input connection resistance to the semiconductor chip and stabilize the input power supply voltage, thereby suppressing the crosstalk phenomenon. Furthermore, the auxiliary board is F
The mounting structure is such that it is lined across both the PC and the display panel substrate to reinforce the respective connection portions of the metal wiring, the input protruding electrode, the display drive connection wiring, and the output protruding electrode. As a result, it is possible to prevent damage to the connection portion even when an external force is erroneously applied during or after the semiconductor chip mounting process, and it is possible to improve connection reliability.

【0015】[0015]

【実施例】本発明の実施例を図面に基づいて説明する。
図1は本発明の実施例の半導体チップの実装構造の断面
形状を示す模式拡大図である。図2は、本発明の実施例
における補助基板の断面形状を示す模式拡大図である。
図3および図4は、本発明の実施例の半導体チップの実
装方法の中間工程の断面形状を示す模式拡大図である。
図5は本発明の実施例の半導体チップの実装構造の平面
形状を示す模式拡大図である。
An embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic enlarged view showing a cross-sectional shape of a semiconductor chip mounting structure according to an embodiment of the present invention. FIG. 2 is a schematic enlarged view showing the cross-sectional shape of the auxiliary substrate in the embodiment of the present invention.
3 and 4 are schematic enlarged views showing the cross-sectional shape of the intermediate step of the method of mounting a semiconductor chip according to the embodiment of the present invention.
FIG. 5 is a schematic enlarged view showing the planar shape of the semiconductor chip mounting structure of the embodiment of the present invention.

【0016】以下本発明の実施例について液晶表示装置
における半導体チップの実装構造を例として説明する。
図2に示す補助基板3は、熱硬化性のエポキシ樹脂から
なり、金型を用いて成形加工したものであり、上段部3
1および下段部32を有する。次に図3に示すようにガ
ラスからなり、周辺部に表示駆動接続電極2を配置した
表示パネル基板1を補助基板3の下段部32に、接着剤
4を介してヒートツールで加圧しながら80〜120℃
に加熱し接着剤4を硬化させ接着した。上記表示駆動接
続電極2は、ITOなどの透明導電膜で構成されてい
る。
Embodiments of the present invention will be described below by taking a semiconductor chip mounting structure in a liquid crystal display device as an example.
The auxiliary substrate 3 shown in FIG. 2 is made of a thermosetting epoxy resin and is formed by using a mold, and the upper stage portion 3
1 and the lower stage portion 32. Next, as shown in FIG. 3, the display panel substrate 1 made of glass and having the display drive connection electrodes 2 arranged on the periphery thereof is pressed onto the lower step portion 32 of the auxiliary substrate 3 with a heat tool through the adhesive agent 80. ~ 120 ° C
Then, the adhesive 4 was heated and cured to bond. The display drive connection electrode 2 is composed of a transparent conductive film such as ITO.

【0017】次に図5に示すように補助基板3の下段部
32に接着した表示パネル基板1ととFPC5とにそれ
ぞれ設けた位置合わせマーク15を用いて位置合わせを
行う。つづいて図4に示すように補助基板3の上段部3
1にFPC5を接着剤4を介してヒートツールで加圧し
ながら80〜120℃に加熱し接着剤4を硬化させ接着
する。この状態で表示駆動接続電極2と金属配線6とが
ほぼ同一平面上に並ぶように補助基板3の上段部31と
下段部32との間に段差33が設けられている。段差3
3の大きさは表示パネル1とFPC5の厚さの差と等し
くすれば良いが、接着剤4の厚さで調整できるので、厳
密に両者の厚さの差に等しくする必要はない。
Next, as shown in FIG. 5, alignment is performed using the alignment marks 15 provided on the display panel substrate 1 and the FPC 5 which are adhered to the lower portion 32 of the auxiliary substrate 3, respectively. Continuing, as shown in FIG.
The FPC 5 is heated to 80 to 120 ° C. while pressing the FPC 5 via the adhesive 4 with a heat tool to cure and bond the adhesive 4. In this state, a step 33 is provided between the upper step portion 31 and the lower step portion 32 of the auxiliary substrate 3 so that the display drive connection electrode 2 and the metal wiring 6 are arranged substantially on the same plane. Step 3
The size of 3 may be equal to the difference in thickness between the display panel 1 and the FPC 5, but since it can be adjusted by the thickness of the adhesive 4, it is not necessary to strictly equalize the difference in thickness between the two.

【0018】さらにヒートツールを用いるとき表示パネ
ル基板1の表示駆動接続電極2にもヒートツールが当た
るようにすればFPC5の金属配線6と表示パネル基板
1の表示駆動接続電極2との高さを揃えることが容易と
なる。また、補助基板3の上段部31の幅寸法は、すく
なくとも半導体チップ7上の入力突起電極8の幅よりも
大きければよく、0.1mm〜5mmあればよい。また
補助基板3の下段部32の幅寸法は、すくなくとも半導
体チップ7上の出力突起電極9の幅よりも大きく、また
表示パネル構成部に掛からない大きさであればよく、
0.1mm〜5mmあればよい。
Further, when the heat tool is used, the height of the metal wiring 6 of the FPC 5 and the display drive connecting electrode 2 of the display panel substrate 1 can be increased by contacting the display drive connecting electrode 2 of the display panel substrate 1 with the heat tool. It becomes easy to align. The width dimension of the upper step portion 31 of the auxiliary substrate 3 may be at least larger than the width of the input protruding electrode 8 on the semiconductor chip 7, and may be 0.1 mm to 5 mm. Further, the width dimension of the lower step portion 32 of the auxiliary substrate 3 may be at least larger than the width of the output projecting electrode 9 on the semiconductor chip 7, and may be a size that does not hang on the display panel constituent portion,
It may be 0.1 mm to 5 mm.

【0019】接着剤4は、液状の場合は、ディスペンサ
で補助基板3の上段部31および補助基板3の下段部3
2に供給し、フィルム状接着剤4の場合はそれぞれに対
応する大きさに切り出して張り付ける。いずれにしても
接着剤4は、補助基板3上に設けても、或いはFPC5
側および表示パネル基板1側に設けても、どちらでもよ
い。また接着剤4は、エポキシ等の樹脂に接着厚さ調整
用の粒径がプラスマイナス10%以内で揃ったプラッス
チックビーズや、ガラスファイバーを5〜30wt%混
入したものを使用するのが望ましい。これにより接着剤
4の厚さを制御することが容易となる。
When the adhesive 4 is liquid, a dispenser is used to dispense an upper step 31 of the auxiliary substrate 3 and a lower step 3 of the auxiliary substrate 3.
2, and in the case of the film adhesive 4, the adhesive is cut out into a size corresponding to each and stuck. In any case, the adhesive 4 may be provided on the auxiliary substrate 3 or the FPC 5
It may be provided either on the display side or the display panel substrate 1 side. Further, as the adhesive 4, it is desirable to use plastic beads having a particle size for adjusting the adhesive thickness within plus or minus 10% and glass fibers mixed in 5 to 30 wt% in resin such as epoxy. This makes it easy to control the thickness of the adhesive 4.

【0020】つぎに半導体チップ7に入力突起電極8と
出力突起電極9をメッキ法や真空蒸着法で銅や金の金属
を用いて形成する。この入力突起電極8と出力突起電極
9の形状は直径50〜200μmの円形が好ましい。つ
ぎに、前記入力突起電極8と出力突起電極9の先端部に
エポキシ系の接着剤に導電粒を混入した導電性接着剤1
0を印刷法やディップ法で一定量を塗布する。 その
後、図5に示すように双眼顕微鏡を用いて半導体チップ
7と表示パネル基板1に配置した表示駆動接続電極2と
FPC上の金属配線6との位置を合わせを行い、図1に
示すように表示駆動接続電極2および金属配線6にそれ
ぞれ出力突起電極9および入力突起電極8を接続する。
この後50〜150℃の温度で加熱処理を行い導電性接
着剤10を硬化させた。これにより出力突起電極9と表
示駆動接続電極2および入力突起電極8と金属配線6は
良好な電気的接続が得られた。最後にFPC5と半導体
チップ7、および表示パネル基板1の周辺領域にエポキ
シ系や、ゴム系などの有機材料からなる絶縁性樹脂11
を充填し、その後、絶縁性樹脂11を加熱硬化させる。
Next, the input projecting electrode 8 and the output projecting electrode 9 are formed on the semiconductor chip 7 by using a metal such as copper or gold by a plating method or a vacuum deposition method. The shapes of the input protruding electrode 8 and the output protruding electrode 9 are preferably circular with a diameter of 50 to 200 μm. Next, a conductive adhesive 1 in which conductive particles are mixed with epoxy adhesive at the tips of the input protruding electrode 8 and the output protruding electrode 9
A fixed amount of 0 is applied by a printing method or a dipping method. Thereafter, as shown in FIG. 5, the display drive connection electrodes 2 arranged on the semiconductor chip 7 and the display panel substrate 1 and the metal wirings 6 on the FPC are aligned using a binocular microscope, and as shown in FIG. The output projection electrode 9 and the input projection electrode 8 are connected to the display drive connection electrode 2 and the metal wiring 6, respectively.
Then, heat treatment was performed at a temperature of 50 to 150 ° C. to cure the conductive adhesive 10. As a result, good electrical connection was obtained between the output projection electrode 9 and the display drive connection electrode 2, and between the input projection electrode 8 and the metal wiring 6. Finally, in the peripheral area of the FPC 5, the semiconductor chip 7, and the display panel substrate 1, an insulating resin 11 made of an organic material such as epoxy or rubber is used.
And then the insulating resin 11 is cured by heating.

【0021】画面サイズが対角4インチの単純マトリッ
クス方式液晶パネルの実装において、信号電極用半導体
チップはCOG法で接続し、走査電極用半導体チップを
本発明の実装構造で接続した結果、クロストークの少な
い良好な表示画像が得られ、実装中および完成後におい
ても接続部が破損する現象は発生しなかった。
In mounting a simple matrix type liquid crystal panel having a diagonal size of 4 inches, the signal electrode semiconductor chips are connected by the COG method, and the scanning electrode semiconductor chips are connected by the mounting structure of the present invention, resulting in crosstalk. A good display image with few defects was obtained, and the phenomenon that the connection part was damaged did not occur during mounting and after completion.

【0022】本発明の実施例の説明では、補助基板3の
材料を熱硬化性のエポキシ樹脂を使用した例で説明した
が適度な剛性を持ち、200℃以上の耐熱性があれば、
金属、セラミック、プラスチック等自由に選択できる。
また、本発明の実施例の説明では、半導体チップの実装
構造を導電性接着剤を使用した例で説明したが、導電性
接着剤の代わりに、光硬化性樹脂や異方導電性シートや
導電性ビーズを使用して、半導体チップ7の入力突起電
極8および出力突起電極と、表示パネル基板1の表示駆
動接続電極2およびFPC5の金属配線6とをそれぞれ
接続しても、同様の結果が得られた。なお、光硬化性樹
脂を使用した場合は図1に示す絶縁樹脂11は不要とな
る。また図3では補助基板3の下段部32と表示パネル
基板1との接着を液晶表示パネルの画像表示部分が完成
した後で行っているが、液晶表示パネルの画像表示部分
が完成する前の工程において、表示パネル基板1へ表示
駆動接続電極2を形成した後に補助基板3の下段部32
に接着してもよい。
In the description of the embodiments of the present invention, the material of the auxiliary substrate 3 is an example in which a thermosetting epoxy resin is used. However, as long as it has appropriate rigidity and heat resistance of 200 ° C. or higher,
Metal, ceramic, plastic, etc. can be freely selected.
Further, in the description of the embodiments of the present invention, the mounting structure of the semiconductor chip is described as an example using a conductive adhesive, but instead of the conductive adhesive, a photocurable resin or an anisotropic conductive sheet or a conductive material is used. Even if the input projecting electrode 8 and the output projecting electrode of the semiconductor chip 7, the display drive connecting electrode 2 of the display panel substrate 1 and the metal wiring 6 of the FPC 5 are connected to each other using the conductive beads, the same result is obtained. Was given. When the photo-curable resin is used, the insulating resin 11 shown in FIG. 1 is unnecessary. Further, in FIG. 3, the lower part 32 of the auxiliary substrate 3 and the display panel substrate 1 are adhered to each other after the image display portion of the liquid crystal display panel is completed, but the process before the image display portion of the liquid crystal display panel is completed. In the above, after the display drive connection electrode 2 is formed on the display panel substrate 1, the lower part 32 of the auxiliary substrate 3 is formed.
May be adhered to.

【0023】[0023]

【発明の効果】以上に述べたように本発明によれば、C
OG法の特徴である半導体チップの出力突起電極と表示
パネル基板の表示駆動接続配線の接続を高密度で実現し
ながら、半導体チップへの入力抵抗を数オーム以下で接
続でき、入力電源電圧が安定することにより表示装置の
クロストーク現象を低減することができる。さらに補助
基板が接続部を補強することにより半導体チップの実装
工程中または完成後に誤って加わる外力に対しても接続
部の破損を防止することができ接続信頼性を向上させる
ことができる。
As described above, according to the present invention, C
The output projection electrode of the semiconductor chip and the display drive connection wiring of the display panel substrate, which is a feature of the OG method, can be connected with high density, and the input resistance to the semiconductor chip can be connected within a few ohms, and the input power supply voltage is stable. By doing so, the crosstalk phenomenon of the display device can be reduced. Further, the auxiliary substrate reinforces the connection portion, so that the connection portion can be prevented from being damaged even if an external force is erroneously applied during or after the semiconductor chip mounting process, and the connection reliability can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例における半導体チップの実装構
造の断面形状を示す模式拡大図である。
FIG. 1 is a schematic enlarged view showing a cross-sectional shape of a semiconductor chip mounting structure according to an embodiment of the present invention.

【図2】本発明の実施例における補助基板の断面形状を
示す模式拡大図である。
FIG. 2 is a schematic enlarged view showing a cross-sectional shape of an auxiliary substrate in an example of the present invention.

【図3】本発明の実施例における接続工程を説明するた
めの実装構造の断面形状を示す模式拡大図である。
FIG. 3 is a schematic enlarged view showing the cross-sectional shape of the mounting structure for explaining the connecting step in the example of the present invention.

【図4】本発明の実施例における接続工程を説明するた
めの実装構造の断面形状を示す模式拡大図である。
FIG. 4 is a schematic enlarged view showing the cross-sectional shape of the mounting structure for explaining the connecting step in the example of the present invention.

【図5】本発明の実施例における半導体チップの実装構
造の平面形状を示す模式拡大図である。
FIG. 5 is a schematic enlarged view showing a planar shape of a semiconductor chip mounting structure according to an embodiment of the present invention.

【図6】従来例における半導体チップの実装構造の断面
形状を示す模式拡大図である。
FIG. 6 is a schematic enlarged view showing a cross-sectional shape of a semiconductor chip mounting structure in a conventional example.

【図7】従来例における半導体チップの実装構造の断面
形状を示す模式拡大図である。
FIG. 7 is a schematic enlarged view showing a cross-sectional shape of a semiconductor chip mounting structure in a conventional example.

【図8】従来例における半導体チップの実装構造の断面
形状を示す模式拡大図である。
FIG. 8 is a schematic enlarged view showing a cross-sectional shape of a semiconductor chip mounting structure in a conventional example.

【符号の説明】[Explanation of symbols]

1 表示パネル基板 2 表示駆動接続電極 3 補助基板 4 接着剤 5 フレキシブル印刷基板 6 金属配線 7 半導体チップ 8 入力突起電極 9 出力突起電極 10 導電性接着剤 11 絶縁樹脂 12 異方導電性シート 15 位置合わせマーク 18 入力突起電極 19 出力突起電極 20 表示パネル 21 入力接続電極 31 上段部 32 下段部 33 段差 1 Display Panel Substrate 2 Display Drive Connection Electrode 3 Auxiliary Substrate 4 Adhesive 5 Flexible Printed Board 6 Metal Wiring 7 Semiconductor Chip 8 Input Projection Electrode 9 Output Projection Electrode 10 Conductive Adhesive 11 Insulating Resin 12 Anisotropic Conductive Sheet 15 Positioning Mark 18 Input protruding electrode 19 Output protruding electrode 20 Display panel 21 Input connection electrode 31 Upper stage 32 Lower stage 33 Step

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 金属配線を有するフレキシブル印刷基板
と、表示パネルの一部を構成し周辺部に表示駆動接続電
極を有する表示パネル基板と、前記フレキシブル印刷基
板および前記表示パネル基板の両者にまたがり前記金属
配線および前記表示駆動接続配線にそれぞれ導電性接着
剤により接着されている入力突起電極および出力突起電
極を有する半導体チップと、前記フレキシブル印刷基板
および前記表示パネル基板の両者にまたがって裏打ちさ
れ両者の当接部を補強する補助基板とからなる実装構造
であって、前記補助基板は段差により高さの異なる上段
部および下段部を有し、前記金属配線および前記表示駆
動接続電極が、ほぼ同一平面上に並ぶように前者を上段
部に後者を下段部にそれぞれ接着固定していることを特
徴とする表示パネル駆動用半導体チップの実装構造。
1. A flexible printed circuit board having a metal wiring, a display panel circuit board which constitutes a part of a display panel and has a display drive connection electrode in a peripheral portion thereof, and the flexible printed circuit board and the display panel circuit board. A semiconductor chip having an input projecting electrode and an output projecting electrode, which are adhered to the metal wiring and the display drive connection wiring by a conductive adhesive, respectively, and both of them are lined with the flexible printed board and the display panel board. A mounting structure comprising an auxiliary substrate that reinforces the contact portion, wherein the auxiliary substrate has an upper step portion and a lower step portion having different heights due to steps, and the metal wiring and the display drive connection electrode are substantially in the same plane. A display panel characterized in that the former is adhered and fixed to the upper part and the latter is adhered to the lower part so that they are lined up. Drive semiconductor chip mounting structure.
JP7178418A 1995-07-14 1995-07-14 Mount structure for semiconductor chip for driving display panel Pending JPH0933940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7178418A JPH0933940A (en) 1995-07-14 1995-07-14 Mount structure for semiconductor chip for driving display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7178418A JPH0933940A (en) 1995-07-14 1995-07-14 Mount structure for semiconductor chip for driving display panel

Publications (1)

Publication Number Publication Date
JPH0933940A true JPH0933940A (en) 1997-02-07

Family

ID=16048158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7178418A Pending JPH0933940A (en) 1995-07-14 1995-07-14 Mount structure for semiconductor chip for driving display panel

Country Status (1)

Country Link
JP (1) JPH0933940A (en)

Cited By (7)

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US6917104B2 (en) 2002-03-06 2005-07-12 Seiko Epson Corporation Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument
US6965164B2 (en) 2003-04-22 2005-11-15 Seiko Epson Corporation Electronic device and method of manufacturing the same
US7235879B2 (en) 2003-04-21 2007-06-26 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, electronic device and method of manufacturing the same, and electronic instrument
US7307854B2 (en) 2003-03-03 2007-12-11 Nitto Denko Corporation Flexible wired circuit board
CN100410740C (en) * 2004-07-13 2008-08-13 精工爱普生株式会社 Electro-optic devices and electronics
CN102548257A (en) * 2011-12-21 2012-07-04 惠州Tcl移动通信有限公司 Support reinforcing device, support reinforcing piece and side key device
KR20160043518A (en) * 2014-10-13 2016-04-21 제네럴 일렉트릭 컴퍼니 Power overlay structure having wirebonds and method of manufacturing the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6917104B2 (en) 2002-03-06 2005-07-12 Seiko Epson Corporation Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument
US7186584B2 (en) 2002-03-06 2007-03-06 Seiko Epson Corporation Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument
US7307854B2 (en) 2003-03-03 2007-12-11 Nitto Denko Corporation Flexible wired circuit board
US7235879B2 (en) 2003-04-21 2007-06-26 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, electronic device and method of manufacturing the same, and electronic instrument
US7662673B2 (en) 2003-04-21 2010-02-16 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, electronic device and method of manufacturing the same, and electronic instrument
US6965164B2 (en) 2003-04-22 2005-11-15 Seiko Epson Corporation Electronic device and method of manufacturing the same
CN100410740C (en) * 2004-07-13 2008-08-13 精工爱普生株式会社 Electro-optic devices and electronics
US7518691B2 (en) 2004-07-13 2009-04-14 Seiko Epson Corporation Electrooptical device, mounting structure, and electronic apparatus having wiring formed on and protruding from a base material to directly under an input bump on a semiconductor device
CN102548257A (en) * 2011-12-21 2012-07-04 惠州Tcl移动通信有限公司 Support reinforcing device, support reinforcing piece and side key device
KR20160043518A (en) * 2014-10-13 2016-04-21 제네럴 일렉트릭 컴퍼니 Power overlay structure having wirebonds and method of manufacturing the same
JP2016082230A (en) * 2014-10-13 2016-05-16 ゼネラル・エレクトリック・カンパニイ Power overlay structure having wirebonds and method of manufacturing the same

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