JPH09331238A - Semiconductor integrated circuit - Google Patents

Abstract

(57) Abstract: A variation in the width of a reference pulse is suppressed with respect to a variation in a gate length. SOLUTION: Each of a pulse generation circuit 9 and a pulse expansion circuit 10 constituting a circuit 90 for generating a reference pulse B-PULSE used for controlling various circuits 16 and 24 in a memory 1 is an input pulse. A delay circuit for delaying (clock CLK0 or pulse A-PULSE), and a logic gate for generating a pulse having a desired pulse width from its output and this input pulse. Variation in gate length at the time of manufacturing transistors belonging to this delay circuit
Since it affects the variation of the pulse width of the generated reference pulse B-PULSE, the gate length of these transistors is made larger than the gate lengths of other transistors on the same integrated circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a pulse generation circuit and including a metal insulator transistor.

[0002]

2. Description of the Related Art In many conventional semiconductor integrated circuits composed of metal-insulator transistors (herein referred to as MIS transistors for simplification or simply transistors), an externally supplied clock signal is converted into this clock signal. On the other hand, it has a reference pulse generating circuit for generating a reference pulse having a predetermined pulse width, and based on this reference pulse, various drive circuits generate a plurality of drive pulses, and these plurality of drive pulses are generated by these drive pulses. It is supplied to a controlled circuit common to the drive circuit. Even if the phase difference between these drive pulses is slightly deviated, the rising time and pulse width of these drive pulses are determined so that the controlled circuit operates normally.

Hereinafter, as an example of such a semiconductor integrated circuit, a static random access memory (hereinafter referred to as a static RAM for simplification) is used. In this memory, the memory cell array is divided into a plurality of mats, and a plurality of word line drivers, a plurality of Y decoders, and a plurality of precharge circuits corresponding to the respective mats are provided. Common to these mats, an X decoder, a reference pulse generation circuit, an address pulse conversion circuit, a mat decoder, a sense amplifier, a READ / WRITE switch, or these sense amplifiers, READ / W
A control signal generation circuit for controlling the RITE switch is provided. A clock signal is externally applied to the reference pulse generating circuit, an external control signal is externally applied to the control signal generating circuit, a Y address is externally applied to the plurality of Y decoders, and an X address is applied to the X decoder.
The X address is given from the outside.

The reference pulse generation circuit is a pulse generation circuit which generates a pulse having a predetermined pulse width in synchronization with an externally applied clock signal, and a pulse which extends the generated pulse to generate a reference pulse. A decompression circuit is used.

A predecode circuit predecodes an externally applied mat address signal, and the address pulse converting circuit pulses the predecoded mat address signal. The mat decoder decodes the pulsed mat address signal, and supplies a signal representing the decoded result to the plurality of word line drivers, the plurality of Y decoders, the plurality of precharge circuits, and the control signal generation circuit. In response to the reference pulse, the plurality of word line drivers, the plurality of Y decoders, and the plurality of precharge circuits specify the word line drive pulse, the Y switch drive signal, and the precharge pulse by the mat address signal. Supply to memory mat. Further, the control signal generation circuit supplies pulses for driving these to the sense amplifier and the READ / WRITE switch in response to the output pulse of the mat decoder. Also, the precharge signal is
It is configured to start after the word line drive pulse ends.

In order for the memory to operate normally, it is necessary that each drive pulse rise at a predetermined timing and have a predetermined pulse width. However, in practice, the rise timing and pulse width of each drive pulse fluctuate due to variations in transistor dimensions during the manufacture of semiconductor integrated circuits, so even if fluctuations occur within a certain range, the memory will operate normally. The rising timings and pulse widths of the plurality of drive pulses are determined so as to operate in the above manner. In particular, it is devised so that the rising timings of different pulses are relatively coincident with each other, despite variations in manufacturing the integrated circuit. For example, the address pulse conversion circuit delays the reference pulse with respect to the clock signal and the clock of the predecoded mat address signal so that the reference pulse and the predecoded mat address signal are supplied at the same timing. The circuit for generating these signals and the circuit for propagating these signals are configured such that the delay with respect to the signals is substantially the same regardless of the manufacturing variation. Similarly, the reference pulse decoded by the matte decoder supplied to the word line driver and the decoded X address supplied from the X decoder to the word line driver have substantially the same timing. , A circuit for generating these signals and a circuit for propagating these signals are configured.

[0007]

The above memory operates normally when used with a relatively low speed clock, for example 60 Mhz, but it is attempted to drive this memory with a higher speed clock, for example 100 Mhz. , The present inventor found the following problem. That is, in the conventional reference pulse generation circuit, fluctuations in the pulse width of the generated reference pulse due to manufacturing variations in the semiconductor integrated circuit may impair normal memory operation at the high-speed clock. Occurs. Specifically, when the reference pulse has a minimum pulse width within the variation range of the pulse width of the reference pulse due to manufacturing variations of the semiconductor integrated circuit, the pulse width of the word line drive pulse is transferred to the memory cell. The pulse width becomes shorter than the pulse width required to complete the writing of data. Further, when the pulse width of the reference pulse has the maximum pulse width within the above fluctuation range,
The pulse width of the precharge pulse becomes shorter than the width required to complete the precharge.

Such a problem is not limited to the above memory,
A reference pulse generation circuit is provided, and various drive circuits generate a plurality of drive pulses based on the reference pulse generated by this circuit, and the plurality of drive pulses are controlled circuits common to these drive circuits. The same applies to the general semiconductor integrated circuit described above which is configured to be supplied to the semiconductor integrated circuit.

An object of the present invention is to provide a semiconductor integrated circuit suitable for high-speed operation, in which a reference pulse having a small pulse width variation due to manufacturing variations of the semiconductor integrated circuit can be used even when operating with a high-speed clock, and the same. It is to provide a suitable pulse generation circuit.

A more specific object of the present invention is to provide a semiconductor integrated circuit capable of securing a data writing period and a precharge period for a word line even when operating with a high-speed clock, despite manufacturing variations of the semiconductor integrated circuit. It is to provide a circuit memory.

[0011]

In order to solve the above-mentioned problems, in the semiconductor integrated circuit according to the present invention, in the case where the gate length varies among the plurality of transistors forming the pulse generation circuit at the time of manufacturing the semiconductor integrated circuit. In order that the gate lengths of the plurality of transistors that change the pulse width of the pulse to be generated are longer than the gate lengths of the other plurality of transistors in the semiconductor integrated circuit including this circuit, The gate length is set.

According to a more specific aspect of the present invention, the pulse generation circuit delays a clock signal, and at least one logic for generating a pulse having a predetermined pulse width from the delayed clock signal. The gate length of the plurality of transistors that have gates and constitute the delay circuit is longer than that of the other plurality of transistors of this semiconductor integrated circuit.

Another more specific aspect of the present invention has a plurality of drive circuits which generate a plurality of drive pulses to be applied to the same controlled circuit in response to the generated pulses.
The plurality of drive pulses include a first drive pulse that should have a pulse width of a predetermined pulse width or more, and a pulse width of a predetermined pulse width or more that should be applied when the first drive pulse ends. A second drive pulse which should have

Still another specific aspect of the present invention is a clock composed of a plurality of MIS transistors for generating another clock signal in response to a clock signal and having the time difference between the clock signal and the reference pulse. A signal output circuit that takes in and outputs an access signal to be used for accessing the signal generation circuit and the controlled circuit in response to the other clock signal, and the reference pulse and the signal output circuit. A pulsing circuit that generates a control pulse that represents the access signal during a period in which the reference pulse is valid, in response to the access signal, and is applied to the controlled circuit in response to the control pulse. A plurality of drive circuits each including a plurality of MIS transistors for generating one of a plurality of drive pulses to be generated. .

[0015]

FIG. 1 shows a synchronous static RAM according to the present invention formed in a semiconductor integrated circuit. This memory is composed of a CMOS circuit using a PMOS transistor and an NMOS transistor as the MIS transistor. In the present embodiment, as in the conventional case, the number of logic gate stages in the paths for propagating two signals to be supplied in synchronization with each other is made substantially equal, so that the logic due to variations in manufacturing of the semiconductor integrated circuit is caused. Even if the delay time of the gate fluctuates, a relative delay does not occur between these signals.
In the present embodiment, further, due to the variation in the gate length of the MOS transistor due to the manufacturing variation of the integrated circuit,
It is configured to reduce variations in pulse width of the various pulses. That is, this circuit 9 is used to reduce variations in the pulse width of the reference pulse generated by the reference pulse generation circuit 96, which is used to generate these pulses.
The gate length of the MOS transistor which controls the pulse width of the reference pulse in 6 is made larger than the gate lengths of the other MOS transistors in this semiconductor integrated circuit.
In this embodiment, the gate lengths of these other transistors are the same, but they may have different gate lengths depending on the purpose of use. Hereinafter, these two types of gate lengths are represented by L1 and L0, and may be referred to as an expanded gate length and a reference gate length.

This memory comprises a plurality of memory mats 17. Here, this mat number is assumed to be 128. The clock used for this memory is assumed to be a high speed clock, for example, a 100 Mhz clock. The clock, the external control signal, the mat address signal, the Y address signal, and the X address signal are input buffers 2A and 2B, respectively.
It is input through 2C, 2D and 2E. The input / output signal is input or output through the input buffer 2F and the output buffer 3. This memory has multiple memory mats 1
7, a Y decoder 13, a Y switch 14, a word line driver 16, and a precharge circuit 24 are provided for each of them, and circuits other than these circuits are provided in common for these plurality of memory mats. ing. The mat address signal is a signal for selecting the mat,
The X address is a signal for selecting the word line on the mat, the Y address is a signal for selecting the Y switch 14 on the mat, and the external control signal controls the sense amplifier 19 and the like. Is a signal for.

The clock branch circuit 23 is composed of MOS transistors each having a reference gate length for delaying the input clock CLK0.
Clocks CLK3, CLK6, CL delayed by respective logic gate rows
K7 and CLK8 are generated.

The reference pulse generation circuit 96 has a delayed clock CLK3 generated by the clock branch circuit 23.
From the reference pulse B-PULS having a predetermined pulse width
It generates E and includes a pulse generation circuit 9 and a pulse expansion circuit 10. Details of these circuits will be described later.

The predecoder 4C operates as a partial decoder for decoding some bits of the mat address input from the input buffer 2C. Other predecoder 4
The same applies to D and 4E. Register 6 is clock CLK8
In response to this, the decoding result of the predecoder 4C is held, and the mat address MATADD is output in synchronization with this clock. The address pulse converting circuit 11 supplies the mat address MATADD supplied from the register 6 via the two-stage logic gate array 90, and the reference pulse B supplied from the reference pulse generating circuit 960 via the four-stage logic gate array 91.
-PULSE pulsed, reference pulse B-PUL
A mat address signal with the same pulse width as SE is output.
This circuit, as shown in FIG.
N to which ATADD and pulse B-PULSE are input
It is composed of an AND gate NAND5 and an inverter INV4 connected to it. These logic gate columns 90, 9
1 and the logic gate trains 93, 94 and 95 described later are
It is for adjusting the propagation time of the signal. The mat decoder 12 decodes the pulsed mat address signal ADD-PULSE to simultaneously select 32 memory mats from 128 mats 17 and 32 word corresponding to the selected memory mats. The line driver 16 is activated via the logic gate array 92.

The predecoder 4E decodes the X address signal input from the input buffer 2E, the register 8 holds the decoded result in response to the clock CLK8, and outputs the X address signal in synchronization with this clock. To do. The X decoder 15 decodes this X address signal supplied through the two-stage logic gate array 95, and outputs the decoded result signal XAD.
D is supplied to the word line driver 16. The word line driver 16 pulsates the decoding result signal XADD with the pulsed mat address signal ADD-PULSE, and the pulsed mat address ADD-PULSE.
Outputs a pulse with the same pulse width as. That is, the word line designated by the decoding result signal XADD in each of the memory mats selected by the mat address signal ADD-PULSE is added to the mat address signal ADD-PULSE.
Word line drive pulse WOR that is valid while SE is valid
Supply D. Thus, the reading of the memory cell connected to the word line is activated.

The predecoder 4D decodes the Y address signal input from the input buffer 2D, the register 7 holds the decoded result in response to the clock CLK8, and outputs the Y address signal in synchronization with this clock. To do. 12
Of the eight Y decoders 15, two stages of logic gate arrays 92,
Each of the 32 Y decoders selected by the pulsed mat address signal ADD-PULSE provided via the three-stage logic gate array 93 has a Y corresponding thereto.
The switch 14 is activated according to this Y address signal.

The register 5 fetches the external control signal input from the input buffer 2B in synchronization with the clock CLK7. The control signal generation circuit 18 receives the pulsed mat address signal MATADD supplied from the mat address decoder 12 via the two-stage logic gate array 94.
This external control signal supplied from the register 5 is pulsed to generate control signals for the sense amplifier 19, the Read / Write switch 20, and the like.

Output MATAD from mat decoder 12
D is input to the precharge circuit 24 as a precharge activation signal PRE-PULSE through the two-stage logic gate array 92. The precharge circuit 24 is composed of only a PMOS, PRE-PULSE is input to the gate of the PMOS, the power source is connected to the source side of the PMOS, and the data line is connected to the drain side. Therefore, PR
When E-PULSE goes low, the PMOS is activated and precharge is started.

The 32 pieces of data read out from each of the 32 selected memory mats 17 pass through the 32 selected Y switches 14 and the sense amplifier 19
Is input to the register 21, and is input to the output buffer 3 in synchronization with CLK6. After reading, when the word line is deselected (the mat address is deselected), the precharge circuit 24 is activated and the data line is precharged. Further, the write data to the memory mat 17 is taken into the register 22 through the input buffer 2 in synchronization with the clock CLK7, and is written to the memory cell mat 17 through the Read / Write changeover switch 20 and the selected Y switch 14. After the writing, when the word line is deselected (the mat address is deselected), the precharge circuit 24 is activated and the data line is precharged.

FIG. 5 shows waveforms of some of the pulses described above. In the figure, the dotted line shows that the starting point and the ending point of these pulses change due to variations in manufacturing the semiconductor integrated circuit. Precharge activation signal P
The fluctuations of the starting point of the pulse other than RE-PULSE and the ending point of this pulse PRE-PULSE are due to variations in the propagation delay time in the transistors of the logic gates that constitute the propagation path of those pulses due to variations in manufacturing.
On the other hand, the end points of the pulses other than the precharge activation signal PRE-PULSE and the variation of the starting point of the pulse PRE-PULSE are caused by the variation of the starting points of the pulses described above and the generation of those pulses due to manufacturing variations. This is due to variations in the pulse width of the reference pulse B-PULSE, which is the original.

The width of the word line pulse needs to be a certain value or more in consideration of writing to the memory cell. Therefore, in order to secure a margin for writing data to the word line as much as possible, it is preferable to generate the word line drive pulse WORD by making maximum use of the width of the reference pulse B-PULSE generated by the reference pulse generation circuit 96. If the reference pulse B-PULSE is input to the address pulse conversion circuit 11 earlier than the mat address MATDDD, or the pulsed address ADD-PULSE is input to the word line driver 16 earlier than the X address XADD, the result is as follows. The pulse width of the word line drive pulse WORD becomes short, which reduces the margin for writing data to the memory cell.

To secure the precharge time of the data line, it is preferable to close the word line as soon as possible and start precharging the data line as soon as possible. For example, when the reference pulse B-PULSE lags behind the mat address MATADD, the precharge activation signal PRE-PUL
SE is delayed, and as a result, the precharge start time is delayed and the data line precharge time is reduced.

Further, in the present embodiment, the word line driver 16 uses the pulsed mat address ADD-P.
ULSE and the X address signal XADD are input to activate the selected word line by the NOR gate, and the precharge circuit 24 further activates the data line by the PMOS to which the precharge activation signal PRE-PULSE is input. Since the precharge is performed, the signal propagation delay time by the word line driver 16 and the precharge circuit 24 is one logic gate delay. The pulsed mat address ADD-PULSE is the X address X
If it is delayed from ADD, the timings of the word line drive pulse WORD and the precharge activation signal PRE-PULSE are deviated, precharge is started when WORD is rising, and data may be corrupted.

As a result, in the address pulse conversion circuit 11, the basic pulse (B-PULSE) generated by the pulse generation circuit 9 and the expansion circuit 10 and the mat address signal (MA) are generated.
In the TADD) and the word line driver 16, it is the timing with the largest margin that the pulsed mat address signal (ADD-PULSE) and the X address signal (XADD) are simultaneously input (FIG. 8).

Therefore, in this embodiment, as can be seen from FIG. 58, the reference pulse B-PULSE and the mat address arrive at the address pulsing circuit 11 at the same time despite the variation in the propagation delay time. In addition, the propagation path of each pulse is configured. Similarly, the propagation paths of these signals are configured such that the address pulse ADD-PULSE and the pulsed X address XADD arrive at the word line driver 16 at the same time. Further, as described above, since the precharge circuit 24 activates the data line by the PMOS, the precharge activation signal PRE- is activated at the time when the start point of the pulsed mat address ADD-PULSE reaches the word line driver 16. The end point of PULSE arrives at the precharge circuit 24, and the pulsed mat address ADD
The propagation paths of these signals are configured such that the start point of the precharge activation signal PRE-PULSE reaches the precharge circuit 24 at the time when the end point of -PULSE reaches the word line driver 16.

Specifically, in the present embodiment, considering the delay time of the path for transferring the reference pulse B-PULSE to the address pulse conversion circuit 11 with reference to the timing of supplying the clock supplied from the outside, Input buffer 2A
Of the logic gates, three stages of logic gates for supplying the clock CLK3 to the register 5 by the clock branch circuit 23, and four stages of logic gates in the reference pulse generation circuit 960 (specifically, the pulse generation circuit 9). Inverter INV1 in FIG. 2, NOR gate NOR1 (FIG. 2), inverter INV2 in pulse expansion circuit 10, NAND gate NAND2 (FIG. 2) (FIG. 3), and four stages in logic gate array 9 This is a delay due to a total of 12 stages of logic gates.

On the other hand, the path for transferring the matte address to the address pulse converting circuit 11 is one stage of the logic gate in the input buffer 2B, and the clock CL by the clock branching circuit 23.
It is a delay due to a total of 12 logic gates by 8 logic gates for generating K8, 1 logic gate in the register 6, and 2 logic gates in the logic gate array 91, and the reference pulse B-PULSE Is a delay due to the same number of logic gates as the delay for. These logic gates are
All have standard gate lengths, and these signals have substantially the same delay in the address pulse circuit regardless of semiconductor manufacturing variations.

Further, the pulsed address ADD-P
Similarly, regarding the delay time of the transfer path until ULSE is input to the word line driver 16, the reference pulse B-PULSE is transferred to the address pulse conversion circuit 11 when the timing of supplying the clock supplied from the outside is considered as a reference. 18 stages of logic gates consisting of 12 stages of logic gates, 2 stages of logic gates in the address pulse conversion circuit 11, 2 stages of logic gates in the mat decoder 12, and 2 stages of logic gates in the logic gate array 92. It is the delay due to the gate. on the other hand,
Assume that the X address signal is supplied at the same timing as the externally supplied clock, and evaluate the delay time of the transfer path until the X address signal is transferred to the word line driver 16 based on this clock supply timing. Then, the delay time is one logic gate in the input buffer 2E, eight logic gates for supplying the clock CLK8 from the clock branch circuit 23 to the register 8, one logic gate in the register 8, and one logic gate array. This is due to 15 stages of logic gates consisting of 2 stages of logic gates in 95 and 3 stages of logic gates in the X decoder 15.
-The delay is due to a logic gate having the same number of stages as the delay time of the transfer path until PULSE is input to the word line driver 16. The difference in the number of three stages is due to the difference in wiring distance, and the substantial delay is the same. All of these logic gates have a standard gate length, and these signals have substantially the same delay in the address pulse circuit regardless of semiconductor manufacturing variations.

To match the timing of applying the word line drive pulse WORD to the word line and the timing of precharging the data line, the word line driver 16
The delay from the reception of ADD-PULSE to the start of activation of the word line is due to one logic gate stage.
The precharge circuit 24 causes the precharge activation signal PRE to
Since the delay from the reception of PULSE to the start of precharging the data line is also the delay corresponding to the logic gate of one stage, the pulsed address ADD-PULSE
The wiring lengths for transferring the precharge activation signal PRE-PULSE from the logic gate array 93 to the word line driver 16 and the precharge circuit 25 may be made substantially equal.

As described above, after the number of stages of the logic gates forming the transfer paths of the two signals to be applied to the common circuit in synchronism with each other is almost met, the MOS forming these logic gates is further added. By adjusting the diffusion layer width of the transistor, the delay received by these two signals can be extremely reduced despite the manufacturing variations of the semiconductor integrated circuit. The number of stages described above is determined as a result of such a detailed study, and even when the gate length of the transistor varies due to manufacturing variations, the timing at which the word line is driven by the word line drive pulse WORD, The timings at which the data lines finish precharging by the precharging circuit are almost the same as each other.

The pulsed mat address AD
D-PULSE is also input to the Y decoder 13,
The output is the timing at which data is output from the memory mat 17 by driving the word line, or Read / Wri.
The Y switch 14 may be opened at the timing when the data comes to the memory mat 17 through the te changeover switch 20, and the ADD-P is added at the input of the Y decoder 13.
It is not necessary to match the timing of ULSE and the Y address signal. Similarly, the pulse ADD-PULSE is also input to the control signal generation circuit 18, but the output of this circuit is
The timing of operating the sense amplifier 19, or
It suffices to match the timing at which the Read / Write switch 20 is turned on, and the control signal generation circuit 18
It is not necessary to match the timing of the pulse ADD-PULSE and the external control signal at the input.

In this way, even if the timing at which the word line starts to be driven by the word line drive pulse WORD and the timing at which the data line finishes precharging by the precharge circuit are not substantially deviated from each other, this If the memory is operated in synchronization with a clock of about 100 MHz or more, there is a problem that the margin for writing data to the word line is reduced. That is, since the pulse width of the word line drive pulse needs to be reduced to a value close to the minimum necessary by increasing the operating frequency, the pulse width of the reference pulse B-PULSE generated due to manufacturing variations of the semiconductor integrated circuit. Fluctuations can no longer be ignored. That is, when the reference pulse has the minimum pulse width within the fluctuation range of the pulse width of the reference pulse due to manufacturing variations, the pulse width of the word line drive pulse is sufficient to complete the writing of data to the memory cell. It becomes shorter than the required pulse width. Further, when the pulse width of the reference pulse has the maximum pulse width within the above variation range, the pulse width of the precharge pulse is
It is shorter than the width required to complete the precharge. Therefore, in the present embodiment, in order to suppress the fluctuation of the pulse width of the reference pulse, among the MOS transistors in the reference pulse generation circuit 96, the gate lengths of a plurality of MOS transistors that control the pulse width are set to the expanded gate length. It is set to L1.

The reference pulse generating circuit 96 comprises a pulse generating circuit 9 and a pulse expanding circuit 10. The pulse generation circuit 9, for example, as shown in FIG.
Delay circuit 25 for delaying 3 and NOR gate NO
It is composed of R1. The delay circuit 25 includes an inverter array 28 including a plurality of inverters connected in series to which CLK3 is input, a NOR gate NOR2 to which an output of the inverter array 28 is input, and an input terminal of any one of the inverters and a power supply potential. It includes a PMOS transistor group 26 composed of a plurality of pairs of PMOS transistors connected in series between them, and an NMOS transistor group 27 composed of a plurality of pairs of NMOS transistors connected in series between the input terminal of any inverter and the ground potential. . N
MOS transistor group 27, PMOS transistor group 2
Reference numeral 6 denotes a MOS transistor for delay time adjustment, which uses only the gate capacitance and adjusts the delay time by a metal option. The metal option refers to mask modification of only the wiring layer and the contact layer to obtain a desired connection. The other input of the NOR gate NOR2 is a test signal, and this test signal has a low level during normal operation. Therefore, during normal operation,
This NOR gate functions as an inverter for the output of the inverter array 28 and as a delay element for the clock CLK3. In a semiconductor integrated circuit that does not use such a test signal, the NOR gate NOR2
Can be converted into an inverter.

The PMOS transistor group 26 and the NMOS transistor group 27 provide additional capacitance for increasing the delay time by the inverter array 28. One gate of each pair of PMOS transistors in the PMOS transistor group 26 is connected to the gate of one of the inverters, and its source and drain are the gate and source of the other PMOS transistor of the PMOS transistor pair. It is connected to the drain and also to the power supply potential. The same applies to the NMOS transistor group 27. In FIG. 2, two PMOS transistors and two NMOS transistors are connected to all the inverters for simplification, but the number of MOS transistors actually included in these PMOS transistor group 26 and NMOS transistor group 27 is , The delay circuit 25 is selected to match the target delay time.

The pulse output to the output node NOD1 of the delay circuit 25 and the pulse output to the output node NOD2 of the NOR gate NOR1 are as shown in FIG. The pulse output to the output node NOD2 of the NOR gate NOR1 is the output pulse A-PU of the pulse generating circuit 9.
It is used as LSE and has a pulse width equal to the delay time by the delay circuit 25 with respect to the clock CLK3. The rising edge of the pulse A-PULSE is delayed by the delay time of the NOR gate NOR1 with respect to the clock CLK0, but these gates do not affect the pulse width. After all, the inverters INV1 and N of FIG.
The delay of circuit elements other than the OR gate NOR1 determines the pulse width of the output pulse A-PULSE.

The pulse expansion circuit 10 outputs the output pulse AP of the pulse generation circuit 9 as shown in FIG. 3, for example.
It is composed of an inverter INV2 to which ULSE is input and three cascaded partial pulse expansion circuits 60, 70 and 80. The expansion circuit 60 includes a delay circuit 60A to which the output of the inverter INV2 is input, and a NAND gate NAND2 to which the output and the output of the inverter INV2 are input.
Consists of. The structure of the delay circuit 60A has basically the same structure as the circuit obtained by converting the NOR circuit NOR2 from the delay circuit 25 into an inverter, and includes an inverter array 36, a PMOS transistor group 30, and an NMOS transistor group 31. The expansion circuit 70 includes a delay circuit 70A to which the output of the expansion circuit 60 is input, an output of the delay circuit 70A, and an inverter INV2.
It is composed of a NAND gate NAND3 to which the output of is input. Similarly, the decompression circuit 80 includes a delay circuit 80A to which the output of the decompression circuit 70 is input, its output, and an inverter IN.
It is composed of a NAND gate NAND1 to which the output of V2 is input. The structure of the delay circuits 70A and 80A is the same as that of the delay circuit 60.
And an inverter array 37 or 38, a PMOS transistor group 37 or 38, and N
It is composed of a MOS transistor group 33 or 35.

The pulse output to the output node NOD3 of the delay circuit 60A and the pulse output to the output node NOD4 of the pulse expansion circuit 60 are as shown in FIG. 7, and the pulse output to this output node NOD4 is a pulse. The pulse A-PULSE generated by the generation circuit 9 is expanded by the delay time of the delay circuit 60A. Similarly, the pulse output to the output node NOD5 of the delay circuit 70A and the pulse output to the output node NOD6 of the pulse expansion circuit 70A are as shown in FIG. 7, and the pulse output to this output node NOD6 is a pulse. The pulse A-PULSE generated by the generation circuit 9 is delayed by the delay circuit 6
Delay time due to 0A and 70A and NAND gate NAND
The pulse is extended by the delay time of 2. Similarly,
The pulse output to the output node NOD7 of the delay circuit 80A and the pulse output to the output node NOD8 of the pulse expansion circuit 80 are as shown in FIG.
The pulse B-PULSE output to the OD 8 is the pulse A-PULSE generated by the pulse generation circuit 9 and the delay circuits 60A, 70A and 80, and the NAND gate NAND.
2. The pulse is extended by the delay time of NAND3. The rising and falling of the reference pulse B-PULSE are delayed by the propagation delay time by the inverter INV2 and the NAND gate NAND1, but these gates do not affect the pulse width of the reference pulse B-PULSE. After all, the inverters INV2, N of FIG.
The delay of circuit elements other than the AND gate NAND1 determines the pulse width of the output pulse A-PULSE.

When the gate lengths of the plurality of transistors forming the delay circuit 23 in the pulse generation circuit 9 vary due to manufacturing variations of the semiconductor integrated circuit, the plurality of inverters belonging to the inverter array 28 and the NOR gate NO.
The delay time of R2 fluctuates, and this delay circuit 25
The delay time of fluctuates. This delay time variation is ± Δt0
Assuming that, as shown by the dotted line in FIG.
Although the pulse width of the delayed clock CLK0 at D1 does not change, its rising time and falling time vary by ± Δt0. Therefore, the falling time and pulse width of the pulse A-PULSE generated by the NOR gate NOR1 vary by ± Δt0.

Similarly, the dotted lines in FIG. 7 show the variations in the waveforms of the output pulses of several nodes in the pulse expansion circuit 10. The input pulse to the pulse expansion circuit 10 is the output pulse AP of the pulse generation circuit 9.
ULSE, which has the pulse width variation .DELTA..DELTA.t0 shown in FIG. 6, but FIG. 7 assumes that the input pulse to the pulse stretching circuit 10 has no such variation. Now, the variation in the delay time due to the delay circuit 60A (which is now assumed to be ± Δt1) directly affects the pulse width of the output pulse B-PULSE. That is,
Although the pulse width of the output pulse of the output node NOD3 of the delay circuit 60A does not change, both its rising time and falling time vary by ± Δt1. Therefore, the pulse width of the output pulse of the output node NOD4 of the partial pulse expansion circuit 60 varies by ± Δt1. Similarly, the variation in the delay time due to the NAND gate NAND2 and the delay circuit 70A (which is now assumed to be ± Δt2) directly affects the pulse width of the output pulse B-PULSE. That is,
The falling time and the rising time of the output pulse of the output node NOD5 of the delay circuit 70A are ± Δt2 and ±, respectively.
The variation is (Δt1 + Δt2), and the pulse width of this pulse has a variation of ± Δt1. Therefore, the pulse width of the output pulse of the output node NOD6 of the partial pulse expansion circuit 70 varies ± (Δt1 + Δt2). Similarly, variations in the delay time due to the NAND gate NAND3 and the delay circuit 80A (which is now assumed to be ± Δt3) directly affect the pulse width of the output pulse B-PULSE. That is, the falling time and rising time of the output pulse of the output node NOD7 of the delay circuit 80A vary by ± Δt3 and ± (Δt1 + Δt2 + Δt3), respectively, and the pulse width of this pulse has a variation of ± (Δt1 + Δt2). Therefore, the partial pulse expansion circuit 80
The pulse width of the output pulse of the output node NOD8 of
(Δt1 + Δt2 + Δt3) varies.

As described above, since the pulse falling time and the pulse width of the input pulse A-PULSE to the pulse expanding circuit 10 vary by ± Δt0, the pulse falling of the reference pulse B-PULSE output from the pulse expanding circuit 10 occurs. Time and pulse width are ± (Δt0 + Δt1 +
Δt2 + Δt3) It will vary. As a result, this reference pulse B-PULSE is used to vary the pulse width of the various pulses produced by the circuit shown in FIG.

The variation of the pulse width of the reference pulse affects the gate length of the transistor in the pulse generation circuit 9 and the pulse expansion circuit 10 used to generate the pulse, which influences the pulse width of the reference pulse B-PULSE. Mainly caused by variations.

Therefore, in this embodiment, variations in the gate length at the time of manufacturing the semiconductor integrated circuit influence variations in the pulse width of the reference pulse, and the gate length of the transistor used in the logic gate is selectively changed to another value. Make it larger than the transistor. Specifically, the gate lengths of the MOS transistors forming the elements other than the inverter INV1 and the NOR gate NOR1 in the pulse generation circuit 9 and the inverter INV2 inside the pulse expansion circuit 10 and the MOS transistors forming the elements other than the NAND gate NAND1 are Use the expanded gate length described above. Inverter I in pulse generation circuit 9
NV1, NOR gate NOR1, a MOS transistor forming NOR1, and an inverter INV in the pulse expansion circuit 10.
2. The MOS transistor forming the NAND gate NAND1 is a logic gate that determines the delay time of the waveform shown in FIG. 5, and thus has a reference gate length.

The delay time of the delay circuit depends on the value of the drain current Ids of the transistor forming the circuit.
When the gate length varies, the threshold varies, which causes the drain current Ids to vary, resulting in a variation in delay time. If the gate length of a transistor is large, even if the gate length changes by a constant value due to dimensional variations during manufacturing of the semiconductor integrated circuit, the gate length after the change is greater than the gate length when there is no variation (reference gate length). The ratio decreases. As a result, the ratio of the variation of the threshold voltage to the reference value is reduced, and as a result, the ratio of the variation of the drain current Ids to the reference value is reduced.
The ratio of the delay time variation of the delay circuit to the reference value is reduced. Therefore, when the delay time of the delay circuit is set so that the reference value of the generated pulse width becomes a predetermined value without depending on the gate length, the variation of the pulse width of the generated reference pulse decreases.

FIG. 8 shows the gate length dependency of the delay time per inverter. At this time, two additional NMOS transistors and two PMOS transistors for capacitance adjustment are not connected to the inverter. The channel width of the NMOS transistor of this inverter is 3μ
m, the channel width of the PMOS transistor is 6 μm,
The power supply voltage was 2.9 V and the environmental temperature was 110 ° C. As can be seen from this figure, as the gate length increases, the delay time also increases, and moreover, the variation in delay time also increases. That is, the gate length is 0.45 μm, 0.6 μm, 0.8 μm
When changed to, the delay time per inverter is
It increases to 0.091 ns, 0.132 ns, and 0.198 ns. That is, when the gate length is 1.45 times and 1.78 times with respect to 0.45 μm, the delay times are 1.29 times and 2.81 times, respectively. Due to manufacturing variations, the maximum manufacturing variation of transistor size does not depend on the gate length. Here, the maximum variation in gate length is ± 0.07 μm, and the maximum variation in oxide film thickness is 8 nm ± 5.
% (0.4 nm). As shown in the figure, when the gate length varies from 0.45 μm to 0.45 + 0.07 μm and the oxide film thickness varies from 8 nm + 5%, the delay time is 0.069 n.
When the gate length is 0.45-0.07 μm and the oxide film thickness is 8 nm-5%, the delay time is 0.11.
It will be 7 ns. Gate length from 0.60 μm to 0.60+
When 0.07 μm and the oxide film thickness vary to 8 nm + 5%, the delay time becomes 0.106 ns and the gate length becomes 0.16 ns.
When the thickness is 60-0.07 μm and the oxide film thickness is 8 nm-5%, the delay time becomes 0.165 ns. Gate length is 0.8
0μm to 0.80 + 0.07μm and oxide film thickness is 8n
When the variation is m + 5%, the delay time is 0.238 ns, and when the gate length is 0.80-0.07 μm and the oxide film thickness is 8 nm-5%, the delay time is 0.164 ns.

However, the ratio of this variation to the delay time decreases as the gate length increases. That is, the ratio of the variation to the delay time is about ± 26% at a gate length of 0.45 μm and about ± 22 at a gate length of 0.4 μm, as shown in FIG.
%, About ± 19% at 0.8 μm. That is, the degree of variation is improved to 16% at a gate length of 0.6 μm and 27% at a gate length of 0.4 μm, and to 27% at 0.8 μm. Therefore, an inverter using a transistor having a long gate length has a smaller variation rate of delay time due to manufacturing variations. Therefore, in order to generate a pulse having the same pulse width by the circuits shown in FIGS. 2 and 3, it is possible to reduce variations in pulse width by using a transistor having a long gate length. Specifically, in order to improve the variation in the gate length of 0.45 μm by 10% or more,
The expanded gate length may be 0.50 μm or more, that is, 1.2 times or more of the reference gate length 0.45 μm. Furthermore, with respect to the variation at the gate length of 0.45 μm,
To improve by more than 15%, increase the gate length by 0.59
1 μm or more, that is, a reference gate length of 0.45 μm.
It may be 31 times or more, that is, about 1.3 times or more.

FIG. 10 shows the pulse transfer characteristics of the delay circuit having the same structure as the delay circuit 25 of FIG. However, this circuit includes 10 inverters and two PMOS transistors and two NMOs connected to each inverter.
The channel lengths of the NMOS transistor and the PMOS transistor of the inverter transistor, which are S transistors, are the same as those in the case of FIG.
The channel width of the MOS transistor 38 is 6 μm, and the channel width of the delay circuit adjusting NMOS transistor 39 is 3 μm.
m. The figure shows that the gate lengths of all transistors in this delay circuit are 0.45 μm, 0.60 μm, and 0.80 μm.
The input and output waveforms when changed to m are shown. At this time, the power supply voltage was 2.9 V and the environmental temperature was 110 ° C. As a result, it can be seen that the output waveform becomes dull with respect to the input waveform when the gate length is 0.80 μm. From this, it is understood that the expanded gate length should not be 0.8 or more. That is, the expanded gate length is 0.8 with respect to the reference gate length.
It can be seen that it is better not to increase /0.45 (= 1.77) times or more, or approximately 1.80 times or more. Therefore, in this embodiment, the expanded gate length is set to 0.6 μm and the reference gate length is set to 0.45 μm. At this time, the expanded gate length is 1.33 times the reference gate length.

Further, in the present embodiment, in the pulse generation circuit 9 and the pulse expansion circuit 10, the delay time adjustment M
The gate length of the OS transistor is the same as that of the transistor forming the inverter train of the delay circuit. On the contrary, when the gate length of the delay time adjusting MOS transistor is small, the variation in the added capacitance value is larger than when the gate length is the same as the transistor forming the inverter array of the delay circuit. This is because there is a problem that variations in delay time increase. Further, when an inverter composed of a transistor having a large gate length is used, the delay time per inverter stage becomes longer than before, and in order to obtain a reference pulse with a desired pulse width, a delay time adjusting MOS transistor added to the inverter train is used. It is necessary to adjust the pulse width by the number of, and the accuracy of this adjustment becomes a problem. However, as will be described in detail later,
The delay time of one stage of the inverter is, for example, 0.198 ns.
Even if the gate length of the delay time adjusting MOS added to this is equal to the expanded gate length, it is 0.03 ns.
It is 15% of the delay time per inverter stage. Therefore, even if the gate length of the added MOS is made equal to the expanded gate length, the delay time can be determined with an accuracy of about 15%. Therefore, even if the gate length of the delay time adjustment MOS is made equal to the expanded gate length, there is no practical problem in terms of delay time adjustment accuracy. If the gate length of the delay time adjusting MOS transistor is made larger than the gate length of the delay circuit, the variation of the delay time can be reduced, but the adjustment range of the delay time becomes narrow (the adjustment step becomes large), which is not desirable.

Further, the number of delay time adjusting MOS transistors to be added per inverter stage is the same as those of the MO transistors.
It is desirable that the increase in the delay time when all the S transistors are added be as close as possible to the delay time per inverter stage for the sake of simplicity of delay time adjustment.

A specific method for determining the structure of the reference pulse generating circuit 96 will be described below.

The pulse generation circuit 9 is designed so that the fall of the output NOD1 of the delay circuit 25 does not fall on the rise of the input clock of the next cycle (FIG. 6), and the width of the output pulse A-PULSE from the node NOD2 is determined. To do. If the output pulse of the node NOD1 falls at the input clock of the next cycle, the width of the output pulse A-PULSE from the node NOD2 of the next cycle becomes short. Inverter train 2 in pulse generator 9
The number of stages of 8 is obtained by dividing the Low time tL (FIG. 5) of the clock CLK3 by the delay time per stage of the inverter array 28.
The quotient is taken as the total number of stages of the NOR gate NOR2 and the logic gates of the inverter array 28 (only odd-numbered stages are selected), and the number of transistors to be added as the delay time adjusting MOS transistor groups 26 and 27 is adjusted by the remaining delay time. Further, the above determination is corrected by taking into consideration the input capacitances of the NOR gates NOR1 and NOR2.

At this time, in order to suppress the rounding of the waveform as much as possible, after adding the gate capacitance for one NMOS and PMOS, if it is necessary to add more, the second NMO is added.
S and PMOS are added. For example, the delay circuit 25 of FIG.
As an example, first, a gate capacitor for one NMOS and one PMOS is added to the fourth stage inverter of the inverter array 28, and if further addition is required, the third stage, second stage, 1st stage,
If the gate capacitance for one NMOS and one PMOS is added to the stage, and if further addition is required, the second NMOS and PMOS are added to the fourth stage, then the third and second stages, The second NMOS and PMOS are added to the first stage.
At this time, there is no limitation on the selection order of the inverters to which the gate capacitance is added.

The pulse expansion circuit 10 is designed to expand the width of the pulse generated by the pulse generation circuit 9 to a desired pulse width. At this time, the expansion width per pulse in the pulse expansion circuit train 29 is designed so as not to exceed the pulse width generated by the pulse generation circuit 9. That is, the delay circuit 60A, the NAND gate NAND2, and the delay circuit 7
0A, the sum of the delay times of the NAND gate NAND3 and the delay circuit 80A must not exceed the width of the pulse A-PULSE generated from the pulse generation circuit 9. Based on this result, the specific method of determining the number of stages will be described below. Specifically, a value obtained by subtracting the width of the pulse A-PULSE generated by the pulse generation circuit 9 from the desired pulse width is divided by the delay time per one stage of the inverter trains 36 to 38, and the quotient is divided by the inverter. And the total number of NAND gate stages (only even stages are selected). After that, based on the above result, the number of stages of the partial pulse expansion circuit is determined so that the number of stages in one pulse expansion circuit train is substantially equal. This is so that the expansion width per pulse expansion circuit array can have a margin substantially the same as the pulse width generated from the pulse generation circuit 9.

Further, the delay time which cannot be compensated by the NAND and the inverter alone is used as the delay time adjusting MO.
This is compensated by adding S transistor groups 30 to 34. After this,
The number of delay time adjusting MOS transistors is corrected in the same manner as in the pulse generating circuit 9. At this time, in order to suppress the rounding of the waveform as much as possible, after adding the gate capacitance for one NMOS and PMOS, if it is necessary to add more, the second NMOS and PMOS are added in the case of the pulse generation circuit 9. Is the same as. For example, first, a gate capacitor for one NMOS and one PMOS is added to the inverter of the third stage of 38, and if further addition is required, the second stage and the first stage, and further, the third stage and the second stage of 37, The first stage, and then the 36th 4, 3, 2 and 1st stage inverters have NMOS
If the gate capacitance for one and one PMOS is added, and further addition is required, the second NMO is added in the order described above.
S and PMOS are added to the inverters 36-38. At this time, there is no limitation on the selection order of the inverters to which the gate capacitance is added.

More specifically, the transistors belonging to the delay circuit 25 in the pulse generation circuit 9 and the inverter INV2 and the NAND gate NA in the pulse expansion circuit 10 are included.
The gate length of the transistors other than ND1 is 0.60 μm, and the NOR gate NOR1 in the pulse generation circuit 9 and the inverters INV2 and NAN in the pulse expansion circuit 10 are provided.
The gate length of the transistor belonging to the D gate NAND1 is set to 0.45 μm of the transistor forming another logic circuit of this semiconductor integrated circuit. However, the PMOS transistor and the NMO which form the inverter INV1
The channel width of the S transistor is set to 10 μm and 6 μm (hereinafter, PMOSs that form the same logic gate in this way)
Channel width of transistor and NMOS transistor is 1
0 μm / 6 μm), NOR gate NOR1 32 μm / 9 μm, NOR gate NOR2 20 μ
m / 6 μm, 40 μm / 22 μ for inverter INV2
m, NAND gate NAND1 is 90 μm / 45 μ
m, 3 μm for NAND gates NAND2 and NAND3
/ 3 μm, 34 μm / 19 μm for inverter INV3
The inverters in the delay circuit 25 and the inverters other than the inverters INV2 and INV3 in the pulse expansion circuit 10 were set to 3 μm / 3 μm.

At this time, in the pulse generation circuit 9, the clock low time tL = 1.3 ns, the delay circuit 25
Since the delay time per stage in the inverter of 3 μm / 3 μm is 0.198 ns, 1.3 / 0.198 = 6.
57, and the number of inverters in the delay circuit 25 is four. Further, NOR2, the inverter 4 of the delay circuit 25
It cannot be compensated by steps (6.57-5) x 0.198 = 0.31
ns is a delay time adjusting MOS transistor 26, 27
Supplement with. Since the increase of the delay time when one delay time adjusting MOS transistor is added is 0.030 ns, 10 or 11 delay time adjusting MOS transistors are added from 0.31 / 0.030 = 10.33. There is a need to. After that, detailed evaluation revealed that eight delay time adjusting MOS transistors were required. The eight delay time adjusting MOS transistors are distributed as shown in FIG. 2 in consideration of the rounding of the waveform. Further, in the pulse expansion circuit 10, the pulse width generated by the pulse generation circuit 9 is 1.3 ns, and the desired pulse width is 4.0 n.
s, the delay time per stage in the inverters 3 μm / 3 μm of the delay circuits 36 to 38 is 0.198 ns,
(4.0-1.3) /0.198=13.64,
When evenly distributed, it is desirable that the number of pulse expansion circuit trains be three and that the number of logic stages per line be four. This is because if the number of logic stages per column is increased further, the expansion width per column becomes longer than the pulse width generated in the pulse generation circuit 9, and if the number of logic stages per column is further decreased, This is because the number of NANDs increases and the fan-out of INV2 increases, which leads to signal rounding and delay. The above-mentioned three pulse expansion circuit trains cannot be supplemented (1
3.66-12) × 0.198 = 0.32 ns is compensated by the delay time adjusting MOS transistors 30 to 35. The increase in delay time when one delay time adjusting MOS transistor is added is 0.030 ns, so 0.32 /
From 0.030 = 10.7, it is necessary to add 10 or 11 delay time adjusting MOS transistors. After this, by detailed evaluation, 6 delay time adjustment MOSs
I needed a transistor. Compared to the pulse generation circuit 9 described above, the difference between the predicted number of delay time adjustment MOS transistors and the number after detailed evaluation is large.
The gate capacitance of 1 (90 μm / 45 μm) is NOR1 (3
This is because the gate capacitance is larger than 2 μm / 9 μm), the delay becomes large, and the load on the delay time adjusting MOS transistor is reduced accordingly. The six delay time adjusting MOS transistors are distributed as shown in FIG. 2 in consideration of the rounding of the waveform.

When the pulse generation circuit 9 and the expansion circuit 10 whose number of stages is determined as described above are used, the power supply voltage is 2.9.
V, ambient temperature 110 ° C, gate length ± 0.07 μm,
Even if the oxide film thickness varies by ± 0.4 nm, the variation in the width of the reference pulse B-PULSE can be suppressed to approximately ± 23%.

On the other hand, for comparison, shown in FIGS.
The gate lengths of all the transistors in the pulse generation circuit 9 and the pulse expansion circuit are the same as before, 0.45 μm, and the other conditions are as described above, and the same pulse width is used when there is no variation in the gate length and the oxide film thickness. When the basic pulse is generated, the gate length is ± 0.07 μm and the oxide film thickness is ±
When the variation is 0.4 nm, the generated pulse width varies about ± 30%.

Therefore, in the pulse generation circuit 9 and the expansion circuit 10 whose number of stages is determined as described above, the maximum width of the word line pulse is (4.0 × 1.23) /
(4 × 1.3) × 100 = 95%, and the operating frequency can be improved by 5%. Further, the minimum width of the word line pulse is (4.0 × 0.77) / (4.0 × 0.7) × compared to the conventional case.
Since 100 = 110%, the margin can be improved by 10%. The pulse width of the precharge signal is 7.5 ns (operating frequency 133 Mhz) in the cycle time (time from the rising of the clock to the rising of the next clock).
Then, compared with the conventional one, (7.5-4.0 × 1.23)
/(7.5-4.0×1.3)=112%, and the margin can be improved by 12%.

As a result, in the present embodiment, even if the gate length or the like varies in the LSI manufacturing process, variations in pulse width are suppressed without causing problems such as timing deviation among a plurality of drive pulses. , The operating frequency can be improved. Further, it is possible to increase the margin for writing data to the memory cell. Further, the present embodiment can be implemented only by changing the gate length, and there is no increase in cost such as an increase in the number of masks.

[0065]

According to the present invention, when the semiconductor integrated circuit is manufactured, even if the gate length of the MIS transistor included therein varies, the variation in the pulse width of the pulse to be generated can be reduced.

Further, in a semiconductor integrated circuit having a plurality of drive circuits for generating a plurality of drive pulses to be applied to the same controlled object from each other in a fixed order from this pulse, in the manufacturing of the semiconductor integrated circuit, a transistor is used. The required pulse length of these drive pulses can be assured even if the delay time of V fluctuates. In particular, the required pulse width of these drive pulses can be guaranteed when one of these drive pulses is a drive pulse applied after the other drive pulse has ended.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of a synchronous static SRAM formed on a semiconductor integrated circuit according to the present invention.

FIG. 2 is a schematic circuit diagram of a pulse generation circuit used in the circuit of FIG.

FIG. 3 is a schematic circuit diagram of a pulse expansion circuit used in the circuit of FIG.

FIG. 4 is a schematic circuit diagram of an address pulse conversion circuit used in the circuit of FIG.

5 is a time chart of some pulses generated by the circuit of FIG.

FIG. 6 is a time chart of some pulses generated by the pulse generation circuit of FIG.

7 is a time chart of some pulses generated by the pulse expansion circuit of FIG.

FIG. 8 is a graph showing gate length dependency of delay time per inverter.

FIG. 9 is a graph showing gate length dependence of delay time variation per inverter.

FIG. 10 is an operation waveform diagram of an inverter array with a delay circuit adjusting MOS transistor.

[Explanation of symbols]

1 ... Synchronous static RAM, 2A to 2F ... Input buffer, 3 ... Output buffer, 21 ... Output register, 22
… Input data register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoji Nishio 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Incorporated company, Hitachi, Ltd. Semiconductor Division (72) Inventor Atsushi Hiraishi Gojomizumoto-cho, Kodaira-shi, Tokyo Hitachi Co., Ltd., Semiconductor Company, Ltd., 20-1 (72) Inventor, Hiroshi Toyoshima 5-2-1, Kamisuihonmachi, Kodaira-shi, Tokyo (20) Invention, Hiritsu Cho-LS Engineering Co., Ltd. Kunihiro Komiyaji 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (9)

[Claims] 1. A semiconductor integrated circuit, comprising: a pulse generation circuit composed of a plurality of MIS transistors for generating a pulse having a predetermined pulse width from an input pulse; and driving by the generated pulse. A circuit composed of a plurality of MIS transistors, and among the plurality of MIS transistors forming the pulse generation circuit, a variation in gate length during manufacturing of the semiconductor integrated circuit causes a pulse width of the generated pulse. In the semiconductor integrated circuit, the gate lengths of the plurality of specific MIS transistors that cause the fluctuations are larger than the gate lengths of the other plurality of MIS transistors in the semiconductor integrated circuit. 2. The pulse generation circuit comprises a delay circuit for delaying the input pulse by a predetermined time, and a pulse depending on the delay time of the delay circuit from the input pulse and the input pulse delayed by the delay circuit. 2. The semiconductor integrated circuit according to claim 1, further comprising a logic circuit that generates a pulse having a width, wherein the specific plurality of MIS transistors includes a plurality of MIS transistors that form the delay circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the logic gate is a logic circuit that generates a pulse having a pulse width substantially equal to the delay time from the input pulse. 4. The semiconductor integrated circuit according to claim 2, wherein the logic gate is a logic circuit that generates a pulse obtained by extending the pulse width of the input pulse by a pulse width substantially equal to the delay time from the input pulse. . 5. The delay circuit is connected to a plurality of inverters connected in series, at least a part of the plurality of inverters, one of a power supply potential and a ground potential of the semiconductor integrated circuit, and a plurality of the plurality of inverters. The capacity for increasing the delay time of the plurality of inverters, which is added between the input terminals of each of the at least some of the inverters, and the capacity of the plurality of inverters. Semiconductor integrated circuit. 6. A semiconductor integrated circuit comprising a plurality of MIS transistors which generate a reference pulse having a predetermined pulse width from a clock signal and having a predetermined relative time difference with respect to the clock signal. A reference pulse generation circuit, a controlled circuit, and a plurality of control circuits respectively for generating one of a plurality of drive pulses to be applied to the controlled circuit in a predetermined order in response to the reference pulse. A plurality of drive circuits each including a MIS transistor, and the plurality of drive pulses include a first drive pulse that should have a pulse width equal to or larger than a predetermined pulse width, and a time point when the first drive pulse ends. A plurality of MIS transistors that include a second drive pulse and have a pulse width greater than or equal to a predetermined pulse width that is to be applied in the pulse generation circuit. Of the plurality of MIS transistors in the semiconductor integrated circuit, the gate lengths of a plurality of specific MIS transistors that vary the pulse width of the reference pulse when the gate length varies during manufacturing of the semiconductor integrated circuit Integrated circuit larger than the gate length of. 7. A semiconductor integrated circuit, comprising a plurality of MIS transistors for generating a reference pulse having a predetermined pulse width from a clock signal and having a predetermined relative time difference with respect to the clock signal. A reference pulse generating circuit, a clock signal generating circuit including a plurality of MIS transistors for generating another clock signal having the time difference between the clock signal and the reference pulse in response to the clock signal, and a controlled circuit, A signal supply circuit including a plurality of MIS transistors for receiving and outputting an access signal for accessing the controlled circuit in response to the other clock signal, the reference pulse and the signal supply In response to the access signal provided by the circuit, the access signal is transmitted during the period when the reference pulse is effective. For generating a control pulse, and for generating one of a plurality of drive pulses to be applied to the controlled circuit in response to the control pulse, respectively. Of the plurality of MIS transistors each including a plurality of MIS transistors, and the plurality of MIS transistors forming the pulse generation circuit, the reference pulse pulse when the gate length varies during manufacturing of the semiconductor integrated circuit. A semiconductor integrated circuit in which gate lengths of a plurality of specific MIS transistors whose widths are varied are larger than gate lengths of other MIS transistors in the semiconductor integrated circuit. 8. The controlled circuit is a memory cell array, the access signal is an address signal for accessing the memory cell array, and the plurality of drive pulses are a word line drive pulse and a precharge. The semiconductor integrated circuit according to claim 7, further comprising an activation signal. 9. The gate length of the specific plurality of MIS transistors in the reference pulse generation circuit is 1.3 times or more the gate length of the other plurality of MIS transistors in the semiconductor integrated circuit. It is 8 times or less.
The semiconductor integrated circuit according to any one of 1.