JPH09326494A - Semiconductor circuit and formation thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the process by reforming at least a part of wiring into an anode oxide through an anodic oxidation process thereby insulating and breaking the wiring electrically through single anodic oxidation. SOLUTION: An anodic oxidation AO wire 201 is constricted partially to form a thin wire part 202. When anodic oxidation is started under that state, an oxide is deposited gradually on the surface touching a catalytic solution and the AO wire 201 becomes thinner as the thickness of the oxide increases. When the anodic oxidation is continued, the AO wire is entirely subjected to anodic oxidation at the thin wire part 202. More specifically, the thin wire part 202 is insulated to lose the electric conductivity and it is broken electrically. According to the method, the AO wire is broken automatically at the time of anodic oxidation without requiring any breaking process by simply making thin a part of the AO wire at the time of patterning a first wiring.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor circuit including a semiconductor device using a thin film semiconductor having crystallinity and a method for forming the semiconductor circuit.
As a typical semiconductor device, a thin film transistor (T
FT).

[0002]

2. Description of the Related Art In the process of forming a semiconductor circuit, a wiring dividing step may be required. For example,
The invention described in the 5-224432 publication corresponds to this. As described in this publication, the thin film transistor L
When the width of the buffer region such as the DD region or the offset region (determined by the thickness of the anodic oxide film) is made different depending on the purpose, a part of the wiring must be divided during the anodic oxidation process. . That is, it has been necessary to devise such as adjusting the width of the buffer region by preventing the wiring after the dividing portion from being further anodized (the thickness of the anodic oxide film does not increase).

As a wiring dividing technique in the case where the above dividing step is required, a means for exposing only a divided portion by patterning and removing it by a dry or wet etching method is generally used. In addition, as another example, an example in which a laser beam is used for division has been reported.

The division by laser light has an advantage that the step is simplified as compared with the former dividing step by patterning and etching, but it is still necessary to temporarily interrupt the anodizing step for the dividing step. .

In addition to the above reasons, a wiring dividing process may be required. For example, in a semiconductor circuit or the like having a multilayer wiring structure, a process of always keeping the wirings of the respective layers short-circuited and dividing them all together when the semiconductor circuit is completed is used as a means for preventing electrostatic breakdown. .

However, the above-mentioned means has a demerit such that the patterning step is additionally increased only for the dividing step, and is not preferable in consideration of mass productivity. Also,
For example, when a hole is formed in the interlayer insulating film and a part of the wiring below it is divided, overetching after dividing the wiring forms a hollow under the interlayer insulating film, and the chemical solution or etching gas remains there. There is also a problem. Further, the wiring thus etched may have an exposed exposed surface, which is not preferable in terms of pollution control.

[0007]

SUMMARY OF THE INVENTION The invention disclosed in the present specification provides a technique for simplifying a method for forming a semiconductor circuit by intentionally dividing wiring by utilizing an anodic oxidation process. Is an issue.

[0008]

The structure of the invention disclosed in the present specification comprises a step of forming a wiring made of an anodizable material on an insulating substrate, and a step of anodizing the wiring. And at least a part of the wiring is transformed into anodic oxide to be insulated by the anodizing step, and the wiring is electrically divided.

That is, utilizing the fact that conductive wiring is transformed into insulating anodic oxidation by performing an anodic oxidation process, a portion of the wiring is completely anodized and the electrical connection of that portion is cut off. The purpose is to do.

Further, the structure of another invention includes at least a step of forming a wiring made of an anodizable material on an insulating substrate, and a step of anodizing the wiring, wherein the wiring is at least There is a region where the wiring width is locally narrowed, and the region is selectively transformed into anodic oxide by the anodizing step to insulate and electrically disconnect the wiring. Characterize.

According to another aspect of the invention, in forming a semiconductor circuit composed of at least two kinds of thin film transistors in which the widths of the LDD regions or the offset regions are different, the gate line of the thin film transistor is made of an anodizable material. The method further includes at least a step of forming a gate electrode extending from the gate line and a wiring to be an anodized line, and a step of anodizing the wiring, and at least a part of the wiring is formed in the middle of the anodizing step. It is characterized in that the wiring is electrically divided by selectively converting it into anodic oxide to electrically divide the wiring, and in at least one kind of the thin film transistors, the formation of anodic oxide is interrupted at the time of the division. .

The outline of the invention having the above structure will be described with reference to FIGS. FIG. 1 schematically shows an active matrix circuit and a peripheral drive circuit arranged in an active matrix type display device. In the figure, the solid line is the first wiring that constitutes the gate line (gate electrode) and the like, and the dotted line is the wiring that should be constructed when the semiconductor circuit is completed and T
The FT is shown.

In FIG. 1, in the active matrix circuit, the gate lines 101 and the data lines 102 are arranged in a grid pattern, and pixel TFTs 103 are formed at the intersections thereof. Switching of the pixel TFT 103 is performed by the gate line 1
Performed by a gate electrode extending from 01.

In the peripheral driving circuit, the pixel TFT
A circuit TFT 104 for driving 103 is arranged. Although shown in a simplified manner in FIG. 1, the peripheral drive circuit is usually configured by using a logic circuit such as a CMOS circuit in which an N-channel TFT and a P-channel TFT are complementarily combined. In this specification, the TFTs arranged in the peripheral drive circuit are generically called circuit TFTs.

The gate electrodes of the plurality of pixel TFTs 103 arranged in the active matrix circuit are all connected by a gate line 101 for each row. The plurality of gate lines 101 are all anodized lines (AO lines) 105.
Is connected to Here, the AO line 105 is a connection line that functions as a current supply line for anodizing wiring such as a gate electrode and a gate line.

Similarly, all the gate electrodes of the circuit TFT are also connected via the AO line 105, and all the gate electrodes on the substrate are connected via the AO line 105. Of course, the gate electrode, gate line 101, AO line 1
05 are all formed from the same wiring (first wiring). The terminal indicated by 106 is the starting point of the AO line 105 and is an external terminal that supplies a current from the outside.

With such a structure, by supplying a current to the AO line 105, all the first wirings are anodized at the same time. Therefore, for example, the pixel TFT and the circuit T
When it is desired to make the width of the LDD region different from that of FT, it is necessary to divide the wiring in the region indicated by 107.

The present invention is characterized in that the dividing step is performed at the same time during the anodizing step. That is, the same effect can be obtained as if the AO line 105 is completely insulated as an anodic oxide in the region indicated by 107 and electrically divided.

In FIG. 2A, 201 indicates the shape of the AO line 105 in the region of the dividing portion 107 of FIG. As shown in FIG. 2 (A), a part of the AO line 201 has a thin and narrowed shape. Hereinafter, the area indicated by 202 is called a thin line portion.

When anodic oxidation is started in this state, oxide is gradually formed from the surface in contact with the electrolytic solution, and at the same time, the line width of the AO line 201 becomes thinner as the oxide film thickness becomes thicker ( Figure 2 (B))

Then, if the anodic oxidation is continued, finally all the AO wires in the thin wire portion 202 are anodized. That is, the thin wire portion 202 is insulated and loses electrical conductivity, and the AO wire 201 is electrically divided.

However, when the present invention is implemented with the circuit configuration as shown in FIG. 1, since the current is supplied from the external terminal 106, the current supply to the peripheral drive circuit side is cut off after the division, and the active matrix circuit is cut off. Only the side gate electrode is selectively anodized.

As described above, if the present invention is utilized, no particular dividing step is required, and only a part of the AO line is finely processed when patterning the first wiring, and the anodic oxidation is automatically performed. It is possible to divide it into two parts.

According to another aspect of the invention, a step of forming anodizable wiring on an insulating substrate, a step of forming an insulating film on the wiring, and at least a part of the insulating film. Forming a hole in the exposed portion of the wiring, and at least a step of selectively anodizing the exposed portion of the wiring, the exposed portion of the wiring by the anodizing step Is selectively converted into an anodic oxide to be insulated, and the wiring is electrically divided.

According to another aspect of the invention, in a semiconductor circuit including a semiconductor device having an anodizable wiring, at least a part of the wiring is transformed into anodic oxide for insulation, and The wiring is electrically divided at the boundary.

In the above-described invention, the wiring is divided in the state where the entire surface of the wiring is exposed like the first wiring. However, in some cases, it is necessary to divide only a part of the wiring under the interlayer insulating film. There is also a possibility. Even in such a case, the present invention enables the division by anodic oxidation without any problem.

The present invention having the above structure will be described in detail with reference to the embodiments described below.

[0028]

【Example】

[First Embodiment] A pixel TFT forming an active matrix circuit and a CMOS forming a peripheral driving circuit according to the present invention
A process of forming a circuit (circuit TFT) will be described with reference to FIG. It should be noted that the present embodiment shows an example, and the numerical values and the like described in the text are not limited to this.

In addition, this embodiment has a circuit configuration as shown in FIG.
A circuit T that requires a high-speed operation by providing a D region
FT (TFT that becomes N-channel type TFT of CMOS circuit
(Only), an example in which an LDD region of 0.5 μm is provided is shown.

In FIG. 3, a silicon oxide film is formed as a base film 302 on a glass substrate 301 to a thickness of 2000 Å. Of course, a quartz substrate or a silicon wafer can be used instead of the glass substrate. In addition, the base film 302
May be an insulating film such as a silicon nitride film.

Next, an unillustrated amorphous silicon film (amorphous silicon film) is formed to a thickness of 500 Å and crystallized to obtain a not-shown crystalline silicon film. As the crystallization means, known heat treatment or laser annealing treatment may be used alone or in combination. In addition, a metal element that promotes crystallization may be introduced.

Then, the crystalline silicon film is patterned to form island-shaped semiconductor layers 303 to 305 which form an active layer of a thin film transistor. Island-like semiconductor layers 303, 30
Numeral 4 is an active layer of N-channel type TFTs and P-channel type TFTs which later constitute a CMOS circuit respectively, and 305 is an active layer of pixel TFTs which later constitute an active matrix circuit.

After forming the active layers 303 to 305, a silicon oxide film having a thickness of 1000 Å is formed as a gate insulating film 306. As another insulating film, a silicon nitride film or a silicon oxynitride film
(For example, represented by SiO _x N _y ) can be used.

Next, a material containing aluminum as a main component is formed into a film having a thickness of 2500 Å as the first wiring (not shown). In this embodiment, an aluminum film containing 0.2 wt% scandium is used. Scandium has the effect of suppressing the formation of protrusions such as hillocks and whiskers on the surface of the aluminum film.

The first wiring is made of a material that can be anodized. Preferred materials include simple metals such as aluminum, tantalum, titanium, tungsten, molybdenum, and silicon, semiconductors, or alloys thereof, and non-oxidized metal compounds such as tantalum nitride, titanium nitride, tungsten silicide, and molybdenum silicide. Can be mentioned.

Next, as shown in FIG. 3A, an aluminum film (not shown) is patterned to form patterns 307 to 309, which will be the prototypes of gate electrodes (and gate lines) later.
An anodized line (AO line) 310 is formed.

Although FIG. 3 (A) shows that there is one AO line connecting the peripheral drive circuit and the active matrix circuit, it is actually provided for stable current supply. The peripheral drive circuit and the active matrix circuit are connected by a plurality of AO lines.

In this embodiment, only a part of the AO line 310 (only the thin line portion 202 in FIG. 2) is described. At this time, it is important that the lateral width of the AO line 310 is less than twice the width (0.5 μm × 2 = 1.0 μm) of the width of the LDD region formed in the N-channel TFT which later constitutes the CMOS circuit. is there. This is a necessary condition for the next anodic oxidation process.

When the state shown in FIG. 3A is obtained in this way, anodization is performed in this state to form a porous anodic oxide. The conditions of anodic oxidation are as follows: an aqueous solution of 3% oxalic acid is used as an electrolytic solution, platinum is used as a cathode, and a substrate is used as an anode.

This anodic oxidation process is performed by leaving the resist mask used for patterning on the upper surfaces of the aluminum film patterns 307 to 310. Therefore, patterns 307-
Since the upper surface of 310 is not in contact with the electrolytic solution, anodic oxide is formed in the direction parallel to the substrate. (Fig. 3
(B))

In the state shown in FIG. 3B, the film thickness of the porous anodic oxides 311 and 312 formed on the side surfaces of the patterns 307 and 308 serving as the prototypes of the gate electrodes of the CMOS circuit reaches 0.5 μm. It is in a state.

At this time, the anodic oxide 313 on the pixel TFT side
The film thickness is 0.5 μm. Further, the AO wire 310 is anodized from both side surfaces, and in the state of FIG. 3B, the entire wiring is just a porous anodic oxide 314. This is the reason why the wiring width of the AO line 310 is set to 1.0 μm.

That is, when the state shown in FIG. 3B is obtained, the AO line 310 connecting the pixel TFT and the CMOS circuit is insulated and electrically divided. Therefore, no more current is supplied to the CMOS circuit, and C
The growth of the film thickness of the anodic oxides 311 and 312 on the MOS circuit side is stopped.

When the anodic oxidation is further continued, the pixel TFT
A current is continuously supplied to the anodic oxide 313 on the side, and the film thickness increases. In this embodiment, the anodic oxidation is finished when the film thickness becomes 1.0 μm. (FIG. 3 (C))

The film thickness of the anodic oxide 315 formed in this manner depends on the voltage application time (current supply time).
It is possible to easily adjust to a desired thickness by controlling. According to the research conducted by the present inventors, it has been confirmed that the porous anodic oxide film grows without a problem up to a film thickness of about 2.0 μm.

In the state shown in FIG. 3C, the CMOS
0.5 μm thick anodic oxides 311 and 312 are formed on the circuit TFTs forming the circuit, and aluminum film patterns 316 and 317 remain. Further, a 1.0 μm-thick anodic oxide 315 is formed on the pixel TFT that constitutes the active matrix circuit, and the aluminum film pattern 3 is formed.
18 remains.

Next, in the state shown in FIG. 3C, P (phosphorus) ions, which are impurities imparting N-type conductivity, are implanted into the active layers 303 to 305, and high concentration impurity regions 319 to 3 are formed.
24 are formed.

High concentration impurity regions 319 to 324
After the formation of the porous anodic oxides 311, 31
2, 315 are removed. This removal process uses acetic acid, nitric acid,
It is possible to selectively remove only the anodic oxide by using a chromium mixed acid containing chromium with respect to a mixed acid mixed with phosphoric acid. At this time, the AO wire 314 transformed into the porous anodic oxide is simultaneously removed, and the AO wire is completely divided. After that, the resist mask (not shown) left on the pattern of the aluminum film is removed by a dedicated stripping solution.

Further, known plasma oxidation is performed in this state, and the remaining aluminum film patterns 316 to 31 are formed.
A thin aluminum oxide 325-327 is formed on the surface of No. 8. If the temperature of the heat treatment is suppressed to around 300 ° C. in the subsequent step, it is possible to sufficiently suppress the generation of hillocks with these oxides. (FIG. 3 (D))

Next, as shown in FIG. 4A, P ion implantation is performed again at a lower dose than that of the previous ion implantation. By this ion implantation, anodic oxides 311, 31
Below the regions where the two 315 exist, the low concentration impurity regions 325 to 330 containing P ions at a lower concentration than the regions indicated by 319 to 324 are formed.

In this state, the source region 319 and the drain region 3 are formed in the N channel type TFT which constitutes the CMOS circuit.
20, low-concentration impurity regions (LDD regions) 325 and 326
And the channel formation region 331 is formed. In addition, the source region 32 is formed in the N-channel TFT which becomes the pixel TFT.
3, a drain region 324, low concentration impurity regions (LDD regions) 329 and 330, and a channel formation region 332 are formed.

When the above-mentioned second P ion implantation is not performed, the regions 325 to 330 are substantially intrinsic semiconductor layers (i layers), which are generally called offset regions. Also in this case, the same effect as that of disposing the LDD region can be obtained.

Next, the resist masks 333 and 334 are set to N.
A region to be a channel type TFT is shielded, and B (boron) ions are implanted as impurities imparting P type (FIG. 4).
(B)). By this ion implantation, the high concentration impurity region 32
The conductivity types of the low-concentration impurity regions 327 and 328 are reversed from N-type to P-type.

Therefore, in the state shown in FIG.
A drain region 335, a source region 336, and a channel formation region 337 are formed in the P-channel TFT that constitutes the CMOS circuit.

When the state shown in FIG. 4B is obtained, the first
A silicon oxide film having a thickness of 3000 Å is formed as the interlayer insulating film 338 of FIG. Note that a silicon nitride film may be used instead of the silicon oxide film.

After forming the first interlayer insulating film 338, contact holes are formed, and a conductive material to be the second wiring is formed and patterned to form the source electrodes 339 to 34.
1, the drain electrodes 342 and 343 are formed. This time,
The N and P channel type TFTs forming the CMOS circuit have a structure in which the drain electrode 342 is shared.

Then, as the second interlayer insulating film 344, an organic resin film (for example, polyimide) is formed to a thickness of 2 μm. The advantages of the organic resin film are that it has excellent flatness and that it has an effect of reducing parasitic capacitance because it has a low relative dielectric constant. Of course, another insulating film such as a silicon oxide film or a silicon nitride film may be used.

Next, a contact hole is formed in the second interlayer insulating film 344 and a pixel electrode 345 made of a transparent conductive film is formed. And heat treatment at 300 ℃ for 1hr in hydrogen atmosphere.
(Hydrogenation treatment) is performed to complete the semiconductor circuit shown in FIG.

The semiconductor circuit shown in FIG. 4C manufactured according to this embodiment is an N-channel type T which constitutes a CMOS circuit.
An LDD region having a width of 0.5 μm is formed in the FT,
N-channel type TF forming an active matrix circuit
An LDD region having a thickness of 1.0 μm is formed in T.

Therefore, the peripheral drive circuit can be formed by a CMOS circuit that emphasizes high-speed operability, and the active matrix circuit can be formed by pixel TFTs that emphasize high withstand voltage. Further, the manufacturing process shown in this embodiment can form a semiconductor circuit having the above structure without particularly needing a dividing process, and the manufacturing process can be significantly simplified.

[Embodiment 2] In this embodiment, an example of forming a low concentration impurity region by a method different from that of Embodiment 1 will be described.
Example 1 describes the TFT manufacturing process and the present invention.
As described in detail above, only the points different from the first embodiment will be described in the present embodiment.

First, the steps similar to those in the first embodiment are performed, and the process shown in FIG.
The state shown in FIG. This state is exactly the same as that in FIG. That is, the pattern 31 of the aluminum film
Porous anodic oxides 311 to 31 1 are formed on the side surfaces of 6 to 318.
AO wire 31 with 3 arranged and completely transformed into anodic oxide
There are four. A resist mask (not shown) used for patterning is arranged on these patterns.

In this state, the gate insulating film 306 is etched by the known dry etching method. In this embodiment, CHF ₃ gas is used as the etching gas. Then
As shown in FIG. 5B, the exposed region of the gate insulating film 306 is removed, and the gate insulating film 501 is processed into an island shape.
˜503 are formed in a self-aligned manner.

Furthermore, porous anodic oxides 311 to 31 1
4 is removed with chromium mixed acid to obtain the state shown in FIG. In this state, part of the gate insulating films 501 to 503 (portions located directly below the porous anodic oxides 311, 312, 315) is exposed.

When the state of FIG. 5B is obtained, the first embodiment
Plasma oxidation is performed in the same manner as described above to form thin oxides 504 to 506 on the surfaces of the aluminum film patterns 316 to 318.
To form

Next, P ions are implanted as impurity ions imparting N type. Ion implantation is divided into two steps, the first time with a dose of 1.2 × 10 ¹³ / cm ² and an acceleration voltage of 90 kV, and the second time with a dose of 5.0 × 10 ¹⁴ / cm ² and an acceleration voltage of 10 kV. Since the accelerating voltage is relatively high the first time, P ions penetrate the gate insulating film and are also injected into the active layer below the gate insulating film, but the accelerating voltage is low the second time, so there is an exposed gate insulating film. The gate insulating film shields the region to be filled with P ions from reaching the active layer.

Therefore, in FIG.
The region indicated by 12 becomes a high concentration impurity region and 513
In the regions indicated by ˜518, as a result, P ions are implanted only for the first ion implantation, and regions 507 to 512 are formed.
The impurity region has a lower impurity concentration than that of.
The regions 519 and 520 will be the channel forming regions of the N-channel TFT later.

Next, as shown in FIG. 5D, resist masks 521 and 522 are provided, and B ions, which are impurity ions imparting P-type conductivity, are implanted. In this embodiment, the ion implantation conditions are a dose amount of 1.0 × 10 ¹⁴ / cm ² and an acceleration voltage of 65 kV. By this ion implantation, the regions 509, 510 and 51 are formed.
5, 516 are inverted from N-type to P-type, and the high-concentration impurity regions 523 and 524 exhibiting P-type, and the P-channel type TF later.
A region 525 to be a T channel formation region is formed.

If the manufacturing steps thereafter are the same as those in the first embodiment, a semiconductor circuit having a structure as shown in FIG. 5E can be formed. Since detailed description has already been given in the first embodiment, only the structure of the semiconductor circuit will be shown in FIG. 5E in this embodiment.

[Third Embodiment] In the first and second embodiments, the peripheral drive circuit and the active matrix circuit have different LDD regions (or offset regions). By applying the present invention, it is possible to configure a semiconductor circuit with a plurality of types of thin film transistors having different buffer region widths.

For example, in FIG. 11, the buffer region width of the pixel TFT 11 forming the active matrix circuit is 1.2.
μm. In addition, the width of the buffer area of the first circuit TFT 12 which constitutes the peripheral drive circuit is set to 1.0 μm, and the second circuit T
The buffer region width of the FT 13 is 0.5 μm.

In this case, the division of the AO line 14 is divided into 15 and 16
It will be done in the area indicated by. At that time, the width of the thin line portion of the dividing portion 15 is set to 1.0 μm in the step of forming the wiring,
The width of the thin line portion of the dividing portion 16 is set to 2.0 μm.

Then, as described in the first embodiment,
When the porous anodic oxide having a film thickness of 0.5 μm is formed on the second circuit TFT 13, the dividing portion 15 is completely insulated and electrically divided. Then, if the anodic oxidation is continued as it is, the dividing portion 16 is electrically divided when the porous anodic oxide having a film thickness of 1.0 μm is formed on the first circuit TFT 12.

When the anodic oxidation is further continued, the pixel TFT is
Since only the anodic oxide of No. 11 is supplied with the current and continues to grow, the current supply is stopped when the film thickness reaches 1.2 μm, and the anodic oxidation process is completed.

As described above, according to the present invention, by adjusting the line width of the AO line 14, it is possible to simultaneously form a plurality of thin film transistors having anodic oxides having different film thicknesses.
Further, the present invention can be easily dealt with even when a more complicated circuit configuration is required by appropriately arranging the positions of the dividing portion and the external terminal.

[Embodiment 4] In this embodiment, as an example requiring a wiring dividing step, an example different from the first to third embodiments will be described. Specifically, this is an example in which a part of the wiring arranged under the insulating film is exposed and the region is selectively insulated to disconnect the electrical connection.

The manufacturing process of the semiconductor circuit according to this embodiment will be described with reference to FIGS. Since the semiconductor circuit of this embodiment is manufactured by almost the same steps as those of the first embodiment, detailed description will be made only on the differences from the first embodiment, and FIGS.
And reference is made to the description of Example 1.

The state shown in FIG. 6A is the same as that shown in FIG. 3A, and the patterns 601 to 6 of the aluminum film (first wiring) serving as a prototype of the gate electrode, the gate line, and the AO line.
This is a state in which 04 is formed. However, in this embodiment, the thickness of the aluminum film is at most 4000 Å or less, preferably
It is less than 2500Å. This is a necessary condition for the dividing step (anodic oxidation step) performed immediately before the completion of the semiconductor circuit.

Then, an ethylene glycol solution of 3% tartaric acid is neutralized with aqueous ammonia and immersed in an electrolytic solution adjusted to PH = 6.92, and an anodization process is performed at a formation current of 5 to 6 mA and an ultimate voltage of 100V. By this anodic oxidation process, a dense anodic oxide is formed on the surfaces of the aluminum film patterns 601-604, and the state shown in FIG. 6B is obtained. Further, in FIG. 6B, the film thickness of the dense anodic oxides 604 to 607 is about 1500Å. Also, the gate electrodes 608 to 6
10 and the AO line 611 define.

Next, as shown in FIG. 6C, P ions are implanted into the active layer by a known ion implantation method or plasma doping method, and subsequently, B ions are implanted. Needless to say, although not shown, a resist mask is arranged on the element to be an N-channel TFT when implanting B ions.

By this ion implantation process, an N channel type T
A source region 612, a drain region 613, and a channel formation region 614 of the FT are formed. Further, a drain region 615, a source region 616, and a channel formation region 617 of a P-channel TFT which form a CMOS circuit, and a source region 618, a source region 619, and a channel formation region 620 of a P-channel TFT which form an active matrix circuit are formed. To be done. It should be noted that 1500 Å is provided between the channel formation region and the source / drain region in any device.
An offset region of a certain degree is arranged (not shown).

Next, as shown in FIG. 6D, a first interlayer insulating film 621, source electrodes 622 to 624 and a drain electrode 625 are formed, and a second interlayer insulating film 626 is formed thereon. To do. Then, an opening 62 is formed in the second interlayer insulating film 626.
7 and 628 are formed. The opening 627 is for electrically connecting the drain region of the pixel TFT to a pixel electrode formed later, and the opening 628 is for electrically disconnecting the AO line 611.

When the state shown in FIG. 6 (D) is obtained, the anodic oxidation step is performed again under the conditions for forming a dense anodic oxide. However, in this anodic oxidation, the ultimate voltage was 200 V.
And According to the experimental results of the present inventors, when the aluminum film is anodized, the film thickness of the dense anodic oxide is determined by the ultimate voltage, and when it is 200 V, the film thickness is about 2800Å. ing.

This is because the resistance between the electrolytic solution and the wiring gradually increases as the film thickness of the anodic oxide increases, and when the film thickness reaches a certain film thickness (eg, 2800Å) corresponding to the ultimate voltage (eg, 200 V), anodic oxidation is performed. Is no longer done.

Therefore, if the wiring to be processed (the first wiring in this embodiment) is thick, it is necessary to increase the ultimate voltage at the time of anodic oxidation accordingly. For example, a dense anodic oxide having a thickness of 4000 Å is used. To form it, a high voltage of about 300 V is applied. However, handling a higher voltage than this is extremely dangerous, so in this embodiment, at most 4000 Å or less,
It is preferable that the film thickness is 2500 Å or less.

The above conditions are experimental facts when the aluminum film was anodized, and when other anodizable materials as described in Example 1 were used, the formation of the anodic oxide was performed under different conditions. Must be taken into account as it progresses.

In this embodiment, the film thickness of the AO line 611 made of an aluminum film is about 2500 Å (actually, 15
Since about 00Å is already anodized),
The AO wire 611 becomes a completely dense anodic oxide 629 and is insulated. That is, a part of the AO line 611 is electrically separated.

After the division is completed, a pixel electrode 630 made of a transparent conductive film is formed and a hydrogenation process is performed to complete the semiconductor circuit shown in FIG. 6 (E).

The dividing step according to this embodiment is characterized in that the wiring is electrically divided, not physically divided. The advantages will be described below.

First, since the step of forming the opening 628 for the dividing step is performed simultaneously with the step of forming the opening 627 for forming the pixel electrode, the number of steps is not increased.

Further, conventionally, as shown in FIG.
A hole was formed in the interlayer insulating film 702 above 01, and the exposed wiring 701 was removed by etching. However, in this method, a cutout portion 703 is formed under the interlayer insulating film 702 due to isotropic etching, and a chemical solution or etching gas remains in this portion, which is problematic in terms of reliability. In addition, it is not desirable in consideration of contamination and the like that the cutout portion 703 has poor coverage, and thus the wiring cross section remains exposed.

On the other hand, according to this embodiment, as shown in FIG. 7B, the exposed region of the wiring 701 is selectively made into the anodic oxide 704 having an insulating property, so that the wiring 701 is electrically connected only. Divided. That is, since the cut-out portion does not occur and the wiring 701 itself is not exposed, it is possible to perform division without impairing reliability.

Example 5 According to the findings of the present inventors,
It has been found difficult to form a porous anodic oxide for a wiring covered with a dense anodic oxide. This is due to the difference in required ultimate voltage and electrolytic solution. Therefore, in Example 4, the dividing step was performed under the condition of forming a dense anodic oxide.

However, in Example 4, unless the formation of the dense anodic oxides 604 to 607 (at least the formation of the anodic oxide 607) described in FIG.
It becomes possible to perform the anodic oxidation for division shown in (D) under the condition of forming a porous anodic oxide.

When the porous anodic oxide is used, it is possible to increase the film thickness at a relatively low voltage, which is preferable from the viewpoint of the safety of the device. Further, if necessary, it can be easily removed with a mixed acid. There is an advantage such as.

Example 6 The anodic oxidation process described in Examples 1 to 5 is a liquid phase treatment in which a wiring-formed substrate (anode) and a platinum electrode (cathode) are immersed in an electrolytic solution. The outline of the apparatus is as shown in FIG.

In FIG. 9A, the constant temperature bath 901 is filled with an electrolytic solution 902. As the electrolytic solution 902, a 3% aqueous solution of oxalic acid is used to form a porous anodic oxide, and an ethylene glycol solution of 3% tartaric acid is used to form a dense anodic oxide.

Then, the substrate 903 to be treated as an anode and the platinum electrode 904 as a cathode are immersed in the electrolytic solution 902, and the connecting wires drawn from the respective terminals are connected to the potentiometer 905. The potentiometer 905 is a control device for keeping the current and voltage constant.

When the electrochemical circuit is constructed in the state as shown in FIG. 9 (A), constant current treatment is first performed on the substrate 90.
When the voltage between the electrode 3 and the platinum electrode 904 (to be precise, between the wiring on the substrate 903 and the electrolytic solution) reaches the ultimate voltage, constant voltage processing is performed while maintaining the voltage as it is. At this time, a current flows in the direction indicated by the arrow in the figure, and the wiring on the substrate is supplied with the current and anodized.

As another oxide forming method, a plasma oxidation method is known. However, the plasma oxidation method has no problem in forming an oxide near the surface of the wiring to be processed, but is not suitable for the purpose of transforming the wiring itself into an oxide as in the present invention. However, in the case where an oxide is formed on the surface of the wiring for the purpose of protecting the wiring, the same effect as the above-described anodic oxidation can be obtained. FIG. 9B shows an example of a device configuration when the plasma oxidation method is used.

In FIG. 9B, the processing chamber 9 is grounded.
A first electrode 907 and a second electrode 908 facing each other are installed in 06. The substrate 909 is held by the first electrode 907, and the first electrode 907 is grounded. Further, the second electrode 908 is connected to an AC power supply 911 via a blocking capacitor 910 and is configured to be applied with an AC voltage.

Reference numeral 912 is an inlet for the plasma excitation gas, and reference numeral 913 is an outlet for discharging the excitation gas to the outside of the processing chamber 906, which is connected to a vacuum pump (not shown). There is. It is to be noted that a so-called ECR mode plasma device can be formed by providing a magnet or the like in the present device to form a magnetic field.

In the plasma device shown in FIG. 9B,
A gas containing oxygen as a plasma excitation gas is introduced into the processing chamber 906 from an inlet 912, and an alternating voltage is applied to the second electrode 9
08 is applied. Then, a plasm 914 is generated between the first electrode 907 and the second electrode 908. Then, the wiring formed on the substrate 909 is oxidized by oxygen plasma, and an oxide containing the same substance as the wiring material in its composition is formed on the surface thereof.

As described above, the oxide formed for the purpose of protecting the wiring can be obtained not only by the liquid phase anodic oxidation method but also by the plasma oxidation method.

[Embodiment 7] The present invention is not limited to the planar type TFTs of Examples 1 to 5, but can be applied to any TFT such as an inverted staggered type, a forward staggered type and an inverted planar type TFT. is there.

For example, a completed drawing of an inverted stagger type TFT according to a known manufacturing method including an anodic oxidation method has a structure as shown in FIG. In FIG. 8, the left thin film transistor 801 and the right thin film transistor 802 are different in thickness of the anodic oxides 805 and 806 on the surfaces of the gate electrodes 803 and 804.

The inverted staggered TFT shown in FIG. 8 is different in that the gate electrodes (gate lines) 803 and 804 exist under the gate insulating film 807, but the basic structure of required wirings and electrodes is It is possible to implement the present invention without any problem, which is not so different from the planar type TFT.

[Embodiment 8] The present invention is a TFT (Thin Film).
The present invention can be applied to all electro-optical devices having a semiconductor circuit using a semiconductor device typified by a transistor or a thin film transistor. As the electro-optical device, a liquid crystal display device, an EL (electroluminescence) display device, E
A C (electrochromic) display device and the like can be mentioned.

Further, the applied products include TV cameras, personal computers, car navigations, TV projections and the like. A brief description of those applications will be given with reference to FIG.

FIG. 10A shows a TV camera, which is a main body 2
001, a camera unit 2002, a display device 2003, and operation switches 2004. The display device 2003 is used as a viewfinder.

FIG. 10B shows a personal computer, which has a main body 2101, a cover portion 2102, and a keyboard 2.
103 and a display device 2104. Display device 21
04 is used as a monitor and requires a size of 10 inches diagonally.

FIG. 10C shows a car navigation system, which includes a main body 2201, a display device 2202, and operation switches 2.
It is composed of 203 and an antenna 2204. Display device 22
The 02 is used as a monitor, but since the main purpose is to display a map, it can be said that the allowable range of resolution is relatively wide.

FIG. 10D shows a TV projection, which includes a main body 2301, a light source 2302, a display device 2303,
It is composed of mirrors 2304 and 2305 and a screen 2306. Since the image displayed on the display device 2303 is projected on the screen 2306, the display device 2303 is required to have high resolution.

As described above, the application range of the present invention is extremely wide, and the present invention can be applied to all manufactured products having semiconductor circuits.

[0115]

According to the present invention, when it is necessary to form anodic oxides having different film thicknesses on the wirings of the same layer as in Example 1, the steps of anodic oxidation-division-anodization have been performed. Can be performed by one-time anodic oxidation without increasing other steps, which greatly contributes to process simplification.

When it is necessary to divide a part of the wiring under the interlayer insulating film as in the third embodiment, the wiring is not physically divided but is exposed electrically to expose the cross section. ,
It is possible to form a highly reliable semiconductor circuit by ameliorating the problem of hollowing out of the interlayer insulating film.

As described above, the present invention can be applied to all manufactured products having semiconductor circuits, and is a very useful technique in industry.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a semiconductor circuit.

FIG. 2 is a diagram for explaining a dividing process by anodic oxidation.

FIG. 3 illustrates a manufacturing process of a thin film transistor.

FIG. 4 illustrates a manufacturing process of a thin film transistor.

5A to 5C are diagrams illustrating a manufacturing process of a thin film transistor.

6A to 6C are diagrams illustrating a manufacturing process of a thin film transistor.

FIG. 7 is a diagram for explaining a dividing process by anodic oxidation.

FIG. 8 is a diagram for explaining an anodic oxidation method and a plasma oxidation method.

FIG. 9 is a diagram showing a structure of an inverted stagger type TFT.

FIG. 10 illustrates an example of a manufactured product including a semiconductor circuit.

FIG. 11 is a diagram showing an outline of a semiconductor circuit.

[Explanation of symbols]

 101 Gate Line 102 Data Line 103 Pixel TFT 104 Circuit TFT 105 Anodic Oxidation (AO) Line 106 External Terminal 107 Dividing Section 202 Fine Line Section

Claims (7)

[Claims] 1. A method comprising: forming a wiring made of a material capable of anodizing on an insulating substrate; and a step of anodizing the wiring, wherein at least one of the wirings is formed by the anodizing step. A method for forming a semiconductor circuit, characterized in that the portion is transformed into anodic oxide to be insulated, and the wiring is electrically divided. 2. A step of forming a wiring made of a material capable of anodizing on an insulating substrate, and a step of anodizing the wiring, wherein the wiring is locally at least partially formed. A semiconductor circuit having a region having a narrow wiring width, which is selectively transformed into anodic oxide by the anodic oxidation step to insulate the region and electrically divide the wiring. Forming method. 3. When forming a semiconductor circuit composed of at least two types of thin film transistors having different widths of LDD regions or offset regions, a gate line of the thin film transistor and an extension from the gate line are made of anodizable material. At least a step of forming a wiring to be a gate electrode and an anodic oxidation line, and a step of anodizing the wiring, wherein at least a part of the wiring is selectively anodic oxide during the anodic oxidation step. A method for forming a semiconductor circuit, comprising insulating by performing transformation to electrically divide the wiring, and in at least one type of the thin film transistors, the formation of the anodic oxide is interrupted at the time of the division. 4. The semiconductor according to claim 1, wherein a 3% oxalic acid aqueous solution is used as an electrolytic solution used in the anodic oxidation step, and the anodic oxide is porous. Method of forming a circuit. 5. A step of forming an anodizable wiring on an insulating substrate, and a step of anodizing the wiring, wherein the anodizing step electrically disconnects the wiring. A method for forming a semiconductor circuit, which is characterized by the object. 6. A step of forming wiring capable of anodizing on a substrate having an insulating property, a step of forming an insulating film on the wiring, and forming an opening in at least a part of the insulating film, At least exposing the part of the wiring, and selectively anodizing the exposed part of the wiring, and selectively anodizing the exposed part of the wiring by the anodizing step. A method for forming a semiconductor circuit, characterized in that the wiring is electrically insulated by transforming into a wiring. 7. A semiconductor circuit comprising a semiconductor device having an anodizable wiring, wherein at least a part of the wiring is transformed into anodic oxide to be insulated, and the wiring is electrically connected in that region. A semiconductor circuit characterized by being divided into.