JPH09322126A - Image conversion timing detector - Google Patents

Abstract

(57) Abstract: An FV conversion timing is detected without omission or erroneous detection based on a television signal obtained by so-called FV conversion. SOLUTION: Regarding a television signal obtained by converting the number of frames of 24 frames / sec by 2-3 conversion, field delays 101 and 102 and an average value circuit 103 of absolute difference values are used for the nth field and the n-2th field. The average value of the absolute values of the differences in the brightness levels of the fields is calculated, and similarly,
-4 field and the n-6th field, the difference value shift register 1
05, the comparing unit 106, the true / false value shift register 107, and the AND circuit 108 make the average value of the difference absolute values of the nth field and the n-2th field the minimum value, and also satisfy the above condition 5 fields before. , The signal indicating that the nth field is the 2-3 conversion timing is output.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a film image, CG
The present invention relates to image processing using a television signal obtained by converting an image or the like by converting the number of frames, for example, a television signal obtained by performing a so-called 2-3 conversion or a 2-2 conversion of a film image or a CG image, The present invention relates to an image conversion timing detection device that detects the timing of 3 conversion and 2-2 conversion.

[0002]

2. Description of the Related Art In the so-called 2-3 conversion, as shown in FIG. 1, two consecutive frames of 24 frames / second image such as film are converted into five consecutive fields of a television signal of 60 fields / second. It is the conversion of the number of pieces to be converted. This conversion is performed by repeatedly allocating one frame of the 24 frame / sec image to two fields of the television signal and allocating the next frame to three fields of the television signal.

The so-called 2-2 conversion is a conversion of the number of frames for converting one frame of an image of 30 frames / second such as film into two fields of a television signal of 60 fields / second as shown in FIG. That is. This conversion is performed by allocating one frame of an image of 30 frames / sec to two fields of the television signal.

Timing detection of 2-3 conversion and 2-2 conversion means which field of the converted television signal is based on the television signal created by such 2-3 conversion and 2-2 conversion. Is to detect whether or not it corresponds to one frame of the original film or the like.

Conventionally, as a 2-3 conversion timing automatic detection device of this type, Japanese Patent Application No. 7-330 filed by the applicant of the present application has been used.
In the embodiment of the 881 patent application “image conversion device”,
There is a timing signal detection unit for 2-3 conversion.

The 2-3 conversion timing detecting section has a configuration shown in FIG. 3 in principle, and receives a luminance signal of a television signal as an input. 1 and 2 are field delays. Assuming that the luminance signal of the nth field is represented by f (n), the luminance signal f (n) of the nth field and the luminance signal f (n− of the nth field of the 3rd difference absolute value sum circuit.
The absolute value of the difference in the brightness level for each pixel in 2) is obtained, and the sum of the absolute difference values of all the pixels in one field is obtained. The sum of absolute differences and the threshold value read from the threshold value memory of 4 are set to 5
When the sum of absolute differences is smaller than the threshold value, the nth field is the last field of the three fields to which the same one piece is assigned in 2-3 conversion as shown in FIG. Detect that there is. The threshold can be set to any value.

[0007]

The sum of absolute differences varies depending on the telecine device that converts a film image into a television signal, and the sum of absolute differences varies depending on the material image even if the same telecine device is used for conversion. Therefore, the conventional 2-3 conversion timing detection device has the following problems.

For example, FIG. 5, FIG. 6, FIG. 7 and FIG. 8 are examples of the sum of absolute differences of the television signals which have been 2-3 converted. The vertical axis of the figure is the average value of the absolute difference values per pixel obtained by dividing the sum of absolute difference values by the number of pixels, and the horizontal axis is the field number of the input television signal of FIG. For example, the value at the position where the field number is 20 indicates the pixel average of the absolute difference values between the luminance signal of the 20th field and the luminance signal of the 18th field. Further, regarding the timing of 2-3 conversion of the images of FIGS. 5, 6, 7, and 8, the 5th, 10th, 15th, 20th, 25th, 30th, ... In the -3 conversion, it is the last field of the three fields to which the same one piece is assigned.

In the conventional 2-3 conversion timing detecting device, in the image shown in FIG. 5, the threshold value is 3.5 in terms of pixel average.
Otherwise, the timing of 2-3 conversion cannot be detected. However, if the threshold value is set to 3.5 or more on the pixel average, for example, in the image shown in FIG.
False detection occurs in the 23rd and 24th fields. On the contrary, in order to prevent erroneous detection and correctly perform 2-3 conversion timing detection in the image shown in FIG. 6, it is necessary to set the threshold value to about 1.2 on a pixel average, but the threshold value is on a pixel average. When 1.2, the timing of 2-3 conversion cannot be detected for the image shown in FIG. In this way, the conventional 2-3
In the conversion timing detection device, it is necessary to adjust the threshold value every time the material image is different.

Further, in the image shown in FIG. 6, if the threshold value is less than 1.0 in terms of pixel average, for example, the timing of 2-3 conversion in the 5th, 10th, 15th, 40th and 45th fields is set. Cannot be detected. When the threshold value is 1.5 or more on the pixel average, for example, 2 in the 24th field.
-3 The timing of conversion is erroneously detected. Therefore, it is necessary to adjust the threshold value between 1.0 and 1.5 on a pixel average. Thus, in order for the conventional 2-3 conversion timing detection device to correctly detect the timing of 2-3 conversion, fine adjustment of the threshold is required.

Further, in the image shown in FIG. 7, if the threshold value is set to 5.1 or more on the pixel average, 2-3 in the 98th field.
If the conversion timing is erroneously detected and the threshold value is less than 5.1 on the pixel average, 2-3 conversion timing is missed in the 30th field and the 70th field. Similarly, in the image shown in FIG. 8, when the threshold value is set to 5.9 or more in pixel average, erroneous detection occurs in the 128th, 129th, and 131st fields, and the threshold value is set to less than 5.9 in pixel average. Then, in the 120th field and the 125th field, 2-
3 Omission of detection of conversion timing occurs. As described above, in the conventional 2-3 conversion timing detection device, there are images that cannot prevent erroneous detection or omission of detection even if the threshold value is adjusted.

A long-term film image such as a movie is divided into a plurality of films. Since each film is converted into a television signal by the telecine device, a phase shift of 2-3 conversion timing may occur when changing films. In addition, editing work may be performed after converting a film image into a television signal by a telecine device, such as television program production using a film camera. In this case, edit point 2-
A phase shift of 3 conversion timing may occur. Therefore, it is necessary to constantly detect the timing of 2-3 conversion required for image conversion, but the conventional 2-3 conversion timing detection device automatically detects all the images due to the above problems. It is difficult to detect the timing of 2-3 conversion.

Therefore, an object of the present invention is to provide an image conversion timing detection device which solves the above problems.

[0014]

In order to achieve the above object, the invention according to claim 1 is an image conversion timing detecting device for detecting a conversion timing in a television signal obtained by converting the number of frames of an image signal. An average value means for obtaining an average value of absolute values of signal level differences between the current field of the television signal and at least one field before the current field;
Out of at least two average values including the temporally newest average value sequentially obtained by the average value means, the condition that the latest average value is smaller than the other average values is satisfied, and the condition is the current field. Than at least 2
And an output means for outputting a signal indicating that the current field is the conversion timing when the field is also filled.

The invention according to claim 2 is the same as claim 1.
In the average value means, a delay circuit for delaying the television signal by one frame, and an average of absolute values of differences between signal levels of television signals at the input and output of the delay circuit are averaged. A value circuit, wherein the output means holds a plurality of average values from the average value circuit, and a temporal shift among the plurality of average values in the first shift register. A comparison unit that outputs a true value when the newest average value is smaller than the other average values, and outputs a false value otherwise, and a second shift that holds a plurality of output values from the comparison unit. Register and the second
And a means for outputting the conversion timing signal when both the newest output value and the oldest output value in time among the plurality of average values in the shift register are true values.

Further, in the invention according to claim 3, in claim 1, the averaging means delays the television signal by one field, and a signal between the television signals at the input and output of the delay circuit. An average value circuit of difference absolute values for obtaining an average value of absolute values of level differences, the output means includes a first shift register for holding a plurality of average values from the average value circuit; Of the plurality of average values in one shift register, the true value is output when the latest average value in time is smaller than the other average values,
Otherwise, a comparison unit that outputs a false value, a second shift register that holds a plurality of output values from the comparison unit,
A plurality of average values in the second shift register, and a means for outputting the conversion timing signal when both the newest output value and the oldest output value in time are true values. To do.

Further, the invention according to claim 4 is the shift register according to claim 2, wherein the first shift register holds five time-sequential average values from the average value circuit, respectively. The second shift register is a shift register that holds six temporally consecutive output values from the comparison unit.

Further, the invention according to claim 5 is the shift register according to claim 3, wherein the first shift register holds two time-sequential average values from the average value circuit, respectively. The second shift register is a shift register that holds three temporally consecutive output values from the comparison unit.

[0019]

FIG. 9 is a schematic block diagram of an apparatus for detecting the timing of 2-3 conversion according to the present invention. This device uses a luminance signal of a television signal as an input signal. Hereinafter, description will be made assuming that the luminance signal of the nth field is input to the input as the current field. Assuming that the luminance signal of the nth field is represented by f (n), the field delay of 101 and 102 causes the
A luminance signal f (n-2) of two fields is created. 10
The average value circuit of the difference absolute value 3 has a luminance signal f (n) of the nth field and a luminance signal f (n− of the n-2th field.
Using 2) as an input signal, the absolute value of the difference in the brightness level for each pixel is calculated, and the average of the absolute values of the differences in all the pixels in one field is output.

The difference value shift register 105 has the n-th field and the n-th field sequentially input from the average value circuit 103.
Average value d of the absolute values of the differences between the luminance signals of the two fields
(N), average value d (n-1) of the difference absolute values of the luminance signals of the (n-1) th field and the n-3rd field, and the difference absolute value of the luminance signals of the (n-2) th field and the n-4th field Mean value d (n−2), the n−3rd field and the n−5th
The average value d (n- of the absolute differences of the luminance signals of the field
3), The average value d (n-4) of the absolute differences between the luminance signals of the n-4th field and the n-6th field is output in parallel. Then, in the difference value shift register 105, similarly, a new average value d (n + 1), ... From the average value circuit 103 is sequentially input every time one field has elapsed, and the average values are sequentially discharged from the oldest average value. shift.

In the comparing section 106, d (n) and d (n-
1), d (n-2), d (n-3), d (n-4) are compared, and true is output when d (n) is minimum, and false is output otherwise. The true / false value shift register 107 includes a true / false value s (n) of the average of absolute values of the difference between the luminance signals of the nth field and the n-2th field among the data sequentially input from the comparison unit 106, and the nth value. -5 field and n-7th
Boolean value s of the average value of the absolute difference values of the luminance signal of the field
(N-5) is output in parallel. Also in the true / false value shift register 107, the input value shifts similarly to the difference value shift register 105.

The AND circuit of 108 causes s (n) and s
When (n-5) is both true, it is detected that the nth field is the last field of the three fields to which the same one piece is assigned in the 2-3 conversion as shown in FIG. Then, the 2-3 conversion timing is detected.

Further, the 2-3 conversion timing detecting device according to the present invention can detect the timing of the 2-2 conversion with a slight modification. FIG. 10 is a schematic block diagram of an apparatus for detecting the timing of 2-2 conversion according to the present invention.
Shown in The luminance signal f (n-1) of the (n-1) th field is created by the field delay 201. The operation of each component is similar to that of FIG. An average value circuit 203 of the absolute value of the difference is the absolute value of the difference of the brightness level of each pixel with the brightness signal f (n) of the nth field and the brightness signal f (n-1) of the n-1th field as input signals. Is obtained, and the average value of the absolute difference values in all the pixels in one field is output. The difference value shift register 205 is an average value circuit 203.
Average value d (n) of the difference absolute values of the luminance signals of the n-th field and the (n-1) th field, and the average value d of the difference absolute values of the luminance signals of the (n-1) th field and the n-2 field.
Output (n-1). D (n) and d in the comparison unit of 206
(N-1) is compared, true is output when d (n) <d (n-1), and false is output otherwise. The true / false value shift register 207 is a true / false value s (n) of an average value of difference absolute values of the luminance signals of the nth field and the n−1th field,
The true / false value s (n-2) of the average value of the difference absolute values of the luminance signals of the (n-2) th field and the (n-3) th field is output.
When the s (n) and s (n-2) are both true by the AND circuit 208, the nth field is assigned the same one piece in the 2-2 conversion as shown in FIG.
The timing of the 2-2 conversion is detected by detecting the last field of the two fields.

[0024]

EXAMPLE An example of detecting the 2-3 conversion timing will be described with reference to the block diagram shown in FIG.

It is assumed that the image of the field is composed of X pixels × Y lines, and the luminance signal at the coordinates (x, y) in the nth field is represented by g (n, x, y) as shown in FIG.

Input luminance signal and field delay 10
1 and 102, the luminance signal of the nth field and the n-2th field
Create a luminance signal for the field. The average difference absolute value circuit 103 calculates the average difference absolute value shown below.

[0027]

[Equation 1]

Examples of average values of the absolute difference values thus obtained are shown in FIGS. 5, 6, 7 and 8. The vertical axis of the figure represents the average value of the absolute difference values, and the horizontal axis represents the field number of the input television signal.

In the comparing unit 106, the n-th field and the n-th field are
Average value of the absolute values of the differences between the luminance signals of the two fields, the n-th
Average value of difference absolute values of luminance signals of 1st field and n-3rd field, average value of difference absolute values of luminance signals of n-2th field and n-4th field, n-3rd field and nth-th field The average value of the difference absolute values of the luminance signals of the 5th field and the average value of the difference absolute values of the luminance signals of the n-4th field and the n-6th field are compared, and the luminance signals of the nth field and the n-2th field are compared. The true value is output in the field in which the average of the absolute difference values of is minimum. As a result, FIG.
Regarding the images shown in FIGS. 6 and 7, the fifth, tenth, and first
5, 20th, 25th, 30th, 35th, 40th, 4th
5, 50th, 55th, 60th, 65th, 70th, 7th
5, 80th, 85th, 90th, 95th, 100th, 1st
True is output in the 05th, 110th, 115th, 120th, and 125th fields, and false is output in the other fields. For the image shown in FIG. 8, the 100th, 105th,
110th, 115th, 120th, 125th, 129th,
True is output in the 130th, 135th, 140th, and 145th fields, and false is output in the other fields.

Next, 107 true / false value shift registers and 10
When the output of the comparing unit 106 determines a field in which the nth field and the n-5th field are both true by the AND circuit of FIG. 8, the 10th and 10th fields are obtained for the images shown in FIGS. 15th, 20th, 25th, 30th, 3rd
5, 40th, 45th, 50th, 55th, 60th, 6th
5, 70th, 75th, 80th, 85th, 90th, 9th
5, 100th, 105th, 110th, 115th, 12th
It becomes true in the 0th and 125th fields, and the 2-3 conversion timing can be correctly detected. The 105th, 110th, 115th, 120th, and 12th images shown in FIG.
True is output in the fifth, 130th, 135th, 140th, and 145th fields, and false is output in the other fields. The 129th field erroneously detected by the comparison unit 106 is
It is removed by the true / false value shift register 107 and the AND circuit 108, and the 2-3 conversion timing can be correctly detected.

Next, according to the block diagram shown in FIG.
2 shows an embodiment for detecting the conversion timing.

Input luminance signal and field delay 201
Thus, the luminance signal of the nth field and the luminance signal of the (n-1) th field are created. Average value circuit 20 of absolute difference
In 3, the average value of the absolute difference values shown below is calculated.

[0033]

[Equation 2]

FIG. 13 shows an example of the average value of the absolute difference values thus obtained. The vertical axis of the figure represents the average value of the absolute difference values, and the horizontal axis represents the field number of the input television signal.

The comparing unit 206 includes an n-th field and an n-th field.
Average value of the absolute difference values of the luminance signal of one field, the n-th
The average value of the difference absolute values of the luminance signals of the 1st field and the n-2th field is compared, and true is output in the field in which the average value of the difference absolute values of the nth field is the minimum. As a result, in the image shown in FIG. 13, true is output in the odd field and false is output in the even field. Next, when the output of the comparing unit obtains a field in which both the nth field and the n-2th field are true by the true / false value shift register 207 and the AND circuit 208, the 13th field is obtained for the image shown in FIG. , 15th, 17th, 19th, ... Fields are true, and the 2-2 conversion timing can be correctly detected.

In the embodiment, the case of a television signal of 60 fields / sec has been described, but it is 59.94.
It goes without saying that the present invention can be applied to the case of a field frequency near 60 fields / second such as fields / second.

The film image transmission is not limited to the case of 24 frames / second and 30 frames / second, and the FV in the general case where the field frequency of the television signal and the number of frames of the film image do not match. Of course, it can be extendedly applied to the detection of the conversion timing.

[0038]

As described above, according to the present invention,
FV conversion timing can be detected without omission or erroneous detection based on a television signal obtained by converting the number of frames of a film image or a CG image, that is, obtained by so-called FV conversion. .

The 2-3 conversion timing detection device according to the present invention does not use a threshold value, and the difference value shift register and the comparison unit continuously provide a plurality of consecutive fields, for example, a field in which the average of the absolute difference values is the smallest in the consecutive 5 fields. In order to obtain, the conventional 2-
Unlike the 3 conversion timing detection device, it is not necessary to adjust the threshold value, and the 2-3 conversion timing can be detected correctly.

Even for an image that cannot be prevented from being missed or erroneously detected by the conventional 2-3 conversion timing detection device, the 2-3 conversion timing detection device according to the present invention, for example, averages the absolute values of the difference in five consecutive fields. It is possible to correctly detect the 2-3 conversion timing by obtaining the field that minimizes the value and using the true / false value shift register and the AND circuit.

Therefore, as compared with the conventional 2-3 conversion timing detecting device, the 2-3 conversion timing detecting device according to the present invention does not need to adjust the threshold value for each image, and does not cause omission of detection or erroneous detection. The timing of 2-3 conversion can be detected.

The present invention can also be applied to a 2-2 conversion timing device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of 2-3 conversion used when converting an image of 24 frames / sec into a television signal of 60 fields / sec.

FIG. 2 is an explanatory diagram of 2-2 conversion used when converting an image of 30 frames / sec into a television signal of 60 fields / sec.

FIG. 3 is a schematic block diagram of a conventional 2-3 conversion timing detection device.

FIG. 4 is an explanatory diagram of detected 2-3 conversion timing.

FIG. 5 is a diagram showing a first example of average values of difference absolute values of 2-3 converted images.

FIG. 6 is a diagram showing a second example of average values of difference absolute values of 2-3 converted images.

FIG. 7 is a diagram showing a third example of average values of difference absolute values of 2-3 converted images.

FIG. 8 is a diagram showing a fourth example of average values of difference absolute values of 2-3 converted images.

FIG. 9 is a schematic block diagram of an apparatus for detecting 2-3 conversion timing according to the present invention.

FIG. 10 is a schematic block diagram of an apparatus for detecting 2-2 conversion timing according to the present invention.

FIG. 11 is an explanatory diagram of detected 2-2 conversion timing.

FIG. 12 is an explanatory diagram of a luminance signal for each pixel.

FIG. 13 is a diagram showing an example of an average value of difference absolute values of a 2-2 converted image.

[Explanation of symbols]

 101, 102 Field Delay 103 Average Circuit of Difference Absolute Value 105 Difference Value Shift Register 106 Comparison Unit 107 True / False Value Shift Register 108 AND Circuit

Claims (5)

[Claims] 1. An image conversion timing detecting device for detecting a conversion timing in a television signal obtained by converting the number of frames of an image signal, the present field of the television signal and at least one field from the present field. An average value means for obtaining an average value of absolute values of signal level differences from the previous field, and at least two average values including the latest temporal average value sequentially obtained by the average value means, The condition that the newest average value is smaller than the other average values is satisfied, and the condition is at least 2 from the current field.
An image conversion timing detection device, comprising: an output unit that outputs a signal indicating that the current field is the conversion timing when the field is also filled. 2. The average value means according to claim 1, wherein the average value means is a delay circuit for delaying the television signal by one frame, and an average of absolute values of signal level differences between the television signals at the input and output of the delay circuit. An average value circuit of absolute difference values for obtaining a value, wherein the output means holds a plurality of average values from the average value circuit, and a plurality of first shift registers in the first shift register. Of the average values, the average value that is newest in time is smaller than the other average values, and outputs a true value, and otherwise outputs a false value, and a plurality of comparison units. The second shift register that holds the output value, and the conversion timing signal when the latest output value and the oldest output value of the plurality of average values in the second shift register are both true values And means for outputting Image conversion timing detecting device, characterized in that. 3. The average value means according to claim 1, wherein the average value means is a delay circuit for delaying the television signal by one field, and an average of absolute values of signal level differences between the television signals at the input and output of the delay circuit. An average value circuit of absolute difference values for obtaining a value, wherein the output means holds a plurality of average values from the average value circuit, and a plurality of first shift registers in the first shift register. Of the average values, the average value that is newest in time is smaller than the other average values, and outputs a true value, and otherwise outputs a false value, and a plurality of comparison units. The second shift register that holds the output value, and the conversion timing signal when the latest output value and the oldest output value of the plurality of average values in the second shift register are both true values And means for outputting Image conversion timing detection device according to claim Rukoto. 4. The second shift register according to claim 2, wherein the first shift register is a shift register that holds five time-sequential average values from the average value circuit, respectively. An image conversion timing detection device, which is a shift register that holds six temporally consecutive output values from a comparison unit. 5. The shift register according to claim 3, wherein the first shift register is a shift register that holds two temporally consecutive average values from the average value circuit, and the second shift register is the shift register. An image conversion timing detection device, which is a shift register that holds three temporally consecutive output values from a comparison unit.