JPH09321815A - Compensation circuit for quadrature modulator in transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a transmitter and to lower a price by performing conversion to the low frequency modulation output of a frequency lower than a modulation carrier frequency by a frequency conversion part and performing a processing in a quadrature modulator distortion measurement system. SOLUTION: This compensation circuit 31 is provided in the transmitter 10 provided with a quadrature modulator 51 and compensates distortion generated inside the quadrature modulator 51. The compensation circuit 31 is composed of the frequency conversion part 11, an LPF 12, a rectifier 13 and a compensation processing part 311 (composed of a DSP.) The frequency conversion part 11 converts modulation output from the quadrature modulator 51 to the low frequency modulation output of the frequency lower than the modulation carrier frequency. The LPF 12 eliminates the high frequency area of the low frequency modulation output. The compensation processing part 311 supplies common-mode input (I input) and quadrature input (Q input) for which the distortion generated inside the quadrature modulator 51 is compensated based on output from the LPF 12 to the quadrature modulator 51. In the constitution, an amplifier and a BPF for handling a GHz band are eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitter used for wireless communication, and more particularly to time division multiple access (TDMA).
The present invention relates to a quadrature modulator compensation circuit in a transmitter suitable for application to a burst wave transmitter used in a communication system. For example, in a transmitter used in a TDMA communication system, a quadrature modulator is one of important circuit components. However, this quadrature modulator has a problem of imperfections, which distorts the transmission signal from the transmitter, causes interference to adjacent channels, and even transmits data. It causes problems such as increasing the error rate. Therefore, a quadrature modulator compensation circuit is generally indispensable.

The following are the three main types of incompleteness in the quadrature modulator. (1) Carrier Leakage (DC Offset) Carrier leak (DC offset) means that both in-phase input and quadrature input (hereinafter abbreviated as I input and Q input) to the quadrature modulator are both 0. , That the carrier leaks on the output side.
The main cause is that the local signal input to the quadrature modulator leaks to its output side. As a countermeasure, the carrier leak can be compensated to 0 by offsetting the I input and the Q input. (2) Gain Deviation Gain deviation is defined as the gain (Gi) from the in-phase input (I input) to the output end of the quadrature modulator and the gain (Gq) from the quadrature input (Q input) to the output end. Imperfections caused by different (3) Phase deviation (orthogonal deviation) The phase deviation means imperfections caused by the crossing angle of the in-phase axis (I axis) and the orthogonal axis (Q axis) deviating from 90 °.

[0003]

2. Description of the Related Art FIG. 36 is a diagram showing an example of a conventional compensation circuit applied to a quadrature modulator in a transmitter. This conventional compensation circuit is described in the publication `` M. Faulkner, T.
Mattsson, W. Yates, "Automatic adjustment of quadr
ature modulators ", IEE Electronics Letters, 31st J
anuary 1991, Vol. 27, No. 3, pp. 214-216 ”, which is constructed based on the method proposed in FIG. This is a concrete part. This is called a quadrature modulator distortion measurement system. The quadrature modulator distortion measurement system 312 and the compensation processing unit 311 form a quadrature modulator compensation circuit 31.

This quadrature modulator is shown at 51 in the figure, whose two inputs are the I and Q inputs described above, each of which is a digital-to-analog converter (DA).
C) 21 and 22 and low-pass filter (LPF) 2
3 and 24 through a DSP (Digital S
orthogonal data (I
The input and the Q input) are received, and modulation is performed by the local signal from the PLL circuit 41. This DSP also forms a compensation processing unit 311 which is the subject of the present invention.

The system from the quadrature modulator distortion measurement system 312 to the compensation processing unit 311 via the power amplifier (Power Amplifier) 71 is a system proposed by the applicant as Japanese Patent Application No. 7-229222. A power amplification distortion measurement system 313 for compensating for the distortion inherent in the power amplifier 71 itself. Its configuration is the directional coupler 72.
(Extraction of transmission output), frequency converter 81 (PLL circuit 4
3 is a local signal), a low-pass filter (LPF) 82 and an analog-digital converter (ADC) 91. These components 72,
81, 43, 82 and 91 can suppress the interference between adjacent channels caused by the distortion in the power amplifier 71.

Quadrature modulator distortion measurement system 3 according to the present subject matter
Reference numeral 12 embodies the method proposed in the above-mentioned publication, and as shown in the figure, a directional coupler 61 for extracting the quadrature modulation output from the quadrature modulator 51, and a low-level carrier leak. And a bandpass filter (BP) for removing unnecessary signals inside and outside the transmitter 10 which are easy to pick up when the gain of the amplifier 62 is high.
F), a rectifier 64 for extracting its DC level, and a compensation processing unit (D) by converting its analog output into a digital output.
SP) 311 for analog / digital input
It is composed of a converter (ADC) 65.

[0007]

In the transmitting apparatus 10 shown in FIG. 36, focusing particularly on the quadrature modulator distortion measuring system 312, there are the following two problems. (1) The use of the amplifier 62 that handles the GHz band and the bandpass filter (BPF) 63 increases the size and cost of the transmitter 10. (2) It takes a long time from setting the I input and the Q input to the quadrature modulator 51 until the input level to the analog-digital converter 65 becomes stable, and
Since the compensation value is driven to the optimum value by repeating a loop loop of the compensation processing unit 311, the quadrature modulator 51, the quadrature modulator distortion measurement system 312, 311, ..., It takes a very long time to finally obtain the optimum compensation value. Need time.

Therefore, the present invention includes at least the above-mentioned two.
Compensation circuit for the quadrature modulator 51 in the transmitter 10 capable of solving (1) of the two problems, and if necessary, simultaneously solving the problems (1) and (2). The purpose is to propose 31.

[0009]

FIG. 1 is a basic configuration diagram showing a compensation circuit for a quadrature modulator according to the present invention. In the figure, reference numeral 31 is a compensation circuit, which is a quadrature modulator 51.
This circuit is provided in the transmitting device 10 including the above and is for compensating for the distortion generated in the quadrature modulator 51.
The compensating circuit 31 includes a frequency converter 11, a low-pass filter 12, a rectifier 13 (the rectifier 64 in FIG. 1).
And a compensation processing unit 311 (which is composed of a DSP).

The frequency converter 11 converts the modulation output from the quadrature modulator 51 into a low frequency modulation output having a frequency lower than the modulation carrier frequency. The low pass filter 12 removes the high frequency region of the low frequency modulation output. The compensation processing unit 311 provides the quadrature modulator 51 with an in-phase input (I input) and a quadrature input (Q input) in which the above-described distortion generated in the quadrature modulator 51 is compensated based on the output from the low-pass filter 12. It is a thing.

Comparing the configuration of FIG. 1 with the configuration of FIG. 36 described above, in the configuration of FIG. 1, the amplifier 62 for handling the GHz band and the bandpass filter (BPF) 63 are eliminated. I understand. This is because the frequency conversion unit 11 converts the low-frequency modulation output on the order of, for example, several tens of KHz to the processing in the quadrature modulator distortion measurement system 312.

Thus, parts for the super high frequency band (62, 63)
Is eliminated, and the transmission device 10 can be downsized and reduced in price (the above problem (1) is solved). Furthermore, the first aspect of the present invention
According to the embodiment, the processing contents in the compensation processing unit 311 are devised to shorten the time until the optimum compensation value is obtained (the above problem (2) is solved). For this purpose, the compensation processing unit 311 shown in FIG. 1 is provided with a “quadrature demodulation processing function”. That is, in the above-mentioned configuration of FIG. 36, it is corrected that the optimum compensation value is driven by the iterative process in the loop loop, which is performed based on the method proposed by the above-mentioned publication, and by the orthogonal demodulation process function, Quadrature modulator 51
I tried to directly obtain the distortion caused by.

In FIG. 1, if high-speed processing is not required, the rectified output is input to the compensation processing unit 311 through the rectifier 13 that rectifies the output from the low-pass filter 12, and the quadrature modulator is used. The distortion generated in 51 may be compensated by driving it to the optimum compensation value by the above-described loop processing (the second embodiment of the present invention).

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Before describing the embodiments according to the present invention, the method proposed by the above-mentioned publication will be explained. FIG. 2 is a diagram for briefly explaining the method proposed in the publication. In this publication, the aforementioned imperfections, namely (carrier leakage (DC offset),
A method for automatically adjusting the gain deviation and the phase deviation (quadrature deviation) is discussed. This FIG. 2 is shown in FIG. 1 is shown as it is.

The imperfection compensation circuit described above is shown in this publication "Automatic Tuning of Quadrature Modulators". The Fig.
1 (FIG. 2), even if the phase deviation φ of the quadrature modulator 51 is φ = 10 ° in the compensation signal flow graph, sec φ / 2 is about 1.0038. Since the deviation is only 0.03 [dB], it can usually be omitted. If the gain deviation is to be compensated, the phase deviation ki of the I input can be fixed to 1 and only the phase deviation kq of the Q input can be changed for compensation. FIG. 36 described above.
Is an example of the configuration when this technique is applied to the transmitter of Japanese Patent Application No. 7-229222. Note that the clock, reference oscillator, etc. are omitted in FIG.

The compensation circuit 31 of the quadrature modulator shown in FIG. 36 operates as follows. This is shown in flowcharts in FIGS. 3 to 9. FIG. 3 is a flowchart of a conventional main routine. FIG. 4 is a flowchart (part 1) of the conventional carrier leak compensation value calculation. FIG. 5 is a flowchart of a conventional carrier leak compensation value calculation (part 2).

FIG. 6 is a flowchart of conventional level measurement. FIG. 7 is a flowchart of a conventional gain deviation compensation value calculation. FIG. 8 is a flowchart of a conventional phase deviation compensation value calculation. The compensation value for the distortion of the quadrature modulator 51 is obtained by the compensation processing unit 311 (DSP) in FIG. 36 according to the flowcharts shown in FIGS. 4, 5, 7
8 and 8 are examples in which the steps until reaching the optimum compensation value are fixed, the time can be shortened by changing the step width. However, it is inevitable that the number of repeated loops will increase. Incidentally, FIGS.
The parameters appearing in 7 and 8 are shown in FIG.

FIG. 9 is a signal flow graph of the compensation circuit 31. This figure is substantially equivalent to FIG. Using the compensation values i _dc , q _dc , k _q, and k obtained by the compensation processing unit (DSP) 311, the in-phase input (I input) and the quadrature input (Q input) I _in , Q _in 6 is a signal flow graph when distortion compensation is performed to obtain post-compensation modulation outputs I and Q, which are output from the quadrature modulator 51. I _dc here
Is a compensation value of carrier leak (DC offset) of in-phase input (I input), q _dc is a compensation value of carrier leak (DC offset) of quadrature input (Q input), k _q is a compensation value of gain deviation, k is a phase It is a compensation value for deviation (orthogonal deviation).

FIG. 3 is a main routine of the operation of the conventional compensating circuit 31. Step S1: carrier leak compensation value calculation routine, step S2: gain deviation compensation value calculation routine, step S3: phase deviation compensation value calculation routine. is there.

A detailed example of step S1 is shown in FIGS. A detailed example of step S2 is shown in FIG. A detailed example of step S3 is shown in FIG. Also, each of FIGS. 4, 5, 7 and 8 includes at least two "level measurement" routines, a detailed example of each of which is shown in FIG.

What is common to these FIGS. 4, 5, 7, and 8 is that there is an operation of "pushing in", and the above-described loop loop is repeated several times to reach the optimum compensation value. This gives rise to the problem that it takes a very long time. FIG. 10 shows the first basic configuration shown in FIG.
It is a figure showing an example. Note that the same reference numerals or symbols are given to the same components throughout the drawings.

As shown in FIG. 10, the frequency conversion section 11 of FIG. 1 has a local oscillator (PLL) 4 for beatdown.
3 is shared by the mixer 66. The modulated output from the quadrature modulator 51 also beats down to a low frequency like the distortion measurement signal of the amplifier (PA) 71. As a result, the conventional high-frequency amplifier 62 is replaced with the mixer 66, or the conventional high-frequency BPF 63 is replaced with a low-frequency amplifier 67 and a low-frequency low-pass filter (LPF) 12 in FIG. , And can be easily integrated, and can be miniaturized. In addition, of course, the price will be low. The low-pass filter 12 can be composed of a simple operational amplifier.

FIG. 11 is a diagram showing a second embodiment according to the present invention. In the second embodiment, as described above, the rectifier 13 (see FIG. 36 showing the conventional example) is added to the first embodiment (FIG. 10).
(Corresponding to the rectifier 64 in FIG. 26), and the compensation processing unit 311 does not include the demodulation processing function described later in the first embodiment as in the case of FIG. However, the configuration of FIG. 11 can be further modified. In this modified example, the output of the low pass filter (LPF) 12 is converted into an analog digital signal without passing through the rectifier 13.
It is input to the converter (ADC) 65, and the function of the excluded rectifier 13 is input to the compensation processing unit (DSP) 3
11 to realize further miniaturization and cost reduction. The configuration of this modification is similar to the configuration of FIG. 10 described above. In this case, the function of the excluded rectifier 13 is fulfilled by performing the digital integration operation in the DSP (311).

Comparing the first embodiment (FIG. 10) with the second embodiment (FIG. 11), the configuration according to the second embodiment of FIG. 11 achieves the necessary optimum compensation value even though the size can be reduced. It takes a long time to do the same as the conventional technology. On the other hand, in the first embodiment of FIG. 10, the distortion of the quadrature modulator 51 is directly calculated by the calculation in the compensation processing unit 311, and thus the acquisition time of the optimum compensation value is greatly shortened.

12 (A), (B) and (C),
It is a vector diagram for explaining 1st Example. (A)
Shows three vectors A, C and E input to the quadrature modulator 51 based on the first embodiment. (B)
When the three vectors A, C and E shown in (A) are input to the quadrature modulator 51, among the distortions of the quadrature modulator 51 itself, carrier leak (DC offset) causes distortion in these vectors. , Vector A ', C'and E'. Note that O ₁ is the carrier leak vector at this time.

(C) is a vector A ₁ , C corresponding to the three vectors A, C and E generated in the compensation processing unit 311 by the orthogonal demodulation function formed based on the first embodiment. ₁ and E ₁ are shown. O ₂ is the carrier leak vector at this time. The compensation processing unit 311 of the first embodiment uses the above-described quadrature demodulation function and the demodulation output obtained by the quadrature demodulation to generate an in-phase input and a quadrature input in which the distortion generated in the quadrature modulator 51 is compensated, and the quadrature input is generated. The distortion compensation function given to the modulator 51 is provided.

See FIGS. 12A, 12B and 12C.
The first embodiment of FIG. 10 will be described in more detail with reference to FIG.
You. Vectors A, C and E shown in FIG.
In addition to the quadrature modulator 51, the quadrature modulator 51 at that time
Of the modulated output of the quadrature in the compensation processing unit (DSP) 31.
Vector A orthogonally demodulated by demodulation function₁, C₁and
E₁To carrier leakage, gain deviation and phase deviation
Find each compensation value for. (1) Carrier leak (DC offset) The carrier leak vector on the input side of the quadrature modulator 51 is set to O.
₁, From the input of the quadrature modulator 51 to the inside of the compensation processing unit 311.
Let G be the complex gain up to the output of the orthogonal demodulation by the orthogonal demodulation function.
Then, G is unknown, but carrier recovery is performed as follows.
Vector O ₁Can be asked. First, A₁= (A + O₁) G, E₁= (E + O₁) G ……………… (1). Here, is E = -A from FIG. 12 (A)?
Then, if E and G are deleted from this and the above equation (1),

[0028]

[Equation 1]

And i_dc= REAL (O₁), Q_dc= IMAG (O₁) ………………………… (3) is obtained. With this, the carrier leak compensation value is obtained.
You. REAL is a real part and IMAG is an imaginary part. (2) Gain deviation Gain deviation compensation value k_qIs the vector A in FIG.
And C. Pair these vectors A and C
The observed value vector A shown in FIG. ₁and
C₁Includes carrier recovery during quadrature demodulation by the quadrature demodulation function.
Vector O _TwoIs included, so in FIG.
Indicating O_TwoO_Two= (A₁+ E₁) / 2 ……………………………………………… (4) Then, find the ratio of the I-axis gain and the Q-axis gain.
Then,

[0030]

[Equation 2]

Then, the compensation value for the gain deviation is obtained. (3) Phase deviation (orthogonal deviation) In the above-mentioned publications, the phase deviation compensation value k is φ = π / 2.
It is shown that the phase deviation angle from is k = sin (φ / 2) …………………………………………………… (6).

Here, since sin φ is that the absolute values of the denominator and the numerator are almost equal,

[0033]

(Equation 3)

Can be represented by Moreover, since φ is usually smaller than 1, it can be approximated as φ = sin φ,

[0035]

(Equation 4)

The compensation value of the phase deviation is obtained at. FIG.
The operation according to the first embodiment shown in FIG. 13 is shown by the flowcharts in FIGS. FIG. 13 is a flowchart showing the main routine (No. 1) of the first embodiment.

FIG. 14 is a flow chart (No. 2) of the main routine in the first embodiment. FIG.
FIG. 4 is a diagram showing a flowchart of vector value measurement in the first embodiment. FIG. 16 is a diagram showing a flowchart of the compensation value calculation in the first embodiment.

FIG. 17 is a diagram showing a flowchart for updating the compensation value in the first embodiment. 13 and 14
R1, R2 and R in the main routine of
FIG. 15 shows a detailed example of each of the Nos. 3 and 3, and FIGS. 16 and 17 show detailed examples of each of the routines R4 and R5 in the main routines of FIGS. 13 and 14, respectively. The execution of these routines is governed by a compensation processing unit (including quadrature demodulation processing) 311 composed of a DSP.

Represented by FIGS. 10 and 12-17.
In the first embodiment, the carrier leak, the gain deviation and the position
Since each compensation value of the phase deviation affects each other,
While updating each compensation value, gradually approach the true value (optimal compensation value).
(See FIG. 4 shown as the prior art,
Different from the above-mentioned "drive-in" in FIGS. 5, 7, and 8.
Become). However, this first embodiment is repeated several times or more.
The compensation value within the practical range is reached by repeating the
In operation, for example, the carrier leak compensation value i_dc, Q _dcSeeking
It is necessary to drive in several loops more than 10 times
Comparing to what was
It becomes possible to acquire a value.

Further, the scale of the hardware as the transmission device 10 can be smaller than that of the prior art, as in the second embodiment of FIG. Referring to FIG. 13, step S1
Then, the compensation values i _dc , q _dc , k _q, and k, the number of loops (the number of repetitions described above), and the amplitude values of the vectors A, C, and E are initially set to their respective predetermined values.

Step S2: Vector A in FIG. 12 (A)
Is set for the quadrature modulator 51 and input to it.
The routine R1 (see FIG. 15) is as follows. Step S1 ': I input and Q input to the quadrature modulator 51 are compensated using the compensation values initialized in step S1 of FIG.

Step S2 ': The I and Q inputs compensated in step S1' are input to the quadrature modulator 51,
The modulation output (I output and Q output) is obtained from this. Step S3 ′: The modulation output from step S2 ′ passes through the quadrature modulator distortion measurement system 312, and the compensation processing unit (DSP).
Since it passes through various circuit elements (61 → 67 → 12 → 65 in FIG. 11) until it reaches the input value of 311, the input value is not stable for a while. Therefore, wait until this input value stabilizes (wait). When the input value is stable,
The input value shows a sine wave.

Step S4 ': Compensation processing unit (DSP) 3
For quadrature demodulation within 11, filter operation (digital FI
R filter) is indispensable. Since this filter operation requires an input value of the same number of samples as the number of taps of the filter, the input value of the number of samples required for quadrature demodulation is input here. The tap coefficient of this filter is DS
It can be input in the initial setting for P (step S1 in FIG. 13).

Step S5 ': The vector value V is calculated by the orthogonal demodulation function in the compensation processing unit 311. Returning to FIG. 13, in step S3 of this figure, the calculated (measured) vector V is used as the vector A of FIG.
Egg with ₁ . Hereinafter, the same operation is performed for the vectors C and E, and C ₁ and E _{1 in} FIG.
Is calculated (measured).

In the routine R4 of FIG. 14 (see FIG. 16), the routines R1, R2 and R3 of FIGS.
Based on the vectors A ₁ , C ₁ and E ₁ calculated by the above equation, carrier leak compensation values i _dct , q _dct and
2 (C) vector O ₂ and gain deviation compensation value k _qt ,
The phase deviation compensation value k _t is calculated. The subscript "t" is added to the symbol representing each compensation value to indicate that it is a transient value up to the optimum compensation value.

In the routine R5 of FIG. 14 (see FIG. 17), updating is performed N times until the optimum compensation value is reached. In addition,
The carrier leak (DC offset) compensation value and the phase deviation compensation value are added (+) to the immediately preceding compensation value, and the gain deviation compensation value is multiplied (*) with the immediately preceding compensation value. And then update.
FIG. 18 is a diagram showing a configuration example in which the components are shared in the configuration of FIG. However, the sharing of these components can be applied not only to FIG. 10 (first embodiment) but also to FIG. 11 (second embodiment).

The object of this application is the first component constituting the power amplification distortion measurement system 313 for measuring the distortion peculiar to the power amplifier 71.
Component group (81, 82, 91) and the quadrature modulator 51.
Second component group (66, 67, 12, 65) forming a quadrature modulator distortion measurement system 312 for compensating for distortions caused by carrier leak, gain deviation and phase deviation
It is.

Since there is a functionally common constituent element between the first and second constituent element groups, it is possible to share these common constituent elements by paying attention to a certain fact. Then, the transmitter 10 can be further downsized and the cost can be reduced. The certain fact referred to here is the power amplification distortion measurement system 3 described above.
13 (first component group) always operates during operation of the transmitter 10, whereas the quadrature modulator distortion measurement system 312 (first component group) operates when the transmitter 10 is powered on or starts transmission. It is to operate at times other than the normal operation of the device. Therefore, a common component group that does not operate at the same time can be shared between them.

Referring specifically to FIG. 10, an analog-digital converter (ADC) 91 and a low-pass filter (LP) of the power amplification distortion measurement system 313 will be described.
F) 82 is the AD of the quadrature modulator distortion measurement system 312, respectively.
It is common to C65 and LPF 12, and can be shared. FIG. 18 shows an example of this sharing, but other than that, the mixer 66 (in the system 312) and the mixer 81 (in the system 313).
Of course, it can be shared with (inside). In FIG. 18, switch means 69 is introduced as means for realizing the above-mentioned sharing. The upper contact and the lower contact, which are schematically shown as switches, are selectively connected to the systems 312 and 313, respectively. The switching control is DSP
Performed by (311).

Next, a first improved example based on the first embodiment will be described. In the first embodiment (FIG. 10), when the device is used,
It was found that the carrier leak compensation value was not accurate enough. As a result of investigating a situation where the accuracy is low, it was found that the carrier leak value on the Q axis has a considerably larger error than the carrier leak value on the I axis. Based on this investigation result, the value of the carrier leak compensation value on the Q-axis side is calculated by using another vector to improve the accuracy of the carrier leak compensation value. It is an improved example of.

FIG. 19 is a vector diagram for explaining a first improvement example based on the first embodiment. The above-mentioned still another vector is the vectors C and F shown in this figure. By further adding these vectors C and F, the accuracy of the carrier leak compensation value is further improved. Therefore, the flowcharts of the main routine shown in FIGS. 13 and 14 are partially changed. That is, a routine for outputting the vector F and calculating the vector F ₁ is further added to the main routine. In the calculation of the compensation value, the carrier leak compensation value i
_dc and q _dc are calculated by the following equations (9) and (10).

[0052]

(Equation 5)

FIG. 20 is a diagram showing a routine added in the first improvement example based on the first embodiment. This routine is inserted in, for example, the part of the main routine in FIG. Along with this, the routine R4 (see FIG. 16) in the main routine in FIG. 14 is also changed. That is, when calculating the compensation value,
The equation (a) in 6 is replaced with the above equation (10).

After all, according to the first improved example, in the calculation of the compensation value (i _dc , q _dc ) of the carrier leak of the distortion generated in the quadrature modulator 51, the in-phase axis (I axis) is calculated. The compensation value of is obtained from the input value input to the compensation processing unit 311 when the in-phase input on the in-phase axis is output from the compensation processing unit 311. Then, the compensation value of the orthogonal axis (Q axis) is obtained from the input value input to the compensation processing unit 311 when the orthogonal input on the orthogonal axis is output from the compensation processing unit 311.

Next, a second improved example based on the first embodiment will be described. When the first embodiment (FIG. 10) is implemented as a device, the accuracy of the phase deviation compensation value may not be sufficient. The main cause is the phase noise of the PLL circuit 41 and the PLL circuit 43. Interfering noise is generated by mixers 66 and 81.
It is caused by the relative phase with respect to the frequency beat-down at, resulting in a fairly large level of noise. In the method of calculating the compensation value according to the first embodiment, the measured phase deviation depends on the phase noise as it is, and the accuracy of the compensation value is not sufficient.

FIG. 21 is a vector diagram for explaining a second improved example based on the first embodiment. Two more vectors disclosed in the aforementioned publication, namely the vector B rotated by 45 ° from the in-phase axis (I axis) and the quadrature axis (Q
And a vector D rotated by 45 ° from the (axis). The compensation value k of the phase deviation can be obtained using the following relational expression described in the publication.

[0057]

(Equation 6)

(Φ is the orthogonal angular deviation between the I and Q axes, and Er is the ratio of the amplitudes of the two 45 ° rotated vectors (= E _max / E _min ). (11) , (12) and (13), k and E
As a relational expression with r, the following expression (14) is obtained.

[0059]

(Equation 7)

According to the first embodiment, when the Er vectors V and D are output from the compensation processing unit 311 to the quadrature modulator 51, the quadrature post-obtained obtained by the demodulation processing function in the compensation processing unit 311 is obtained. Is the ratio of the absolute values of the vectors B ₁ and D ₁ of, and is expressed by the following equation (15).

[0061]

(Equation 8)

Since Er is a ratio of absolute values, it is not affected by phase noise. Therefore, the accuracy of the phase deviation compensation value can be improved. Since the above-mentioned method is adopted in the second improved example, the flowcharts of the main routine shown in FIGS. 13 and 14 are also partially modified. That is, for the main routine, vectors B and D
Is output and a routine for calculating the vectors B ₁ and D ₁ is further added. Then, the routine R4 in FIG. 14 is also modified so that the phase deviation compensation value calculation in FIG.
The expression (e) in the above is replaced with the above expressions (15) and (14).

FIG. 22 shows a routine added in the second improvement example based on the first embodiment. (A) is a vector B,
(B) is a diagram showing a vector D. These routines (A) and (B) are connected in series and are inserted into, for example, the part of the main routine in FIG. After all, under the second modified example, regarding the phase deviation of the distortion generated in the quadrature modulator 51, the value obtained by rotating the in-phase axis (I axis) by 45 ° is calculated in the calculation of the compensation value (k). The input value that is input to the compensation processing unit 311 when it is output from the compensation processing unit 311 and 4 from the orthogonal axis (Q axis).
The compensation value for the phase deviation is obtained using the input value input to the compensation processing unit 311 when the value rotated by 5 ° is output from the compensation processing unit 311.

Next, a third improved example based on the first embodiment will be described. When implemented as a device under the second embodiment using the vector (A, C, E) in FIG. 12 and the vector (F) in FIG. 19, the + side and − side of the I axis of the quadrature modulator 51 and the Q side. In some cases, the gains on the + and − sides of the axis are not the same. Then,
The carrier leak compensation values (i _dc , q _dc ) may not be accurate. In order to solve this problem, a new vector is introduced in this third modification.

FIG. 23 is a vector diagram for explaining a third improved example based on the first embodiment. The above-mentioned new vector is a vector O in which a black circle mark is added to the origin position in the figure. Thus, the origin vector O is output from the compensation processing unit 311 to the quadrature modulator 51, and the quadrature modulator 51 is output.
The vector O ₂ corresponding to the origin vector O after quadrature demodulation by the quadrature demodulation function in the compensation processing unit 311 on the output side of is calculated and used. As in the first improvement plan (FIGS. 19 and 20) described above, I-axis carrier leakage (DC
The offset value) is a vector A, and the carrier leak (DC offset value) of the Q axis is a vector C.
It can be obtained as in equations (6) and (17).

[0066]

[Equation 9]

FIG. 24 is a diagram showing a routine added in the third improvement example based on the first embodiment. This routine is a routine for outputting the vector O to calculate the vector O ₂ , and is inserted into, for example, the part of the main routine in FIG. Along with this, the routine R4 (see FIG. 16) in the main routine in FIG. 14 is also changed. That is, in the calculation of the carrier leak compensation value, the equations (a) and (a) in FIG. 16 are replaced with the equations (16) and (17), respectively, and the equation (c) is deleted.

After all, under the third modified example, in the calculation of the compensation value of the carrier leak of the distortion generated in the quadrature modulator 51, the in-phase axis (I axis) is calculated from the compensation processing unit 311. Also, when a value corresponding to the origin intersecting the orthogonal axis (Q axis) is output, the demodulation output corrected by the value input to the compensation processing unit 311 is used to obtain the compensation value.

Next, a fourth improved example based on the first embodiment will be described. When implemented as a device under the first embodiment, the quadrature modulator 51 may not have the same gain on the + and − sides of the I axis or the + and − sides of the Q axis, and the gain deviation is the I axis. And Q
It may not be compensated correctly except in the first quadrant defined by the axis. In this case, for example, with reference to the + side of the I axis, Q
The axis of the + side, the Q-axis - side, the I axis - compensating value side of the gain deviation k _qp respectively, and k _qm and k _im, determine these compensation values individually. The vector diagram used at this time is as shown in FIG. 19, and the respective coefficient values are (18), (1
It is obtained by the equations (9) and (20). The subscript p of k represents plus (positive) and m represents minus (negative).

[0070]

(Equation 10)

In carrying out this fourth improved example, FIG.
The flowchart of the main routine shown in FIG. 14 is also partially changed. That is, a routine for outputting the vector F and calculating the vector F ₁ is further added to the main routine. This routine is the first
20 is exactly the same as the routine of FIG.
For example, it is inserted in the main routine in FIG.

Accordingly, the routine R4 of FIG. 14 (see FIG.
In calculating the carrier leak compensation value in (6), k _qp , k _qm, and k _im are replaced by the above equations (18), (19), and (20) instead of equation (d) in FIG. Change to calculate. Then, these compensation values k _qp ,
When compensating the gain deviation using k _qm and k _im , the signal flow is as follows.

FIG. 25 is a signal flow graph in the case of compensating the gain deviation with the compensation value obtained by the fourth improved example according to the present invention. This corresponds to the signal flow graph of FIG. 9 already described. Depending on whether i ′ is i ′ ≧ 0 or i ′ <0, the equation of I in FIG. 9 is multiplied by 1 or by k _im . Further, depending on whether q ′ is q ′ ≧ 0 or q ′ <0, the equation of Q in FIG. 9 is multiplied by k _qp or k _qm . i ′ and q ′ are values obtained by adding phase deviation compensation to the _in- phase input (I _in ) and the quadrature input (Q _in ).

After all, under the fourth modified example, in the calculation of the compensation value for the gain deviation of the distortion generated in the quadrature modulator 51, the in-phase input is positive on the in-phase axis (I axis). Different gain deviation compensation values are set depending on whether the value is negative or negative. Also, different gain deviation compensation values are set depending on whether the quadrature input has a positive value or a negative value on the quadrature axis (Q axis).

The fourth improved example is applicable not only to the first embodiment but also to the second embodiment. Next, a fifth improved example based on the first embodiment will be described. In each of the improved examples based on the second embodiment described above, each vector takes discrete values like the vectors A, B, C, D, E and F. Therefore, the compensation processing unit (DSP) 311
There is a disadvantage in that it takes a long time from the start of outputting one vector to the stable reception of the input value to the compensation processing unit 311 corresponding to this vector. The fifth improved example is to eliminate such a long waiting time (see "weight" in step S'in FIG. 15) to shorten the time until the compensation value is calculated.

FIG. 26 is a vector diagram for explaining a fifth improved example based on the first embodiment. In the figure, A, B,
C, D, and E are the respective vectors that have the discrete values described above. In the fifth improved example, for example, a continuous vector having a point indicated by a small black circle along the periphery of the inverted heart shape shown in FIG. 26 as a vertex of each vector is adopted, and such a continuous vector is sampled. The calculated value is output from the compensation processing unit 311, and applied to the input side of the compensation processing unit 311 through the quadrature modulator distortion measurement system 312. On this input side, a target vector, for example, vectors A, B, ...
, Respectively, and the corresponding vectors A ₁ , B ₁ ... Are obtained.

If a discrete value such as the vector A, B ... Is taken, a sudden change will be involved in the processing, so that a waiting time (weight) for stabilization is inevitably required. However, in the fifth modified example, since each vector smoothly transits, the processing does not include a sudden change, and therefore, the waiting time for stabilization is also unnecessary.

FIG. 27 is a diagram showing a main routine used in the fifth improvement example based on the first embodiment. FIG. 28 is a flow chart of vector value measurement used in the fifth improved example based on the first embodiment. 27 corresponds to FIGS. 13 and 14 already described, and FIG. 28 corresponds to FIG. 15 already described. Referring first to FIG. 27, reference symbols S1, R1 ...
13 and 14 use the corresponding symbols as they are. Note that the compensation value calculation routine R4 and the compensation value update routine R5 are as described above and are not changed at all.

Next, referring to FIG. 28, step S1: Initialize the total number M of continuous vectors described above and start the process from the first vector (m ←
1). Step S2: Vectors are designated one by one from the output vector table in the DSP (311).

Step S3: Same as step S1 'in FIG. Step S4: Same as step S2 'in FIG. Step S5: Output from quadrature demodulator 51 (level)
Is input to the compensation processing unit 311. Step S6: The input value of step S5 is written in the demodulation table based on the orthogonal demodulation processing function in the compensation processing unit 311 described above.

Step S7: Sample the next vector. Step S8: When the total number of vectors (M) is reached (+1 indicates returning to the original), the process proceeds to step S9. Step S9: Required vector (vectors A, B, C ...
Etc.) are subjected to quadrature demodulation processing.

After all, under the fifth improved example, when sampling the values of a plurality of vectors on the plane defined by the in-phase axis and the quadrature axis, which correspond to the in-phase input and the quadrature input, the origin on the plane is determined. As a center, a continuous vector that continuously shifts between adjacent vectors is set. Next, a sixth improved example based on the present invention will be described.

In the fifth improved example described above, in order to shorten the time until the compensation value is calculated, discrete vectors (A, B,
The value of the vector that continuously shifts in small steps was used instead of the value of C ...). In the sixth modified example to be described below, the time until the compensation value is calculated is similarly shortened even when the values of the discrete vectors (A, B, C ...) Are used.

Therefore, a delay element of processing existing in all systems for calculating a compensation value is found, and the influence of this delay element is minimized. FIG. 29 is a diagram showing a configuration of a sixth improved example based on the present invention. In addition,
Although the configuration of this drawing is drawn based on the configuration of FIG. 18, the idea of the sixth improved example can be applied not only to the first embodiment but also to the second embodiment (FIG. 11).

This sixth improved example focuses on the fact that the delay time of the low-pass filters (LPF) 23 and 24 is the main cause of the time required for the vector to become stable after being set to a certain value. Is. Therefore, when the compensation value for the distortion of the quadrature modulator 51 is obtained, the LPFs 23 and 24 are passed by controlling the switch means 25 from the compensation processing unit (DSP) 311 (connected to each lower contact in the figure). Try not to.

As a result, the discrete vectors (A, B
...) can be used to shorten the time until the compensation value is obtained. After the above-mentioned calculation of the compensation value is completed and the transmission device 10 enters the normal operation, each contact in the switch control means 25 is switched from the lower side to the upper side. At this time, the contact of the switch means 69 is switched from the upper side to the lower side. These switching commands are given from the DSP (311).

After all, according to the sixth improved example, the low-pass filters 23 and 24 are provided to the in-phase low-pass filter 23 and the quadrature-side low-pass filter 24 provided on the input side of the quadrature modulator 51. Only when the compensating circuit 31 is operating, the switch means 69 is provided, which bypasses and connects to the output side of the compensation processing unit 311. Next, a seventh improved example based on the present invention will be described.

This seventh modified example is similar to the above modified example.
This is intended to shorten the time until the compensation value is calculated. The point is that the sampling cycle for operating the compensation circuit 31 is returned to the original speed in the normal time, which is early only when the compensation value is calculated. FIG. 30 shows a seventh embodiment according to the present invention.
It is a figure which shows the structure of the improved example of FIG. The seventh improved example can be applied to both the first embodiment and the second embodiment, but FIG.
It is drawn based on the configuration of 8.

The point to be noted in FIG. 30 is the variable clock generating means 90. The means 90 may have any configuration as long as it can switch between high-speed and low-speed clocks for output, but in this figure, the means 90 is one example.
A high-speed clock source (CLOCK2) 93, a low-speed clock source (CLOCK1) 92, and these clock sources 92
And a switch 91 for selectively switching the outputs of 93 and 93. As another example, the clock generation means 90 may be configured by a single high-speed clock source, and a thinning circuit that appropriately thins or outputs the output clock pulse.

FIG. 31 is an operation timing chart in the circuit of FIG. In this figure, (1) is the DA of FIG.
The clock pulse train given to C21 and 22 and ADC65 is shown. It should be noted that although drawn with two kinds of amplitudes, a high-amplitude pulse train represents a pulse from the low-speed clock source 92,
The low amplitude pulse train represents the pulses from the high speed clock source 91.

(2) in the figure shows the sampling pulse during the measurement of the compensation value, and (3) in the figure shows the sampling pulse during the normal operation (including the measurement of the power amplification distortion).
After all, according to the seventh modified example, the variable clock generating means 90 is provided which supplies the high-speed sampling pulse only during the operation of the compensation circuit 31 and otherwise supplies the low-speed sampling pulse.

Next, an eighth improved example based on the first embodiment will be described. When the compensation value is updated under the first embodiment (see FIG. 17), if the compensation value has already reached a value that can be calculated with the accuracy of the compensation system, the compensation value is moved back and forth around a certain compensation value. The value changes to. When the update change width at the time of completion of this drive-in (immediately before “end” in FIG. 14) is large, the compensation value driven in to the optimum cutting angle value may move in the opposite direction to a large extent, which has a good effect. Do not give.

In such a case, in the eighth improved example, the updated value of the compensation value is multiplied by the gain constant (g) smaller than 1. Then, the movement becomes as if the loop gain of the quadrature modulator distortion measurement system is lowered, and the change width of the compensation value update can be reduced, so that the above-mentioned transition to the deterioration direction is eliminated. As a result, a stable compensation value can be obtained.

In the case of the gain deviation compensation value (k _q ), since it is multiplied by the update value changing around 1, the value obtained by subtracting 1 from the updated compensation value is multiplied by a constant smaller than 1. It is better to use the value obtained by adding 1 again. FIG.
FIG. 14 is a diagram showing a routine for updating a compensation value under an eighth improvement example based on the first embodiment. This figure corresponds to FIG. 17 described above, but the carrier leak compensation value (i _dc ,
q _dc ) is multiplied by g1 as the above gain constant.

As the gain deviation compensation value (k _q ), g2 is used as the gain constant, and the value obtained by subtracting 1 from the updated compensation value (k _qt ) is multiplied by the gain constant g2 and added with 1. . Compensation value of the phase deviation for (k) is updated compensation values for (k _t) multiplied by g3 as the gain constants. All of the above g1, g2 and g3 are smaller than 1.

After all, under the eighth improved example, when the above-mentioned compensation values for generating the compensated in-phase input and quadrature input are repeatedly updated a predetermined number of times,
Of the distortions generated in the quadrature modulator 51, the compensation value for the carrier leak and the phase deviation is 1 for the compensation value.
When the distortion is a gain deviation, the value obtained by subtracting 1 from the compensation value of the gain deviation is multiplied by a gain constant smaller than 1, and then 1 is set again. It is updated to add.

Next explained is a ninth improved example based on the first embodiment. According to the eighth improved example, the accuracy at the time of the completion of the drive is stably improved, but the drive time of the compensation value becomes long. Therefore, in the ninth improvement example, the compensation value updated for the first few times at the start of driving is used as it is without being multiplied by the gain constant, and then the gain constant smaller than 1 is used. . In this way, the drive-in can be speeded up, and the precision at the time of the drive-in is further improved.

FIG. 33 is a diagram showing a compensation value updating routine under the ninth improvement example based on the first embodiment. FIG.
Step S is preceded by a routine R1 which is exactly the same as that of 2.
1, S2 and S3 are executed. The number of times of the above-mentioned driving-in is N, and N usually reaches the optimum compensation value when it exceeds 3 times. Therefore, when the number of times is less than 3 (NO in step S1), the routine R1 is entered through step S2 while keeping each gain constant at 1.

However, if the number of times exceeds 3 (YES in step S1), in step S3, a gain constant smaller than 1 is set as g1, g2, and g3, and then the routine R1 is entered. After all, under the ninth improved example, the above-mentioned gain constant is set to 1 until the above-mentioned predetermined number of repetitions (N) reaches a predetermined number, and after that number of times, the gain constant is set to 1 To make it smaller.

The effect of the ninth improved example described above will be verified by simulation. FIG. 34 is a diagram showing a carrier leak drive-in characteristic when the ninth improved example is not applied. FIG. 35 is a diagram showing a carrier leak drive-in characteristic when the ninth improved example is applied.

Comparing the above two figures, as seen from the characteristics of FIG. 35, it is possible to improve the compensation accuracy at the time of completion of the drive while making the drive fast.

[0102]

As described above, according to the present invention, the following effects can be obtained. (1) According to the configurations of FIGS. 1, 10, and 11 (basic configuration, first and second embodiments), downsizing and cost reduction can be achieved. (2) According to the configuration of FIG. 10 (basic of the first embodiment), it is possible to shorten the time for obtaining the compensation value.

(3) According to the configuration of FIG. 18 (common type),
It enables downsizing and price reduction. (4) In the configuration based on FIGS. 19 and 20, (first
Improved example), carrier leakage compensation characteristics can be improved. (5) In the configuration based on FIGS.
The improved example), the phase deviation compensation characteristic can be improved even when there are many phase errors.

(6) In the configuration based on FIGS. 23 and 24 (third improved example), the carrier leak compensation characteristic can be improved even when the gain is different depending on whether the axis is positive or negative. (7) According to the configuration based on FIG. 25 (fourth improved example),
Even when the gain is different depending on whether the axis is positive or negative, the gain deviation compensation characteristic can be improved. (8) According to the configuration based on FIGS. 26, 27 and 28 (fifth improved example), it is possible to shorten the time for obtaining the compensation value.

(9) According to the configuration of FIG. 29 (sixth improvement example), it is possible to shorten the time for obtaining the compensation value. (10) According to the configurations of FIGS. 30 and 31, (seventh improvement example), it is possible to shorten the time for obtaining the compensation value. (11) With the configuration based on FIG. 32 (eighth improvement example), a stable compensation value can be obtained at the completion of the drive-in.

(12) With the configuration based on FIG. 33 (the ninth improved example), it is possible to improve the compensation accuracy when the drive-in is completed, while the drive-in is accelerated.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram showing a compensation circuit for a quadrature modulator according to the present invention.

FIG. 2 is a diagram for briefly explaining a method proposed in a publication.

FIG. 3 is a flowchart of a conventional main routine.

FIG. 4 is a flowchart (part 1) of a conventional carrier leak compensation value calculation.

FIG. 5 is a flowchart (part 2) of a conventional carrier leak compensation value calculation.

FIG. 6 is a flowchart of conventional level measurement.

FIG. 7 is a flowchart of a conventional gain deviation compensation value calculation.

FIG. 8 is a flowchart of a conventional phase deviation compensation value calculation.

9 is a signal flow graph of the compensation circuit 31. FIG.

10 is a diagram showing a first embodiment of the basic configuration shown in FIG.

11 is a diagram showing a second embodiment of the basic configuration shown in FIG.

12A, 12B and 12C are vector diagrams for explaining the first embodiment.

FIG. 13 is a diagram showing a flowchart (No. 1) of a main routine in the first embodiment.

FIG. 14 is a view showing a flowchart (No. 2) of the main routine in the first embodiment.

FIG. 15 is a diagram showing a flowchart of vector value measurement in the first embodiment.

FIG. 16 is a diagram showing a flowchart of compensation value calculation in the first embodiment.

FIG. 17 is a diagram showing a flowchart of compensation value update in the first embodiment.

18 is a diagram showing a configuration example in which the components are shared in the configuration of FIG.

FIG. 19 is a vector diagram for explaining a first improvement example based on the first embodiment.

FIG. 20 is a diagram showing a routine added in a first improvement example based on the first embodiment.

FIG. 21 is a vector diagram for explaining a second improvement example based on the first embodiment.

22A and 22B are routines added in the second improved example based on the first embodiment, and FIG. 22A is a diagram showing a vector B and FIG.

FIG. 23 is a vector diagram for explaining a third improvement example based on the first embodiment.

FIG. 24 is a diagram showing a routine added in a third improvement example based on the first embodiment.

FIG. 25 is a signal flow graph in the case of compensating the gain deviation with the compensation value obtained by the fourth improved example according to the present invention.

FIG. 26 is a vector diagram for explaining a fifth improvement example based on the first embodiment.

FIG. 27 is a diagram showing a main routine used in a fifth improvement example based on the first embodiment.

FIG. 28 is a flowchart of vector value measurement used in a fifth improvement example based on the first embodiment.

FIG. 29 is a diagram showing the configuration of a sixth improved example based on the present invention.

FIG. 30 is a diagram showing a configuration of a seventh improved example based on the present invention.

FIG. 31 is an operation timing chart in the circuit of FIG. 30.

FIG. 32 is a diagram showing a routine for updating a compensation value under an eighth improvement example based on the first embodiment.

FIG. 33 is a diagram showing a routine for compensation value update under a ninth improvement example based on the first embodiment.

FIG. 34 is a diagram showing a carrier leak drive-in characteristic when the ninth improved example is not applied.

FIG. 35 is a diagram showing carrier leak drive-in characteristics in the case where the ninth improved example is applied.

FIG. 36 is a diagram showing an example of a conventional compensation circuit applied to a quadrature modulator in a transmission device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Transmitter 11 ... Frequency converter 12 ... Low-pass filter 13 ... Rectifier 21 ... Digital-analog converter 22 ... Digital-analog converter 23 ... Low-pass filter 24 ... Low-pass filter 25 ... Switch means 31 ... Compensation circuit 311 Compensation processing unit 312 ... Quadrature modulator distortion measurement system 313 ... Power amplification distortion measurement system 41 ... PLL circuit 43 ... PLL circuit 51 ... Quadrature modulator 62 ... Amplifier 63 ... Bandpass filter 64 ... Rectifier 65 ... Analog / digital Converter 69 ... Switching means 71 ... Power amplifier 90 ... Variable clock generating means

Claims (16)

[Claims] 1. A compensating circuit (31) provided in a transmitting device (10) including a quadrature modulator (51) for compensating for distortion generated in the quadrature modulator (51), A frequency converter (11) for converting the modulation output from the quadrature modulator (51) into a low frequency modulation output having a frequency lower than the modulation carrier frequency; and a low pass filter for removing a high frequency region of the low frequency modulation output.
Distortion occurring in the quadrature modulator (51) using a filter (12), a demodulation processing function for performing quadrature demodulation on the output from the low-pass filter (12), and a demodulation output obtained by the quadrature demodulation. Compensation unit (311) having a distortion compensation function for generating an in-phase input and a quadrature input which are compensated for and giving the quadrature input to the quadrature modulator (51). circuit. 2. Compensation value of in-phase axis (I axis) is calculated in the compensation value of carrier leak among distortions generated in the quadrature modulator (51).
From the input value that is input to the compensation processing unit (311) when the in-phase input on the in-phase axis is output, the compensation value of the orthogonal axis (Q axis) is obtained from the compensation processing unit (311).
The compensation circuit according to claim 1, wherein the compensation circuit obtains an orthogonal input on the orthogonal axis from the input value input to the compensation processing unit (311). 3. Regarding the phase deviation of the distortion generated in the quadrature modulator (51), a value rotated by 45 ° from the in-phase axis (I axis) is calculated from the compensation processing unit (311) in the calculation of the compensation value. When output, the compensation processing unit (311)
When the input value input to the and the value rotated by 45 ° from the orthogonal axis (Q axis) are output from the compensation processing unit (311), the compensation processing unit (311)
The compensation circuit according to claim 1, wherein the compensation value for the phase deviation is obtained using the input value input to the compensation circuit. 4. In the calculation of the compensation value for the carrier leak of the distortion generated in the quadrature modulator (51), the in-phase axis (I axis) and the quadrature axis (Q axis) are calculated from the compensation processing unit (311). The compensation value according to claim 1, wherein the compensation value is obtained by using the demodulation output corrected by the value input to the compensation processing unit (311) when the value corresponding to the origin at which circuit. 5. In calculating a compensation value for a gain deviation of distortion generated in the quadrature modulator (51), the in-phase input takes a positive value or a negative value on the in-phase axis (I axis). Different gain deviation compensation values are set according to whether the quadrature is taken, and different gain deviation compensation is performed depending on whether the quadrature input takes a positive value or a negative value on the quadrature axis (Q axis). The compensation circuit according to claim 1, wherein the value is set. 6. When sampling the values of a plurality of vectors on the plane defined by the in-phase axis and the quadrature axis, which correspond to the in-phase input and the quadrature input, between the adjacent vectors centering on the origin on the plane. 2. A continuous vector is set so as to continuously shift
Compensation circuit according to. 7. The low-pass filter (23, 24) is provided to the in-phase low-pass filter (23) and the quadrature-side low-pass filter (24) provided on the input side of the quadrature modulator (51). Switching means (69) for bypassing and connecting to the output side of the compensation processing unit (311) only while the compensation circuit (31) is operating.
The compensation circuit according to claim 1, wherein the compensation circuit is provided. 8. A variable clock generation means (9) for supplying a high speed sampling pulse only during the operation of the compensation circuit (31) and supplying a low speed sampling pulse otherwise.
0) comprising a compensation circuit according to claim 1. 9. A carrier leak and a phase deviation among distortions generated in the quadrature modulator (51) when the compensation values for generating the compensated in-phase input and quadrature input are repeatedly updated a predetermined number of times. The compensation value is updated by multiplying the compensation value by a gain constant smaller than 1, and when the distortion is a gain deviation, the value obtained by subtracting 1 from the compensation value of the gain deviation is smaller than 1. The compensation circuit according to claim 1, wherein the compensation circuit is updated by multiplying by a gain constant and then adding 1 again. 10. The gain constant is set to 1 until the predetermined number of repetitions reaches a predetermined number, and the gain constant is made smaller than 1 after the number of times has elapsed.
Compensation circuit according to. 11. A quadrature modulator (51) provided in a transmitter (10) including a quadrature modulator (51).
A compensating circuit (31) for compensating for distortion generated in the frequency converter (11) for converting the modulation output from the quadrature modulator (51) into a low frequency modulation output having a frequency lower than the modulation carrier frequency. And a low-pass filter that removes the high-frequency region of the low-frequency modulation output.
A filter (12), a rectifier (13) for rectifying the output from the low-pass filter (12), and a distortion generated in the quadrature modulator (51) based on the rectified output from the rectifier (13) A compensation circuit for a quadrature modulator in a transmitter, comprising: a compensation processing unit (311) for applying the in-phase input and the quadrature input to the quadrature modulator (51). 12. A quadrature modulator (51) provided in a transmission device (10) including a quadrature modulator (51).
A compensating circuit (31) for compensating for distortion generated in the frequency converter (11) for converting the modulation output from the quadrature modulator (51) into a low frequency modulation output having a frequency lower than the modulation carrier frequency. And a low-pass filter that removes the high-frequency region of the low-frequency modulation output.
A filter (12) and an in-phase input and a quadrature input which have a rectifying function for rectifying the output from the low-pass filter (12) and compensate for distortion generated in the quadrature modulator (51) based on the rectified output. A compensation circuit for a quadrature modulator in a transmitter, comprising: a compensation processing unit (311) provided to the quadrature modulator (51). 13. In calculating a compensation value for gain deviation of distortion generated in the quadrature modulator (51), the in-phase input takes a positive value or a negative value on the in-phase axis (I axis). Different gain deviation compensation values are set according to whether the quadrature is taken, and different gain deviation compensation is performed depending on whether the quadrature input takes a positive value or a negative value on the quadrature axis (Q axis). 13. The compensation circuit according to claim 11, wherein the value is set. 14. The low-pass filter (23, 24) is provided to the in-phase low-pass filter (23) and the quadrature-side low-pass filter (24) provided on the input side of the quadrature modulator (51). Switching means (69) for bypassing and connecting to the output side of the compensation processing unit (311) only while the compensation circuit (31) is operating.
The compensation circuit according to claim 11, wherein the compensation circuit is provided. 15. Only during operation of the compensation circuit (31),
13. Compensation circuit according to claim 11 or 12, comprising variable clock generating means (90) for supplying high speed sampling pulses and for supplying otherwise low speed sampling pulses. 16. A first component group constituting a power amplification distortion measurement system (313) for measuring distortion peculiar to a power amplifier (71) provided in the transmitter (10), and the quadrature modulator. For the common component group with the second component group constituting the quadrature modulator distortion measurement system (312) for compensating the distortion generated in (51), these are selected by the switch means (69). The compensation circuit according to any one of claims 1, 11 and 12, wherein the compensation circuit is switched and shared.