JPH09321732A - Data transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit data without receiving the influence of frequency characteristic. SOLUTION: In a transmitter 10, after a base band binary data S is serial- parallel-converted by a serial-parallel converter 11 and reverse-Hadamard- transformed by a reverse-Hadamard transformer 12 and then it is analog- converted by a D/A converter 13 and angularly modulated by a voltage- frequency converter 14 to be transmitted through a radio transmission channel. At a receiver 20, transmitted data is demodulated by a frequency-voltage converter 24, digitally converted by an A/D converter 23, Hadamard-transformed by a Hadamard-transformer 22 and then reproduced to base band binary signal data by a parallel-serial converter 21.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OFDM (Orthogonal Frequency) used for a modulation / demodulation device for a wired transmission line or a wireless transmission with no frequency band use restriction or wireless transmission of infrared rays.
The present invention relates to a data transmission device of a quencyDivision Multiplexing (orthogonal frequency division multiplexing) system, and particularly to a data transmission device capable of realizing communication having strong frequency characteristics.

2. Description of the Related Art Hitherto, digital transmission of data has become widespread. For digital data transmission, high-efficiency encoding of baseband signals, digital modulation, and encoding and decoding corresponding to various transmission paths have been performed. There is a demand for technologies such as conversion. In order to respond to such a demand for digitization, F
SK data transmission is adopted. F like this
As shown in FIG. 8, a data transmission device that performs SK data transmission includes a transmitter 1 and a receiver 2, and the transmitter 1 includes binary (1, 0) voltage values to be transmitted. Serial data (FIG. 9) is modulated into a frequency corresponding to each value of the frequency of the sine wave that is the carrier wave. Two
In order to modulate the sine wave with the value data, in the transmitter 1, when the serial data value is 0, a low frequency sine wave is output as shown in FIG. 10, and when the serial data value is 1. , A high frequency sine wave is output. The signal output from the transmitter 1 is transmitted by a wireless or wired transmission line and input to the receiver 2. In the receiver 2, the modulated sine wave signal is frequency-voltage converted and binary data is obtained.

However, in such a data transmission apparatus, since a sine wave is used as a carrier wave, it is unavoidable that the frequency characteristic of the transmission line is received, and the voltage of the data value converted by the receiver is unavoidable. In some cases, erroneous data was obtained. Further, there is a problem that the device becomes large-scale and the capacity of the data memory also becomes large. The present invention has been made in order to solve such a problem, and does not require a complicated device and prevents erroneous transmission of data by reducing the voltage of the data value, thereby performing accurate data transmission. An object of the present invention is to provide a data transmission device capable of performing the above.

In order to achieve this object, a data transmission apparatus according to the present invention comprises a serial-parallel converter for converting baseband binary signal data into serial-parallel conversion, and inverse-Hadamard conversion for serial-parallel converted data. Inverse Hadamard converter, D / A converter for digital-analog conversion of inverse Hadamard converted data, transmitter having angle modulator for angle-modulating and transmitting digital-analog converted data, and angle-modulating and transmitting A demodulator that demodulates and receives the received data, an A / D converter that converts the demodulated data to analog-digital, a Hadamard converter that converts the analog-digital-converted data into a Hadamard, and a parallel serial of the Hadamard-converted data A parallel system for converting and reproducing baseband binary signal data. It is obtained by a receiving apparatus having a Al transducer. In such a data transmission device, baseband binary signal data is serial-parallel converted, serial-parallel converted data is inverse Hadamard converted, and analog-converted data is angle-modulated to transmit the data. In the receiver, the transmitted data is subjected to Hadamard conversion, and then converted into binary data by using the threshold value as a reference to reproduce the data. Therefore, the data to be transmitted is not affected by the frequency characteristic, and the incorrect data is not transmitted due to the voltage drop accompanying the transmission, and the accurate data can be transmitted.

BEST MODE FOR CARRYING OUT THE INVENTION The data transmission device of the present invention will now be described.
Preferable applied to data transmission equipment that transmits data by wire
Embodiments will be described in detail with reference to the drawings. FIG.
As shown in FIG.
And a communication device 20. The transmitter 10 is
Data signal S of binary band signal_TenThe serial parallel
A serial-parallel converter 11 for converting a digital signal is included. Siri
The parallel-to-parallel converter 11 is a series of binary voltage values.
For converting an Al signal into, for example, an 8-bit synchronization signal
It is. The output side of the serial / parallel converter 11 is an inverse adder.
It is connected to the Marl converter 12. Inverse Hadamard transformer 1
2 is the inverse Hadamard data that has been converted from serial to parallel
As shown in FIG. 2, the serial
It is connected to each of the eight output terminals of the Larel converter 11.
8 data input terminals I₁₁, I₁₂, I₁₃, I₁₄,
I_Fifteen, I₁₆, I₁₇, I₁₈Equipped with an input port to which
The data selector 101,
Output side (output data signal S₁₁) Is a 1-bit multiplier
103 is provided. Furthermore, the input port of the multiplier 103
A 64-bit data memory 102 connected to
Output side of the data memory 102 (output data signal
S₁₂) Is connected to the multiplier 103. Output of multiplier 103
Force side (output data signal S₁₃) Is a 4-bit adder 10
4 is provided, and the output side of the adder 104 (output data signal
S₁₄) Is provided with a 4-bit latch register 105
You. Output side of the latch register 105 (output data signal S
_Fifteen) Is connected to the input side of the adder 104 and D
It is designed to be connected to the / A converter 13. here,
Output data signal S_FifteenIs shown in Figure 3, as described below.
As you can see, it is a multilevel digital signal. Data processing
Output signal Φ of the imming generator 107₁₁, Φ₁₂, Φ₁₃Is de
Input as a column address signal of the data selector 101,
Output signal Φ of data processing timing generator 107₁₄, Φ
_Fifteen, Φ₁₆Is input as a row address signal of the data memory 102.
Is forced. Further, the data processing timing generator 107
Output signal Φ₁₇, Φ₁₈Is the rise of the latch register 105
Latch signal and L level active data clear signal
Is entered as. Reverse adada like this
4-bit D / A conversion on the output side of the Marl converter 12
Is provided with a digital signal from the latch register 105.
Output data signal S_FifteenIs input, analog conversion
The analog output data signal S₁₆To output
ing. Output signal of data processing timing generator 107
No.Φ₁₉Is the rising edge signal of the input data of the D / A converter 13.
Is entered as. D / A converter 13
On the output side of the voltage frequency converter (VC
O) 14 is connected. The voltage frequency converter 14 is a digital
Output signal S converted into analog₁₆And further
Output data signal S₁₇Is output
It is. Angle modulation is the frequency modulation of data of a specified voltage value.
Alternatively, the output data signal S₁₆
By frequency-modulating or phase-modulating
Therefore, the frequency is set to correspond to multilevel digital signals.
Output data signal S₁₇And is sent from the transmitter 10.
It is. The receiving device 20 outputs the output data from the transmitting device 10.
Signal S₁₇Input data signal S transmitted by₂₀Is entered
A frequency-voltage converter that is a demodulator (for example, an FM demodulator,
The frequency discriminator) 24 is provided, and the frequency or
Analog converted to voltage value corresponding to phase and demodulated
Data signal S_{twenty one}Is output. Of the frequency voltage converter 24
On the output side, a 4-bit A / D converter 23 is connected,
Analog data signal S_{twenty one}Is converted to digital,
Output data signal S_{twenty two}(4 bits) is output. A
The output side of the / D converter 23 is a digital output data signal.
S_{twenty two}Is provided with a Hadamard converter 22 for Hadamard conversion
Can be The Hadamard transformer 22, as shown in FIG.
Output data signal S output from A / D converter 23_{twenty two}To
To store as sampling data for one frame
Connected to the input port of the FIFO 203 of 4 bits x 8
It is. Output side of FIFO 203 (output data S_{twenty two}’(4
Bit)) is one input port of the 4-bit multiplier 204.
Connected to the other input port of the multiplier 204
Is connected to the 64-bit data memory 202,
Output data signal S from the memory 202_{twenty three}(1 bit)
Is entered. Output side of multiplier 204 (output data signal
S_{twenty four}(4 bits)) is one of 4-bit adder 205
Connected to the input port of the output side of the adder 205 (output
Data signal S_{twenty five}(4 bits)) is the latch register 206
Connected to. Output side of the latch register 206 (output
Data signal S₂₆(4 bits) is added to the 1/8 frequency divider 207
It is connected to the other input port of the calculator 205. Frequency division
Output side of output device 207 (output data signal S₂₇(1 bit))
Is an 8-bit S / P (serial / parallel) converter 208
Connected to the output port of the S / P converter 208
The data output terminal is connected. Data synchronized with one frame
Output signal Φ of the data processing timing generator 209_{twenty one},
Φ _{twenty two}, Φ_{twenty three}, Φ_{twenty four}, Φ_{twenty five}, Φ₂₆Is the data memory 202
Input as the address signal of₂₇, Φ₂₈The latch
The rising latch signal of the register 206 and the L level
It is input as an active data clear signal. Data processing
Output signal Φ of the logic timing generator 209₂₀, Φ₂₉Is A
Sampling lock signal of the D / D converter 23 and 8 bits
Rising shift lock signal of the S / P converter 208 of
Is entered. On the output side of the Hadamard converter 22,
Eight outputs of the S / P converter 208 of the Hadamard converter 22
Force terminal O_{twenty one}, O_{twenty two}, O_{twenty three}, O_{twenty four}, O_{twenty five}, O₂₆, O₂₇, O
₂₈And a comparator 25 connected to
Output from each output terminal in the comparator 25
The signal is compared with the threshold value and output as 0 or 1 data.
It is supposed to be. On the output side of the comparator 25
A parallel-serial converter 21 is provided, and a binary voltage value
Serial data signal S₃₀To be converted to
You. Transmitter 1 of the data transmitter configured as described above
At 0, the serial / parallel converter 11 outputs a binary signal.
Issue data S_TenIs converted to an 8-bit sync signal and
In the Haar converter 12, the inverse Hadamard transform is performed,
Will be converted. This encoding converts the input data into 64 bits
Hadamard matrix (8 ×
8) by the inverse Hadamard transform.
The inverse Hadamard transform of input data is a 64-bit data
Hadamard matrix and input data input to memory 102
It is realized by performing "convolution operation" in. 6
Hadamard row input to 4-bit data memory 102
The column has a column address offset of Φ, as shown in Table 1.
₁₁, Φ₁₂, Φ₁₃, The row address offset is Φ₁₄,
Φ_Fifteen, Φ₁₆Is specified by, for example, as shown in FIG.
And the row address signal of the data memory 102 is Φ₁₁=
0, Φ₁₂= 1, Φ₁₃= 0, sequentially from the beginning of the second line
Read output data signal S₁₂And the data selector 101
Input data signal S selected in₁₁Is multiplied by the multiplier 103
The output data signal S of the multiplier 103₁₃And Latch Regis
Output data signal S of data 105_FifteenIs added by the adder 104
You. The above is repeated 8 times, and finally the latch register 105
Output data signal_FifteenTo the D / A converter 13 ₁₉Rise
After latching with the glue, Φ₁₈To L level
The contents of register 105 are cleared to zero. Each of the above in Table 1
Output data signal S of one frame repeated eight times in column order_FifteenTo
To generate.

[Table 1] The output data signal S ₁₅ encoded in this way is D / A
After the digital-analog conversion is performed in the converter 13 and the output data signal S ₁₆ having a composite waveform of a plurality of frequencies is converted, frequency modulation is performed in the voltage frequency converter 14. Further, the digital output data signal S ₁₆ having a composite waveform of a plurality of frequencies is transmitted as an analog output data signal S ₁₇ . On the other hand, in the receiving device 20, the output data signal S ₁₇ is transmitted and becomes the input data signal S ₂₀ , which is input to the receiving device 20 and converted into a voltage signal by the frequency-voltage converter 24. S ₂₁ is output. The output data signal S ₂₁ is sampled by the A / D converter 23 at each rise of Φ ₂₀ of the timing generator 209, and 8 data are recorded in the FIFO 203 in one frame of the output data signal S ₂₁ .
The Hadamard transform is similar to the encoding, and the input data and the table 1
It can be realized by performing "convolution operation" of and then dividing by 8. For example, when the row address signal of the data memory 202 is Φ ₂₁ = 0, Φ ₂₂ = 1 and Φ ₂₃ = 0, as shown in FIG. 7, the signal S ₂₃ sequentially read from the beginning of the second row of the data memory 202. And the input data signal S ₂₂ ′ read from the FIFO 203 are multiplied by the multiplier 204, and the output signal S ₂₄ of the multiplier 204 and the output data signal ₂₆ of the latch register 206 are added by the adder 205. The above is repeated 8 times, and finally the output data signal S ₂₇ obtained by dividing the output data signal ₂₆ of the latch register 206 by ⅛ frequency by the ⅛ frequency divider 207 is sent to the S / P converter 208 by 1 at the rising edge of Φ _29.
After the shift input for the data, Φ _{28 is set} to the L level and the contents of the latch register 206 are cleared to zero. The above operation is repeated eight times in each column of Table 1 to output 8-bit data from the data output terminal. The data signal decoded and output from the data output terminal is input to the comparator 25,
It is compared with a predetermined threshold value and classified into data of 0 or 1. As a result, the binary data is surely demodulated, and the baseband binary signal data S ₁₀ input to the transmitter 10 is input.
Is reproduced and a data signal ₃₀ of 8-bit data is output. Therefore, it is possible to reliably transmit the data without receiving the frequency characteristic due to the transmission. The present invention is not limited to the data transmission apparatus applied to the above-described wired data transmission, but can be applied to a wireless transmission line.
In addition, it can be diverted to a remote controller or a PCM audio transmission device.

As is apparent from the above description, according to the data transmission device of the present invention, the frequency is multiplexed by using the Hadamard function, the data is angularly modulated and transmitted, and the demodulated data is set to a constant threshold value. Since the data is classified according to the above and serial data is generated, accurate data transmission can be realized without being affected by frequency characteristics.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of a data transmission device according to the present invention.

FIG. 2 is a block diagram showing an inverse Hadamard transformer of a data transmission device according to the present invention.

FIG. 3 is an explanatory diagram showing the operation of the data transmission device according to the present invention.

FIG. 4 is an explanatory diagram showing the operation of the data transmission device according to the present invention.

FIG. 5 is a block diagram showing a Hadamard converter of a data transmission device according to the present invention.

FIG. 6 is an explanatory diagram showing the operation of the data transmission device according to the present invention.

FIG. 7 is an explanatory diagram showing the operation of the data transmission device according to the present invention.

FIG. 8 is a block diagram of a conventional data transmission device.

FIG. 9 is a diagram showing an operation of a conventional data transmission device.

FIG. 10 is a diagram showing an operation of a conventional data transmission device.

[Explanation of Codes] 10 ··· Transmission device 11 ··· Serial / parallel converter 12 ··· Inverse Hadamard converter 13 ··· D / A converter 14 ·・ ・ ・ ・ ・ Voltage frequency converter (angle modulator) 20 ・ ・ ・ ・ ・ Reception device 21 ・ ・ ・ ・ ・ ・ Parallel to serial converter 22 ・ ・ ・ ・ ・ ・ Hadamard converter 23 ・ ・ ・ ・ ・・ A / D converter 24 ・ ・ ・ ・ ・ ・ Frequency voltage converter (demodulator) S ₁₀・ ・ ・ ・ ・ ・ Baseband binary signal data

Claims (1)

[Claims] 1. A serial-parallel converter for serial-parallel converting baseband binary signal data (S ₁₀ ).
1), an inverse Hadamard converter (12) for inverse Hadamard conversion of serial-parallel converted data, a D / A converter (13) for digital-analog conversion of the inverse Hadamard-converted data, and an angle of the digital-analog converted data A transmitting device (10) having an angle modulator (14) for modulating and transmitting, a demodulator (24) for demodulating and receiving the data which has been angularly modulated and transmitted, and converts the demodulated data into analog-to-digital data. A / D converter (23), Hadamard converter (22) for Hadamard conversion of analog-digital converted data, Parallel-Serial conversion for parallel-serial conversion of Hadamard-converted data to reproduce the baseband binary signal data And a receiver (20) having a device (21).