JPH09321308A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the drain current by forming gates, sources which make continuity with source regions and overhang to the gates, drains which make continuity with drain sources and overhang to the gates, etc. SOLUTION: An NMOS transistor is composed of a gate G, first silicon nitride film 31, first silicon oxide film 41, a gate active layer 5, etc. At the sides of the active layer 5 a source and drain regions are formed. A source S, overhang source SH are formed on the source region through a second Si film 42 and drain D and overhang drain DH are formed on the drain region. When a voltage applied to the gate 4, a current flows between the source S and drain D and between the overhang source SH and overhang drain DH.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a MIS (MOS)
Semiconductor device including a thin film transistor.

[0002]

2. Description of the Related Art Conventionally, in the case of an inverted stagger, a MIS (MOS) type thin film transistor formed on a liquid crystal driving substrate of a liquid crystal display device is formed on a transparent insulating substrate such as a quartz glass substrate or a borosilicate glass substrate. Gate electrode, a gate active layer formed on the gate electrode via an insulating layer such as a silicon oxide film, and source and drain electrodes formed on the sides of the gate electrode.

In this semiconductor device, by applying a predetermined voltage to the gate electrode, carriers at the interface of the insulating layer in the gate active layer are controlled to turn ON / OFF the current flowing between the source electrode and the drain electrode. is there. When this semiconductor device is formed on the liquid crystal driving substrate, the transmission / cutoff of light in the liquid crystal layer is controlled by turning on / off the drain current between the source electrode and the drain electrode by applying a signal voltage to the gate electrode.

[0004]

However, in a conventional semiconductor device including a thin film transistor, when a drain current flows between a source electrode and a drain electrode, only a boundary between the insulating layers on the side of the gate electrode flows, so that a predetermined gate is formed. It was difficult to obtain sufficient source-drain current with respect to voltage.

Further, there is a limit to shortening the length of the gate active layer due to the fine processing in photolithography and the like, and it is difficult to improve the characteristics of the semiconductor device by shortening the gate length. .

[0006]

The present invention is a semiconductor device made to solve the above problems. That is, according to the present invention, in a semiconductor device including a thin film transistor, a source region provided on one side in the length direction of the gate active layer, a drain region provided on the other side in the length direction of the gate active layer, and a gate active layer. The gate electrode provided on one side in the thickness direction of the gate electrode through the first insulating layer and the gate electrode in the state of being electrically connected to the source region, and the protruding portion is the other side in the thickness direction of the gate active layer. And a source-side overhanging electrode provided on the gate electrode side in a state of being electrically connected to the drain region, and the overhanging portion is on the other side in the thickness direction of the gate active layer on the second insulating layer. And a predetermined gap is provided between the tip of the projecting portion and the tip of the projecting portion of the source-side projecting electrode. The drain side projecting electrode and a diffusion layer provided in the gate active layer corresponding to the gap between the source side projecting electrode and the drain side projecting electrode and having a conductivity type opposite to that of the channel of the gate active layer. It is equipped.

The source region provided on one side in the length direction of the gate active layer, the drain region provided on the other side in the length direction of the gate active layer, and the drain region provided on one side in the thickness direction of the gate active layer. The gate electrode provided through the first insulating layer and the gate electrode project in the state of being electrically connected to the source region, and the projecting portion is provided on the other side in the thickness direction of the gate active layer through the second insulating layer. The source side projecting electrode provided and the projecting part are projecting to the gate electrode side in a state of being electrically connected to the drain region, and the projecting part is provided on the other side in the thickness direction of the gate active layer through the second insulating layer, and is projecting. A drain side projecting electrode in which a predetermined interval is provided between the tip of the portion and the tip of the projecting portion of the source side projecting electrode, and a gate active layer. It is also a semiconductor device and a LDD region provided in each of the definitive source region side and drain region side.

According to the present invention, the gate electrode is provided on one side in the thickness direction of the gate active layer via the first insulating layer, and on the other side the source-side protruding electrode is electrically connected to the source region via the second insulating layer. And the drain-side protruding electrode that is electrically connected to the drain region, the source and drain voltages are always applied to the gate active layer through the second insulating layer.

As a result, when the NMOS type TFT is turned on, electrons are always accumulated at the interface between the gate active layer and the second insulating layer due to the source and drain voltages, and the electron accumulation region is formed, so that the LDD (Lightly Doped Dr
ain) will play a role equivalent to the structure. When a positive voltage is applied to the gate electrode in this state, electrons are also accumulated in the interface between the gate active layer and the first insulating layer to form a carrier channel region, and the source-drain current immediately flows. .

Further, when a positive voltage is applied, the electron storage region formed at the interface of the first insulating layer expands and fills the gap between the tip of the source side protruding electrode and the tip of the drain side protruding electrode. Source-drain current also flows at the interface between the two insulating layers. Therefore, by applying a positive voltage equal to or higher than a certain value, a source-drain current more than twice the normal current flows.

In this case, the length of the effective gate active layer can be shortened by the distance between the tip of the source side projecting electrode and the tip of the drain side projecting electrode, the drain current controllability at the gate voltage is improved, and the switching characteristics are improved. become able to.

Further, when the TFT is off, when a negative voltage is applied to the gate electrode, holes are accumulated at the interface between the gate active layer and the first insulating layer, and the source-drain current does not flow. When a larger negative voltage is applied, the hole storage region spreads to the second insulating layer side of the gate active layer, and the electron storage region at the interface of the second insulating layer of the source side extension electrode and the drain side extension electrode. Can be offset and reduced, the gap between the source-side protruding electrode and the drain-side protruding electrode can be filled, and the leak current and the tunnel leak current at the interface of the second insulating layer can be suppressed.

Further, since the diffusion layer having the conductivity type opposite to the conductivity type of the channel of the gate active layer is provided in the gate active layer, the leak current in the gap between the source side extension electrode and the drain side extension electrode. Can be positively reduced.

Furthermore, the LDD regions provided on the source region side and the drain region side of the gate active layer can alleviate the electric field applied to the gate active layer and further increase the drain breakdown voltage.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device of the present invention will be described below with reference to the drawings. 1 is a schematic sectional view for explaining a first embodiment of a semiconductor device of the present invention, FIG. 2 is a schematic sectional view for explaining a second embodiment, FIG. 3 is a schematic sectional view for explaining a third embodiment, and FIG. Is a schematic sectional view for explaining the fourth embodiment, FIG. 5 is a schematic sectional view for explaining the fifth embodiment, FIG. 6 is a schematic sectional view for explaining the sixth embodiment, and FIG. 7 is for explaining the seventh embodiment. FIG. 8 is a schematic sectional view for explaining the eighth embodiment, FIG. 9 is a schematic sectional view for explaining the ninth embodiment, and FIG. 10 is a schematic sectional view for explaining the tenth embodiment.

First, the structure and operation of the semiconductor devices of the first to fourth embodiments will be described. First, the semiconductor device 1 according to the first embodiment shown in FIG. 1 has an inverted staggered structure, and includes a gate electrode G provided on a transparent insulating substrate 2 such as quartz glass or borosilicate glass,
A first silicon nitride film 31 and a first silicon oxide film 41 formed on the substrate 2 so as to cover the gate electrode G;
The gate active layer 5 formed thereon constitutes an NMOS type thin film transistor.

Further, a source region and a drain region are provided on the sides of the gate active layer 5, a source electrode S is provided on the source region through a source side projecting electrode SH, and a source region is provided on the drain region. Is provided with a drain electrode D via a drain side projecting electrode DH.
The protruding portion of the source-side protruding electrode SH is arranged above the gate electrode G via the second silicon oxide film 42 on the gate active layer 5. The protruding portion of the drain-side protruding electrode DH is arranged above the gate electrode G via the second silicon oxide film 42 on the gate active layer 5. Moreover, a predetermined interval is provided between the tip of the protruding portion of the source-side protruding electrode SH and the tip of the protruding portion of the drain-side protruding electrode DH.

The source-side protruding electrode SH and the drain-side protruding electrode DH are made of a metal such as polycrystalline silicon or amorphous silicon of a predetermined conductivity type, aluminum, etc., but are made of the same material as the source region and the drain region. Is desirable.

Further, in the semiconductor device 1 according to the present embodiment, in the gate active layer 5 corresponding to the gap between the source-side protruding electrode SH and the drain-side protruding electrode DH, the conductivity type of the channel of the gate active layer 5 is opposite. The conductive type (P type in the example shown in FIG. 1) diffusion layer 5 a is formed into the second silicon oxide film 4.
It is provided from the interface 2 to the interface of the first silicon oxide film 41.

Next, in the second embodiment shown in FIG.
The semiconductor device 1 is of the same inverted stagger type as that of the semiconductor device 1 of the first embodiment shown in FIG. 1, and the gate electrode G, the first silicon nitride film 31, and the first silicon oxide film 4 provided on the substrate 2 are provided.
1, a gate active layer 5, a source electrode S and a drain electrode D, and a source-side overhanging electrode SH and a drain-side overhanging electrode DH arranged on the gate active layer 5 via the second silicon oxide film 42. The common difference is that the diffusion layer 5a provided in the gate active layer 5 is formed at a slight depth from the interface of the second silicon oxide film 42.

In addition, in the third embodiment shown in FIG.
A reverse stagger type similar to the semiconductor device 1 of the first embodiment shown in FIG.
The silicon nitride film 31, the first silicon oxide film 41, the gate active layer 5, the source electrode S and the drain electrode D, and the source-side overhanging electrode SH and the drain arranged on the gate active layer 5 via the second silicon oxide film 42. Although it is common in that it has the side projecting electrode DH, the second silicon oxide film 42 corresponding to the gap between the tip of the source side projecting electrode SH and the tip of the drain side projecting electrode DH is removed, and from this part. The difference is that the diffusion layer 5a is provided up to the interface of the gate active layer 5 on the side of the first silicon oxide film 41.

Further, in the fourth embodiment shown in FIG. 4, a gate electrode G formed on the substrate 2 and the first nitride, which is of an inverted stagger type similar to the semiconductor device 1 of the first embodiment shown in FIG. Silicon film 31, first silicon oxide film 41, gate active layer 5, source electrode S and drain electrode D, second
The common feature is that the source-side overhanging electrode SH and the drain-side overhanging electrode DH are provided on the gate active layer 5 via the silicon oxide film 42, but the tip of the source-side overhanging electrode SH and the drain-side overhanging electrode DH are common. The second silicon oxide film 42 corresponding to the gap with the tip of the gate active layer is removed, and the diffusion layer 5a is provided from this portion to a slight depth on the interface side of the second silicon oxide film 42 of the gate active layer 5. Differences in points.

In the semiconductor device 1 having these structures,
Depending on the voltage applied to the gate electrode G, the source electrode S-
Although the current flowing between the drain electrodes D can be controlled, the drain-side overhanging electrode DH, which is electrically connected to the drain region, overhangs above the gate active layer 5, so that the current between the source electrode S and the drain electrode D is applied to the gate electrode G. Since the drain voltage is always applied from the drain side protruding electrode DH to the gate active layer 5 even when the voltage for flowing the current is not applied, electrons are always accumulated at the interface of the second silicon oxide film 42. It will be in a state of being. This plays a role equivalent to that of the LDD structure.

When a positive voltage is applied to the gate electrode G in such a state, a carrier channel region is formed in the electron storage layer at the interface of the first silicon oxide film 41 on the gate electrode G side. As a result, a drain current flows, but by further applying a positive voltage to the gate electrode G, an electron accumulation region spreads also to the second silicon oxide film 42 side and the source on the second silicon oxide film 42 side. The region and the drain region are electrically connected to each other and the second silicon oxide film 42 is formed.
The drain current also flows at the interface.

Therefore, the presence of the source-side overhanging electrode SH and the drain-side overhanging electrode DH causes the drain current to flow also at the interface between the first silicon oxide film 41 and the second silicon oxide film 42. Even when applied, a large drain current can be made to flow.

On the other hand, when a negative voltage is applied to the gate electrode G, holes are accumulated at the interface of the first silicon oxide film 41 and a drain current does not flow between the source electrode S and the drain electrode D, that is, the source type. The electron storage regions at the interface of the second silicon oxide film 42 of the overhang electrode SH and the drain-side overhang electrode DH are canceled and reduced. Further, when a negative voltage is applied to the gate electrode G, the hole accumulation region spreads toward the second silicon oxide film 42 side, and the space L between the source-side overhanging electrode SH and the drain-side overhanging electrode DH. Therefore, the leak current and the tunnel leak current at the interface of the second silicon oxide film 42 can be suppressed.

Further, the diffusion layer 5a provided in the gate active layer 5 can positively reduce the leak current in the gap between the source-side overhanging electrode SH and the drain-side overhanging electrode DH.

That is, the semiconductor device 1 according to the present embodiment.
Then, the drain current and the leak current can be controlled by the size of the gap between the tip of the protruding portion of the source-side protruding electrode SH and the tip of the protruding portion of the drain-side protruding electrode DH and the diffusion layer 5a.

Next, the structure and operation of the semiconductor device according to the fifth to seventh embodiments will be described. The semiconductor device 1 of the fifth embodiment shown in FIG. 5 is of the same inverted stagger type as the semiconductor device 1 of the first embodiment shown in FIG. 1, and has the gate electrode G and the first silicon nitride provided on the substrate 2. Membrane 3
1, first silicon oxide film 41, gate active layer 5, source electrode S and drain electrode D, second silicon oxide film 42
The common feature is that the source-side overhanging electrode SH and the drain-side overhanging electrode DH are provided on the gate active layer 5 via the gate active layer 5, but the diffusion layer 5a (see FIG. 1) is provided in the gate active layer 5. However, the difference is that the conductivity type of the gate active layer 5 is opposite to the conductivity type of the channel.

The gate active layer 5 is composed of an extremely low concentration P type in the case of an N channel type and an extremely low concentration N type in the case of a P channel type.

Further, in the sixth embodiment shown in FIG. 6, in FIG.
A reverse stagger type similar to the semiconductor device 1 of the first embodiment shown in FIG.
The silicon nitride film 31, the first silicon oxide film 41, the gate active layer 5, the source electrode S and the drain electrode D, and the source-side overhanging electrode SH and the drain arranged on the gate active layer 5 via the second silicon oxide film 42. The gate active layer 5 is common in that it is provided with the side overhanging electrode DH.
LD is not formed on the source region side and the drain region side of the gate active layer 5 without the diffusion layer 5a (see FIG. 1) being provided in
The difference is that each D region 5b is provided.

In the semiconductor device 1 according to the sixth embodiment,
The LDD regions 5b are provided outside the portion of the gate active layer 5 corresponding to the gate electrode G, respectively.

Further, in the seventh embodiment shown in FIG. 7, the gate electrode G, the first silicon nitride film 31, the first silicon oxide film 41, the gate active layer 5, the source electrode S and the drain provided on the substrate 2 are provided. Electrode D, second silicon oxide film 4
The source side projecting electrode SH and the drain side projecting electrode DH disposed on the gate active layer 5 via the LDD region 5b provided on the source region side and the drain region side of the gate active layer 5, respectively. The LDD region 5b is the same as that of the sixth embodiment, but is different in that the LDD region 5b is provided outside from a position slightly entering the end of the portion of the gate active layer 5 corresponding to the gate electrode G.

Semiconductor device 1 in the fifth to seventh embodiments
Then, the basic operation is the same as that of the first to fourth embodiments, but the gate active layer 5 has a conductivity type opposite to that of the channel, and the LDD regions on the source region side and the drain region side of the gate active layer 5 are formed. By providing 5a, the electric field applied to the gate active layer 5 can be relaxed, the drain breakdown voltage can be increased, and the leak current can be further reduced.

Next, the eighth to tenth embodiments will be described. The semiconductor device 1 according to the eighth to tenth embodiments shown in FIGS. 8 to 10 is the fifth to seventh embodiments shown in FIGS. 5 to 7, respectively.
First silicon nitride film 3 of semiconductor device 1 in the embodiment
1 is arranged between the gate electrode G and the substrate 2.

The structure above the gate electrode G in the figure corresponds to the eighth embodiment shown in FIG. 8 and the fifth embodiment shown in FIG. 5, and the ninth embodiment shown in FIG. 9 and the sixth embodiment shown in FIG. Corresponds to the sixth embodiment shown in FIG. 10, and the tenth embodiment shown in FIG. 10 corresponds to the seventh embodiment shown in FIG. 7.

The operation as the semiconductor device 1 is the same as that of the semiconductor device 1 of the fifth to seventh embodiments, but in the eighth to tenth embodiments, the first silicon nitride is interposed between the gate electrode G and the substrate 2. Since the film 31 is provided, the sodium ions (N
Alkali metal ions such as a ⁺ ) can be more effectively prevented from entering the gate active layer 5, and the leak current can be reduced.

Next, a method of manufacturing the semiconductor device according to the first to fourth embodiments will be described in order. 11 to 12 are the first
It is sectional drawing explaining the manufacturing method of embodiment.

First, as shown in FIG. 11A, a gate electrode G made of, for example, a Mo / Ta alloy is formed on a substrate 2 made of transparent borosilicate glass by sputtering and etching by photolithography. The thickness is 300 nm, for example. At this time, a taper shape (10 to 20 °) is preferable for relaxation of electric field concentration.

Next, the first silicon nitride film 31 and the first silicon oxide film 4 are formed on the substrate 2 so as to cover the gate electrode G.
1, amorphous silicon film 51 ′, second silicon oxide film 42
Are continuously formed by plasma CVD. The first silicon nitride film 31 uses a reaction gas composed of SiH ₄ , NH ₃ , and N ₂ , and the first silicon oxide film 41 and the second silicon oxide film 42 use a reaction gas composed of SiH ₄ and O ₂ . The amorphous silicon film 51 ′ is formed at a temperature of about 300 ° C. using a reaction gas made of SiH ₄ .

The first silicon nitride film 31 has a thickness of about 200.
nm, the first silicon oxide film 41 has a thickness of about 50 nm, the amorphous silicon film 51 'has a thickness of about 30 nm, and the second silicon oxide film 42 has a thickness of about 50 nm. Here, the reason why the thickness of the first silicon nitride film 31 is thicker than the others is to prevent Na ⁺ contamination from entering from the glass substrate. Further, in order to improve the gate breakdown voltage between the gate and the drain and the source and drain breakdown voltages of the source-side projecting electrode SH and the drain-side projecting electrode DH, the film thicknesses of the first silicon oxide film 41 and the second silicon oxide film 42 are further increased. You may. However, it is necessary to consider the balance between crystallization and activation of the second silicon oxide film 42 by annealing by laser light irradiation.

Then, as shown in FIG. 11B, the second
After coating the resist R1 on the silicon oxide film 42, opening a slight gap by photolithography, and etching the second silicon oxide film 42, 10 ¹² to 10 ¹³ c
Doping with boron ions at a concentration of about m ⁻² . After that, the resist R1 is stripped with a solution of H ₂ SO ₄ : H ₂ O ₂ = 5: 1, and then the second silicon oxide film 42 is once removed with H.
Etching is performed with a solution of F: H ₂ O = 1: 5, and a thickness of 50 nm is formed again by plasma CVD (using a reaction gas composed of SiH ₄ and O ₂ ).

Next, as shown in FIG. 11C, a resist R2 is formed on the second silicon oxide film 42, and the portion of the second silicon oxide film 42 other than where the resist R2 is formed is formed.
Was etched with a solution of HF: H ₂ O = 1: 5 to obtain 10
Doping with phosphorus ions having a concentration of about ¹⁴ to 10 ¹⁵ cm ^-2 . Then, the resist R2 is changed to H ₂ SO ₄ : H ₂ O ₂ =
Peel off with a 5: 1 solution.

Then, as shown in FIG.
Amorphous silicon film 51 ′ so as to cover the silicon oxide film 42
An N-type amorphous silicon film 52 'is formed on top of the SiH ₄ , PH ₃
Is formed to a thickness of 10 nm by plasma CVD using as a reaction gas. The concentration of this N type is 10 ¹⁴ to 10 ¹⁵ cm ^-2
It is a degree.

After that, the amorphous silicon films 51 'and 52' are irradiated with laser light to dehydrogenate, crystallize, and activate the amorphous silicon films 51 'and 52', and the gate active layer 5 and the first silicon film are converted into polycrystalline silicon.
A P-type diffusion layer 5a reaching from the silicon oxide film 42 to the first silicon oxide film 41 is formed.

The laser light has, for example, a wavelength of 308 (n
m) using excimer laser light, about 250 m in air
Irradiate with J / cm ² . At this time, first, irradiation is performed with energy lower than the melting energy of the amorphous silicon films 51 ′ and 52 ′ to expel hydrogen from the thin film, and then irradiation with energy higher than the melting energy to crystallize and activate. Plan.

Next, as shown in FIG. 12B, a resist R3 is formed, a slight gap is opened in the N-type polycrystalline silicon film 52 corresponding to the gate electrode G (dry etching by CF ₄ ) and the source side is formed. The overhanging electrode SH and the drain side overhanging electrode DH are formed, and the resist R3 is set to H.
Peel off with a solution of ₂ SO ₄ : H ₂ O ₂ = 5: 1.

Then, PSG (not shown) is formed on the source-side protruding electrode SH and the drain-side protruding electrode DH.
And a protective silicon nitride film are formed by an atmospheric pressure CVD method, and hydrogenation annealing treatment is performed at 400 ° C. for about 3 to 4 hours in a forming gas to cut the silicon dangling bonds and move the field effect of electrons and holes. The leakage current is reduced.

Then, windows are formed in the PSG and the protective silicon nitride film corresponding to the source region and the drain region, and the source electrode S and the drain electrode D as shown in FIG. 1 are formed therein. The source electrode S and the drain electrode D are
Aluminum containing 1% silicon was formed to a thickness of 1000 nm by sputtering, and H ₃ PO ₄ + CH ₃ COO was formed.
Etching is performed with a mixed solution of H + HNO ₃ and aluminum sintering treatment is performed. The semiconductor device 1 according to the first embodiment is completed by such a series of processes.

Next, the manufacturing method of the second embodiment will be described with reference to the sectional views of FIGS. First, FIG. 13 (a)
As shown in, the gate electrode G (tapered), the first silicon nitride film 31, the first silicon oxide film 41, and the amorphous silicon film 51 are formed on the substrate 2 made of borosilicate glass as in the first embodiment. ', The second silicon oxide film 42 is continuously formed.

Next, a resist R1 as shown in FIG. 13B is formed on the second silicon oxide film 42, and the resist R is formed.
The portion of the second silicon oxide film 42 other than 1 is HF: H ₂ O.
Etching with a solution of 1: 5. After that, phosphorus ions are doped (10 ¹⁴ to 10 ¹⁵ cm ⁻² ), and the resist R
1 was peeled off with a solution of H ₂ SO ₄ : H ₂ O ₂ = 5: 1.

Then, as shown in FIG. 13C, laser light is irradiated to dehydrogenate, crystallize, and activate the amorphous silicon film 51 ′, and the gate active layer 5 made into polycrystalline silicon is formed. To form. The laser light has a wavelength of 3
Irradiation with about 250 mJ / cm ^{2 is} performed in air using 08 (nm) excimer laser light. At this time, first, irradiation is performed with energy lower than the melting energy of the amorphous silicon film 51 'to expel hydrogen from the thin film, and then irradiation is performed with energy higher than the melting energy for crystallization and activation.

Next, after forming a resist R2 as shown in FIG. 14A, a slight gap is opened in the second silicon oxide film 42 corresponding to the gate electrode G (HF: H ₂ O =
Etching with a 1: 5 solution), and boron ions are doped into the gate active layer 5 through the gap (10 ¹² to 10 10).
¹³ cm ^-2 ).

After that, the resist R2 is changed to H ₂ SO ₄ : H ₂
After stripping with a solution of O ₂ = 5: 1 and once etching the entire surface of the second silicon oxide film 42 with a solution of HF: H ₂ O = 1: 5, as shown in FIG. CV
D (using a reaction gas consisting of SiH ₄ and O ₂ ) is formed to a thickness of 50 nm.

Next, as shown in FIG. 14C, an N-type amorphous silicon film 52 ′ is covered by plasma CVD so as to cover an unnecessary portion of the second silicon oxide film 42 in an etched state. Form. The N-type amorphous silicon film 52 ′ uses SiH ₄ and PH ₃ as reaction gases,
It is formed to a thickness of 10 nm. The concentration of this N type is 1
It is about 0 ¹⁴ to 10 ¹⁵ cm ^-2 .

[0056] Figure 15 to form a resist R3 as shown in (a), (dry etching with CF ₄₎ opened a slight clearance to the N-type amorphous silicon film 52 'corresponding to the gate electrode G, the source-side The overhanging electrode SH and the drain side overhanging electrode DH are formed, and the resist R3 is set to H ₂ SO.
Stripping is performed with a solution of ₄ : H ₂ O ₂ = 5: 1.

Then, as shown in FIG.
RTA (Rapid Therm) at 00 ° C for about 10 seconds
Al Anneal) to form a P type diffusion layer 5a in the gate active layer 5. By this RTA, the diffusion layer 5a
Is formed in a slight depth of the gate active layer 5 on the second silicon oxide film 42 side.

After that, PS (not shown) is formed on the source-side protruding electrode SH and the drain-side protruding electrode DH.
G and a protective silicon nitride film are formed by an atmospheric pressure CVD method, and hydrogenation annealing treatment is performed in a forming gas at 400 ° C. for about 3 to 4 hours to cut the silicon dangling bond, and the electric field effect of electrons and holes. Improve mobility and reduce leakage current.

Then, windows are formed in the PSG and the protective silicon nitride film corresponding to the source region and the drain region, and the source electrode S and the drain electrode D as shown in FIG. 2 are formed there. The source electrode S and the drain electrode D are
Aluminum containing 1% silicon was formed to a thickness of 1000 nm by sputtering, and H ₃ PO ₄ + CH ₃ COO was formed.
Etching is performed with a mixed solution of H + HNO ₃ and aluminum sintering treatment is performed. The semiconductor device 1 according to the second embodiment is completed by such a series of processes.

Next, the manufacturing method of the third embodiment will be described with reference to the sectional views of FIGS. First, FIG. 16 (a)
As shown in, the gate electrode G (tapered), the first silicon nitride film 31, the first silicon oxide film 41, and the amorphous silicon film 51 are formed on the substrate 2 made of borosilicate glass as in the first embodiment. ', The second silicon oxide film 42 is continuously formed.

Next, a resist R1 as shown in FIG. 16 (b) is formed on the second silicon oxide film 42, and the resist R1 is formed.
The portion of the second silicon oxide film 42 other than 1 is HF: H ₂ O.
= Etching with a solution of 1: 5, 10 ¹⁴ to 10 ¹⁵ cm
Doping with a phosphorus ion concentration of about ^-2 . Then, the resist R1 is peeled off with a solution of H ₂ SO ₄ : H ₂ O ₂ = 5: 1.

Then, as shown in FIG. 16C, the second
An N-type amorphous silicon film 52 ′ is formed by plasma CVD so as to cover the silicon oxide film 42. The N-type amorphous silicon film 52 'is formed to a thickness of 10 nm by using SiH ₄ and PH ₃ as reaction gases. Further, the concentration of this N type is about 10 ¹⁴ to 10 ¹⁵ cm ⁻² .

After that, a resist R2 as shown in FIG. 17A is formed, and a slight gap is opened in the N-type amorphous silicon film 52 'and the second silicon oxide film 42 corresponding to the gate electrode G, The source-side protruding electrode SH and the drain-side protruding electrode DH are formed. Then, in this state, boron ion doping is performed (10 ¹² to 10 ¹³ c
m ^-2 ), P-type diffusion layer 5a is formed.

After forming the P type diffusion layer 5a, the resist R2 is stripped with a solution of H ₂ SO ₄ : H ₂ O ₂ = 5: 1. Next, as shown in FIG. 17B, laser light is irradiated to dehydrogenate, crystallize, and activate the amorphous silicon film 51 ′ and the N-type amorphous silicon film 52 ′. A gate active layer 5 and an N-type polycrystalline silicon film 52 which are made into crystalline silicon are formed. As the laser light, for example, excimer laser light having a wavelength of 308 (nm) is used, and irradiation is performed in the air at about 250 mJ / cm ² . At this time, first, irradiation is performed with energy lower than the melting energy of the amorphous silicon film 51 'and N-type amorphous silicon film 52' so as to expel hydrogen from the thin film, and then irradiation with energy higher than the melting energy. For crystallization and activation.

By this laser light irradiation, the P-type diffusion layer 5a reaching the first silicon oxide film 42 of the gate active layer 5 to the first silicon oxide film 41 of the gate active layer 5 is formed.

Then, PSG (not shown) is formed on the source-side protruding electrode SH and the drain-side protruding electrode DH.
And a protective silicon nitride film are formed by an atmospheric pressure CVD method, and hydrogenation annealing treatment is performed at 400 ° C. for about 3 to 4 hours in a forming gas to cut the silicon dangling bonds and move the field effect of electrons and holes. The leakage current is reduced.

Then, a window is opened in the PSG and the protective silicon nitride film corresponding to the source region and the drain region, and the source electrode S and the drain electrode D as shown in FIG. 3 are formed therein. The source electrode S and the drain electrode D are
Aluminum containing 1% silicon was formed to a thickness of 1000 nm by sputtering, and H ₃ PO ₄ + CH ₃ COO was formed.
Etching is performed with a mixed solution of H + HNO ₃ and aluminum sintering treatment is performed. The semiconductor device 1 according to the third embodiment is completed by such a series of processes.

Next, the manufacturing method of the fourth embodiment will be described with reference to the sectional views of FIGS. First, FIG. 18 (a)
As shown in, the gate electrode G (tapered), the first silicon nitride film 31, the first silicon oxide film 41, and the amorphous silicon film 51 are formed on the substrate 2 made of borosilicate glass as in the first embodiment. ', The second silicon oxide film 42 is continuously formed.

Next, a resist R1 as shown in FIG. 18B is formed on the second silicon oxide film 42, and the resist R
The portion of the second silicon oxide film 42 other than 1 is HF: H ₂ O.
= Etching with a solution of 1: 5, 10 ¹⁴ to 10 ¹⁵ cm
Doping with a phosphorus ion concentration of about ^-2 . Then, the resist R1 is peeled off with a solution of H ₂ SO ₄ : H ₂ O ₂ = 5: 1.

Then, as shown in FIG. 18C, the second
The amorphous silicon film 5 is covered with the silicon oxide film 42.
Plasma CVD of N-type amorphous silicon film 52 'on 1'
Formed by The N-type amorphous silicon film 52 ′ is S
iH_Four, PH_ThreeIs used as a reaction gas, 10 nm thick type
To achieve. The concentration of this N type is 10¹⁴-10 ^Fifteen
cm^-2It is a degree.

The N-type amorphous silicon film 52 'is then formed.
The amorphous silicon film 51 ′ is irradiated with laser light from above.
Then, dehydrogenation, crystallization and activation of the N-type amorphous silicon film 52 'are performed to form the gate active layer 5 and the N-type polycrystalline silicon film 52 which are made into polycrystalline silicon. As the laser light, for example, excimer laser light having a wavelength of 308 (nm) is used, and irradiation is performed in the air at about 250 mJ / cm ² . At this time, first, irradiation is performed with energy lower than the melting energy of the amorphous silicon film 51 'and N-type amorphous silicon film 52' so as to expel hydrogen from the thin film, and then irradiation with energy higher than the melting energy. For crystallization and activation.

Next, after forming a resist R2 as shown in FIG. 19A, a slight gap is opened in the N-type polycrystalline silicon film 52 and the second silicon oxide film 42 corresponding to the gate electrode G ( Etching is performed with a solution of HF: H ₂ O = 1: 5), and boron ions are doped into the gate active layer 5 through the gap (10 ¹² to 10 ¹³ cm ⁻² ).

After that, the resist R2 is changed to H ₂ SO ₄ : H ₂
Peeling was performed with a solution of O ₂ = 5: 1, and as shown in FIG. 15B, RTA (Rapid) at 1000 ° C. for about 10 seconds was used.
Thermal Annealing) to form a P-type diffusion layer 5a in the gate active layer 5. With this RTA,
The diffusion layer 5a is the second silicon oxide film 42 of the gate active layer 5.
It is in a state of being formed only at a slight depth on the side.

After that, PS (not shown) is placed on the source-side protruding electrode SH and the drain-side protruding electrode DH.
G and a protective silicon nitride film are formed by an atmospheric pressure CVD method, and hydrogenation annealing treatment is performed in a forming gas at 400 ° C. for about 3 to 4 hours to cut the silicon dangling bond, and the electric field effect of electrons and holes. Improve mobility and reduce leakage current.

Then, a window is formed in the PSG and the protective silicon nitride film corresponding to the source region and the drain region, and the source electrode S and the drain electrode D as shown in FIG. 4 are formed there. The source electrode S and the drain electrode D are
Aluminum containing 1% silicon was formed to a thickness of 1000 nm by sputtering, and H ₃ PO ₄ + CH ₃ COO was formed.
Etching is performed with a mixed solution of H + HNO ₃ and aluminum sintering treatment is performed. The semiconductor device 1 according to the fourth embodiment is completed by such a series of processes.

In the above manufacturing method, XeC is mainly used.
An example of a method of manufacturing the semiconductor device 1 by low temperature annealing with a laser has been shown. However, when the semiconductor device 1 is manufactured by high temperature annealing, a quartz glass substrate is used as the substrate 2 and Mo / Ta is used as the gate electrode G. N instead of alloy
⁺ Polycrystalline silicon may be used.

Further, in the present embodiment of the semiconductor device 1 described above, the example in which the second silicon oxide film 42 is used as the second insulating layer has been described, but not only the silicon oxide film but also the silicon oxide film / silicon oxynitride film. Alternatively, a multilayer film such as a silicon oxide film / a silicon oxynitride film / a silicon nitride film or a silicon oxide film / a silicon nitride film may be used.

[0078]

As described above, the semiconductor device of the present invention has the following effects. That is, in a semiconductor device including a thin film transistor, a current also flows at the interface of the insulating layer on the side opposite to the gate electrode centering on the gate active layer. It becomes possible to pass an electric current.

Further, due to the source voltage and the drain voltage by the source-side protruding electrode and the drain-side protruding electrode, the insulating layer interface on the side opposite to the gate electrode is always LDD.
The structure plays a role equivalent to that of the structure, the electric field between the source-gate and the drain-gate is relaxed, and a large breakdown voltage can be obtained, and a large drain current can be passed.

Further, the gate active layer corresponding to the distance between the tip of the protruding portion of the source-side protruding electrode and the tip of the protruding portion of the drain-side protruding electrode is provided with a diffusion layer having a conductivity type opposite to that of the channel. By doing so, it becomes possible to positively reduce the leak current in the gap between the source-side protruding electrode and the drain-side protruding electrode.

Further, the LDD regions provided on the source region side and the drain region side of the gate active layer can alleviate the electric field applied to the gate active layer and increase the drain breakdown voltage.

[Brief description of drawings]

FIG. 1 is a schematic sectional view illustrating a semiconductor device according to a first embodiment.

FIG. 2 is a schematic sectional view illustrating a semiconductor device according to a second embodiment.

FIG. 3 is a schematic sectional view illustrating a semiconductor device according to a third embodiment.

FIG. 4 is a schematic sectional view illustrating a semiconductor device according to a fourth embodiment.

FIG. 5 is a schematic sectional view illustrating a semiconductor device according to a fifth embodiment.

FIG. 6 is a schematic sectional view illustrating a semiconductor device according to a sixth embodiment.

FIG. 7 is a schematic sectional view illustrating a semiconductor device according to a seventh embodiment.

FIG. 8 is a schematic sectional view illustrating a semiconductor device according to an eighth embodiment.

FIG. 9 is a schematic sectional view illustrating a semiconductor device according to a ninth embodiment.

FIG. 10 is a schematic sectional view illustrating a semiconductor device according to a tenth embodiment.

FIG. 11 is a cross-sectional view (1) for explaining the manufacturing method according to the first embodiment.

FIG. 12 is a cross-sectional view (2) illustrating the manufacturing method according to the first embodiment.

FIG. 13 is a cross-sectional view (1) for explaining the manufacturing method of the second embodiment.

FIG. 14 is a cross-sectional view (2) for explaining the manufacturing method of the second embodiment.

FIG. 15 is a cross-sectional view (3) illustrating the manufacturing method according to the second embodiment.

FIG. 16 is a cross-sectional view (1) for explaining the manufacturing method according to the third embodiment.

FIG. 17 is a cross-sectional view (2) explaining the manufacturing method according to the third embodiment.

FIG. 18 is a sectional view (1) for explaining the manufacturing method according to the fourth embodiment.

FIG. 19 is a cross-sectional view (2) for explaining the manufacturing method according to the fourth embodiment.

[Explanation of symbols]

1 semiconductor device 2 substrate 5 gate active layer
21 Silicon Substrate 31 First Silicon Oxide Film 32 Second Silicon Oxide Film 41 First Silicon Nitride Film 42 Second Silicon Nitride Film 51 Amorphous Silicon Film D Drain Electrode G
Gate electrode S Source electrode

Claims (6)

[Claims] 1. A semiconductor device comprising a thin film transistor, a source region provided on one side in the width direction of the gate active layer, a drain region provided on the other side in the length direction of the gate active layer, and the gate active layer. A gate electrode provided on one side in the thickness direction with a first insulating layer interposed between the gate electrode and the gate electrode, the protruding portion extending toward the gate electrode side in a state of being electrically connected to the source region, and the protruding portion is in the thickness direction of the gate active layer. And a source-side projecting electrode provided on the other side of the gate insulating layer via a second insulating layer, and projecting toward the gate electrode in a state of being electrically connected to the drain region, and the projecting portion is the other side in the thickness direction of the gate active layer. On the side with the second insulating layer interposed therebetween, and the tip of the projecting portion and the projecting electrode on the source side are projected. And the drain-side protruding electrodes predetermined gap is provided between the minute tip, provided on the gate active layer corresponding to the gap between the drain-side protruding electrode and the source-side protruding electrode,
A semiconductor device comprising: a diffusion layer having a conductivity type opposite to that of the channel of the gate active layer. 2. The semiconductor device according to claim 1, wherein the diffusion layer is formed from one end to the other end in the thickness direction of the gate active layer. 3. The semiconductor device according to claim 1, wherein the diffusion layer is formed from an end on the other side in the thickness direction of the gate active layer to a central portion of the gate active layer. 4. A semiconductor device comprising a thin film transistor, comprising: a source region provided on one side in the length direction of the gate active layer; a drain region provided on the other side in the length direction of the gate active layer; A gate electrode provided on one side in the thickness direction of the layer with a first insulating layer interposed, and a gate electrode that projects in a state of being electrically connected to the source region, and the projecting portion is the thickness of the gate active layer. The source side projecting electrode provided on the other side in the direction through the second insulating layer, and projecting to the gate electrode side in a state of being electrically connected to the drain region, and the projecting portion in the thickness direction of the gate active layer. The second insulating layer is provided on the other side, and the tip of the protruding portion and the source-side protruding electrode are protruded. A drain side projecting electrode provided at a predetermined distance from the tip of the portion, and LDD regions provided on the source region side and the drain region side of the gate active layer, respectively. Semiconductor device. 5. The semiconductor device according to claim 4, wherein the LDD region is provided outside each portion of the gate active layer corresponding to the gate electrode. 6. The semiconductor device according to claim 4, wherein each of the LDD regions is provided outside from a position slightly entering an end of a portion of the gate active layer corresponding to the gate electrode. .