JPH09321236A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof, enabling the adaptation to the voltage reduction, low power consumption and elimination of power for holding data during waiting by reducing the leak current between a drain region connected to a capacitor and semiconductor substrate to improve the retention characteristic of DRAM. SOLUTION: The semiconductor device comprises a single crystal Si layer 14a selectively epitaxially grown in active regions surrounded with an element isolating insulation film 12 on a Si substrate 10, a silicon oxide film 36 formed by implanting O ions between the Si layer 14a and Si substrate 10, and drain regions 16b which are formed on the surface of the Si layer 14a, connected to store electrodes 26 of capacitors, and adjoined to the insulation film 12 at the ends and to the silicon oxide film 36 at the lower ends.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a DRAM (Dynamic Random Acceleration).
ess Memory) and its manufacturing method.

[0002]

2. Description of the Related Art L is the current element isolation method for DRAMs.
The OCOS (Local Oxidation of Silicon) method is the mainstream. D produced using the conventional LOCOS method
The RAM will be described with reference to FIG. Here, in FIG.
FIG. 3 is a cross-sectional view showing a DRAM memory cell for bits.

A LOCOS oxide film 52 having a thickness of 200 to 600 nm is formed on a silicon substrate 50 as a semiconductor substrate. On the surface of the silicon substrate 50 in the active region separated by the LOCOS oxide film 52, N
A source region 54a and a drain region 54b formed of a P-type or P-type impurity diffusion layer are formed opposite to each other. A gate electrode 58 is formed on the channel region sandwiched by the source region 54a and the drain region 54b with a gate oxide film 56 interposed therebetween. Thus, a MOS (Metal-Oxide-Semiconductor) transistor is formed in the active region.

An interlayer insulating film 60 is deposited on the entire surface, and the storage electrode 6 connected to the drain region 54b via a contact hole opened in the interlayer insulating film 24.
2 is formed. Further, on the storage electrode 62,
A plate electrode 66 is formed via the capacitor insulating film 64. Thus, a capacitor connected to the drain region 16b of the MOS transistor is formed.

Next, the LOCO for separating the active region
The formation of the S oxide film 52 will be described with reference to FIG. First, the surface of the silicon substrate 50 is thermally oxidized to form a silicon oxide film 68 having a thickness of 5 to 70 nm on the silicon substrate 50, and then, for example, CVD (Chemical Vapor Dep) is used.
osition) method, a thickness of 5 is formed on the silicon oxide film 68.
A silicon nitride film 70 of 0 to 300 nm is deposited. Then, after applying a resist on the silicon nitride film 70, the resist is patterned into a shape of an active region by using a lithography technique.

Next, RIE (Reactive) using the resist patterned in the shape of the active region as a mask
The silicon nitride film 70 is selectively etched by Ion Etching (reactive ion etching) to pattern the active region.

Then, after removing the resist, LOCOS oxidation is performed using the silicon nitride film 70 patterned in the shape of the active region as a mask to form a LOCOS oxide film 52 having a thickness of 200 to 600 nm in the element isolation region.

[0008]

However, in the DRAM manufactured by using the conventional LOCOS method described above, a leak current I flowing from the drain region 54b to the silicon substrate 50 is generated. And this leakage current I is
As shown by the arrows in FIG. 24, each leak current component Ia, Ib, Ic flowing in three directions is formed. That is, Ia
Is a leak current component flowing in the gate direction. The leak current component Ia includes a subthreshold leak current that flows when the gate voltage is equal to or lower than the threshold voltage and the surface is in the weak inversion state. I
b is a leak current component flowing from the bottom of the drain region 54b to the silicon substrate 50. Ic is a leak current component flowing in the element isolation region direction.

Thus, the leakage current components Ia, Ib, I
The generation of the leak current I consisting of c causes the DRA
The retention characteristic of M deteriorates. Therefore, it may not be possible to operate at a low voltage, or the refresh cycle may not be lengthened, and power consumption may not be reduced. Therefore, there has been a problem that it will be an obstacle to the promotion of lower voltage and lower power consumption of DRAM in the future.

The leak current I consisting of the leak current components Ia, Ib, Ic is turned off by the DRAM.
If this is set to, the data will be lost. Therefore, a power supply for retaining data even when not in use has been indispensable for the DRAM. Therefore, there is a problem that the leak current I must be reduced in order to retain the DRAM data even when the power is turned off.

Further, the conventional LOC described above is used for manufacturing a DRAM.
The use of the OS method itself has the following problems. For example, as shown in FIG. 25A, LOCOS oxidation is performed using the silicon nitride film 70 patterned in the shape of the active region as a mask to form the element isolation region with a thickness of 2.
When the LOCOS oxide film 52 having a thickness of 0 to 600 nm is formed, a bird's beak 72 having a length L1 is generated at the end of the LOCOS oxide film 52. Since the bird's beak 72 reduces the active area, it becomes difficult to control the line width of the active area.
There is a problem that the miniaturization of the above is hindered.

Further, as shown in FIG.
When the width of the OS oxide film 52 is reduced to miniaturize the DRAM, the space L2 between the silicon nitride films 70 used as a mask is narrowed. However, in this case, the amount of oxygen diffusing into the silicon substrate 50 through the narrow space L2 between the silicon nitride films 70 becomes small, and the LOCOS oxide film 52 is wider than the normal LOCOS oxide film 52. A sufficient thickness D of the LOCOS oxide film 52 cannot be obtained at a portion where the width of the film 52 is narrowed. Therefore, there is a problem that the element isolation characteristics are deteriorated and the transistors adjacent to each other may be short-circuited.

Further, as shown in FIG.
During the OS oxidation, stress may occur between the silicon substrate 50 and the LOCOS oxide film 52, and a crystal defect 74 may occur in the silicon substrate 50 in contact with the LOCOS oxide film 52. The crystal defect 74 causes a leak current I,
In particular, since the leak current component Ic increases, there is a problem that it causes deterioration of the retention characteristic in the DRAM.

Further, in order to obtain good element isolation characteristics, it is necessary to increase the thickness of the LOCOS oxide film 52.
As the thickness of the LOCOS oxide film 52 increases, the LOCOS increases.
The oxide film 52 rises above the surface of the silicon substrate 51, and the flatness is deteriorated. Therefore, there is also a problem that a process margin is deteriorated during processing such as resist patterning and etching in a later step.

Therefore, the present invention has been made in view of the above problems, and reduces the leakage current between the drain region connected to the capacitor and the semiconductor substrate to improve the retention characteristic of the DRAM, thereby reducing the It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can cope with a reduction in voltage and power consumption and can eliminate a power supply for holding data during standby.

[0016]

The above object is achieved by the following method of manufacturing a semiconductor device according to the present invention. That is, the semiconductor device according to claim 1 is a semiconductor substrate, an element isolation insulating film formed in an element isolation region on the semiconductor substrate, and an active element on the semiconductor substrate surrounded by the element isolation insulating film. A single crystal silicon layer selectively formed in a region, a source region and a drain region formed opposite to the surface of the single crystal silicon layer, and a channel region sandwiched between the source region and the drain region. A gate electrode formed via a gate insulating film, and a storage electrode connected to the drain region via a contact hole opened in the interlayer insulating film deposited on the entire surface,
A plate electrode formed on the storage electrode via a capacitor insulating film.

As described above, in the semiconductor device according to the first aspect, the element isolation insulating film is formed in the element isolation region on the semiconductor substrate, and the active region on the semiconductor substrate surrounded by the element isolation insulating film is formed. Since the single crystal silicon layer is selectively formed, the problem of element isolation using the conventional LOCOS method can be solved. That is, L
Since bird's beaks generated in OCOS oxidation do not reduce the active region, the active region and the element isolation region can be formed in a desired pattern, and the line width control of the active region becomes easy.
The miniaturization of semiconductor devices can be promoted.

Since the width and thickness of the element isolation insulating film can be controlled arbitrarily, even if the width of the element isolation insulating film is reduced in order to miniaturize the semiconductor device, L
Unlike the OCOS oxide film, the thickness of the element isolation insulating film does not decrease, a desired thickness can be secured, and good element isolation characteristics can be obtained even in a fine element isolation region. it can.

Further, since the single crystal silicon layer is selectively formed on the semiconductor substrate, the stress generated during the LOCOS oxidation does not cause crystal defects, and the leakage current caused by the crystal defects is not generated. It will not increase. Therefore, finer and better element isolation characteristics can be obtained than element isolation using the conventional LOCOS method.
Leakage current flowing out from the drain region connected to the storage electrode is reduced to improve the retention characteristics, which makes it possible to reduce the voltage and power consumption of the semiconductor device and also to hold data during standby. Allows you to reduce the power supply.

Further, in the semiconductor device according to claim 1, an insulating film is formed between the single crystal silicon layer and the semiconductor substrate, and the single crystal silicon layer is formed by the insulating film and the element isolation insulating film. Can be insulated and separated into islands. By adopting such a configuration, a so-called SOI (Silicon On I) in which a single crystal silicon layer forming an element is insulated and isolated on its side surface and bottom surface in an island shape by an element isolation insulating film and an insulating film.
Since it has an nsulator structure, the element isolation characteristics can be further improved as compared with the semiconductor device according to the first aspect.

Further, in the semiconductor device according to the first aspect, the end of the drain region on the side opposite to the channel side may be in contact with the element isolation insulating film. Since the end of the drain region on the side opposite to the channel side is in contact with the element isolation insulating film in this way, the leak current flowing out from the drain region connected to the storage electrode is a leak current component flowing in the gate direction ( Sub-threshold leak current) and the leak current component flowing in the semiconductor substrate direction from the bottom of the drain region, and the leak current component flowing in the element isolation region direction disappears.
The overall leakage current can be reduced. The retention characteristic is improved due to the decrease in the leak current, so that the operation at a low voltage becomes possible. Further, since the refresh cycle can be lengthened, low power consumption can be achieved. Therefore, lowering the voltage of the semiconductor device,
It is possible to promote low power consumption. In addition, since the retention characteristic improves, the data can be retained even when the power is turned off. Therefore, it is possible to reduce the number of power sources for holding data in the standby state, which has been required until now.
It can also be used as a non-volatile memory such as a flash memory.

In the above semiconductor device, the end of the drain region opposite to the channel side is in contact with the insulating film for element isolation, and the lower end of the drain region is in contact with the insulating film. It can be configured. In this way, the end of the drain region opposite to the channel side is in contact with the element isolation insulating film, and the lower end of the drain region is in contact with the insulating film, so that the drain region connected to the storage electrode is connected. The leak current flowing out from is limited to the leak current component (including subthreshold leak current) flowing in the gate direction, and the leak current component flowing in the semiconductor substrate direction from the bottom of the drain region and the leak current component flowing in the element isolation region direction. Since it is eliminated, the leak current can be further reduced as compared with the semiconductor device according to the third aspect. Therefore, due to this decrease in leakage current,
Since the retention characteristic of the DRAM is further improved and the refresh cycle can be further lengthened, D
It is possible to further reduce the voltage and power consumption of the RAM. Further, since the effect of reducing the leak current is greater than that of the semiconductor device according to the third aspect, the retention characteristic is further improved to reduce the power supply for holding data in the standby state and the nonvolatile memory such as the flash memory. It is even more likely to use it as a static memory.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
A first step of forming an element isolation insulating film in an element isolation region on a semiconductor substrate, and a single crystal silicon layer selectively in an active region on the semiconductor substrate surrounded by the element isolation insulating film. A second step of epitaxial growth, a source region and a drain region are formed opposite to each other on the surface of the single crystal silicon layer, and a gate insulating film is provided on the channel region sandwiched between the source region and the drain region. And a third step of forming a gate electrode.

As described above, in the method of manufacturing the semiconductor device according to the fifth aspect, the element isolation insulating film is formed in the element isolation region on the semiconductor substrate, and the element isolation insulating film surrounds the semiconductor substrate. Since the single crystal silicon layer is selectively epitaxially grown in the active region, the problem of element isolation using the conventional LOCOS method can be solved. That is, since the active region is not reduced by the bird's beak generated in the LOCOS oxidation, the active region and the element isolation region can be formed in a desired pattern, and the line width control of the active region is facilitated, and the semiconductor device Can be further miniaturized.

Further, since the width and thickness of the element isolation insulating film can be controlled arbitrarily, even if the width of the element isolation insulating film is reduced in order to miniaturize the semiconductor device, L
Unlike the OCOS oxide film, the thickness of the element isolation insulating film does not decrease, a desired thickness can be secured, and good element isolation characteristics can be obtained even in a fine element isolation region. it can. In addition, since the single crystal silicon layer is selectively formed on the semiconductor substrate, the crystal defects are not generated by the stress generated during the LOCOS oxidation, and the leak current caused by the crystal defects is increased. Nor. Furthermore, the thicknesses of the element isolation insulating film and the single crystal silicon layer can be controlled arbitrarily, and it is extremely easy to make the thicknesses of the two substantially equal.
It is possible to prevent the flatness from being deteriorated by rising from the surface of the semiconductor substrate as in the case of COS oxidation, and to obtain good flatness without a step between the element isolation insulating film and the single crystal silicon layer. it can.

Further, in the method of manufacturing a semiconductor device according to claim 5, a storage electrode is formed on the drain region through a contact hole opened in an interlayer insulating film, and then a capacitor insulation is formed on the storage electrode. The configuration may include a fourth step of forming a plate electrode via a film. With such a configuration, the conventional L
Since finer and better element isolation characteristics can be obtained as compared with the element isolation using the OCOS method, the leakage current flowing out from the drain region connected to the storage electrode is reduced, the retention characteristic is improved, and the low semiconductor device It is possible to promote voltage reduction and low power consumption, and it is possible to reduce the power supply for holding data during standby.

Further, in the above-described method for manufacturing a semiconductor device, an insulating film is formed on the bottom surface of the single crystal silicon layer, and the single crystal silicon layer is insulated and separated into islands by the insulating film and the element isolation insulating film. It can be configured to include a step of performing. By adopting such a configuration, the single crystal silicon layer forming the element forms an SOI structure in which the side surface and the bottom surface are insulated and isolated in an island shape by the insulating film for element isolation and the insulating film. The characteristics can be improved.

Further, in the present invention, in the above-described method for manufacturing a semiconductor device, the step of insulatingly isolating the single crystal silicon layer in an island shape by the insulating film and the insulating film for element isolation is the single crystal silicon layer. Can be a step of forming an oxide film by implanting oxygen ions into the bottom surface portion or the interface portion between the single crystal silicon layer and the semiconductor substrate. In this manner, by implanting oxygen ions into the bottom surface portion of the single crystal silicon layer or the interface portion between the single crystal silicon layer and the semiconductor substrate to form an oxide film, the single crystal silicon layer forming the element has its side surface and bottom surface covered. It is possible to easily form the SOI structure in which the element isolation insulating film and the insulating film are insulated and isolated in an island shape.

Further, in the present invention, in the above-mentioned method for manufacturing a semiconductor device, the step of insulatingly isolating the single crystal silicon layer in an island shape by the insulating film and the element isolation insulating film is applied to the back surface of the semiconductor substrate. After removing a part of the semiconductor substrate, the element isolation insulating film and the single crystal silicon layer by polishing or etching from the above, an insulating substrate having an insulating film formed on the surface is separately prepared, and the element isolation insulating film is prepared. A step of adhering a bottom surface of the film and the single crystal silicon layer to a surface of the insulating film can be performed. Single crystal silicon for forming an element by adhering the element isolation insulating film and the bottom surface of the single crystal silicon layer having a predetermined thickness by polishing or etching to the insulating film surface of an insulating substrate prepared separately. It is possible to easily form the SOI structure in which the side surface and the bottom surface of the layer are insulated and separated into island shapes by the element isolation insulating film and the insulating film.

In the present invention, in the above-mentioned method for manufacturing a semiconductor device, the first step is to oxidize the surface of the semiconductor substrate to form an oxide film on the semiconductor substrate.
Forming a resist patterned in the shape of an element isolation region on the oxide film, etching the oxide film using the resist as a mask, and forming the oxide film in the element isolation region on the semiconductor substrate I can do it.
After the oxide film is formed on the semiconductor substrate by the thermal oxidation as described above, the oxide film is patterned into the shape of the element isolation region by using the lithography technique to form the element isolation insulating film. Since the element isolation region can be formed in the semiconductor device, the line width of the active region surrounded by the element isolation region can be easily controlled, and the miniaturization of the semiconductor device can be promoted. Further, the width and thickness of the element isolation insulating film can be controlled arbitrarily, and even if the width of the element isolation insulating film is reduced in order to miniaturize the semiconductor device, Since the thickness does not decrease and a desired thickness can be secured, good element isolation characteristics can be obtained even in a fine element isolation region.

Further, in the present invention, in the above-described method for manufacturing a semiconductor device, in the first step, an insulating film is deposited on the entire surface of the semiconductor substrate and patterned on the insulating film in the shape of an element isolation region. After forming the resist, the insulating film may be etched using the resist as a mask to form the insulating film in the element isolation region on the semiconductor substrate. After depositing an insulating film on the entire surface of the semiconductor substrate as described above, the insulating film is patterned into a shape of an element isolation region by using a lithography technique to form an element isolation insulating film. Since the element isolation region can be formed,
It becomes easy to control the line width of the active region surrounded by the element isolation region, and the semiconductor device can be miniaturized.
Further, the width and thickness of the element isolation insulating film can be controlled arbitrarily, and even if the width of the element isolation insulating film is reduced in order to miniaturize the semiconductor device, Since the thickness does not decrease and a desired thickness can be secured, good element isolation characteristics can be obtained even in a fine element isolation region.

Further, in the present invention, in the above-described method for manufacturing a semiconductor device, the third step comprises forming a gate electrode on the single crystal silicon layer via a gate insulating film, and then forming the gate electrode. And impurity ions are implanted into the surface of the single crystal silicon layer by using the element isolation insulating film as a mask to form a source region and a drain region opposite to each other on the surface of the single crystal silicon layer, and a channel side of the drain region. The step may be such that the end portion on the opposite side is in contact with the insulating film for element isolation. Thus, the source region and the drain region are formed on the surface of the single crystal silicon layer by the impurity ion implantation using the gate electrode and the element isolation insulating film as a mask, and the end of the drain region opposite to the channel side is the element isolation insulating layer. In order to be in contact with the film, the leak current flowing out from the drain region is limited to the leak current component flowing in the gate direction (including the subthreshold leak current) and the leak current component flowing in the semiconductor substrate direction from the bottom of the drain region. Since there is no leak current component flowing in the element isolation region direction, the leak current can be reduced.

Further, in the present invention, in the above method for manufacturing a semiconductor device, in the third step, after forming a gate electrode on the single crystal silicon layer via a gate insulating film, the gate electrode is formed. And impurity ions are implanted into the surface of the single crystal silicon layer by using the element isolation insulating film as a mask to form a source region and a drain region opposite to each other on the surface of the single crystal silicon layer, and a channel side of the drain region. The step may be such that an end portion on the side opposite to is in contact with the insulating film for element isolation, and a lower end of the drain region is in contact with the insulating film. Thus, the source region and the drain region are formed on the surface of the single crystal silicon layer by the impurity ion implantation using the gate electrode and the element isolation insulating film as a mask, and the end of the drain region opposite to the channel side is the element isolation insulating layer. The leak current flowing out from the drain region is limited to the leak current component (including the subthreshold leak current) flowing in the gate direction in order to contact the film and the lower end of the drain region to contact the insulating film. Since the leak current component flowing from the bottom of the drain region toward the semiconductor substrate and the leak current component flowing toward the element isolation region are eliminated, the leak current can be further reduced.

[0034]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
An embodiment of the present invention will be described. (First Embodiment) A DRAM according to a first embodiment of the present invention will be described with reference to FIGS. here,
FIG. 1 is a sectional view showing a DRAM according to this embodiment, and FIG.
FIG. 2 is an enlarged view of a 1-bit memory cell of the DRAM of FIG. In a device isolation region on a silicon substrate 10 as a semiconductor substrate, a device isolation insulating film 12 made of a silicon oxide film or a silicon nitride film having a thickness of 100 to 1700 nm is formed. In the active region on the silicon substrate 10 surrounded by the element isolation insulating film 12, a single crystal silicon layer 14 having a thickness almost equal to that of the element isolation insulating film 12 is formed.
Are selectively formed.

On the surface of the single crystal silicon layer 14, the source region 1 made of an N type or P type impurity diffusion layer is formed.
6a and drain region 16b are formed opposite to each other. Although not shown, the source region 16a and the drain region 16b each have an LDD (Lightly Doped Drain-Source) structure composed of a high concentration impurity region and a low concentration impurity region on the channel side thereof. . The end of the drain region 16b opposite to the channel side is in contact with the element isolation insulating film 12.

In addition, the source region 16a and the drain region 1
On the channel region sandwiched by 6b, for example, a thickness of 5 to
Through the gate oxide film 18 of 30 nm, for example, a thickness of 50
~ 400nm polycrystalline silicon layer or polycide
A gate electrode 20 composed of a cide) layer is formed. Further, a sidewall 22 made of, for example, a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode 20. In this manner, in the active region, the gate is formed on the source region 16a and the drain region 16b formed facing the surface of the single crystal silicon layer 14 and the channel region sandwiched between the source region 16a and the drain region 16b. A MOS transistor including a gate electrode 20 formed via the oxide film 18 is formed.

An interlayer insulating film 24 is deposited on the entire surface, and the storage electrode 2 connected to the drain region 16b through a contact hole opened in the interlayer insulating film 24.
6 are formed. Further, on the storage electrode 26,
A plate electrode 30 is formed via the capacitor insulating film 28. Thus, a capacitor composed of the storage electrode 26 and the plate electrode 30 with the capacitor insulating film 28 sandwiched therebetween is formed so as to be connected to the drain region 16b of the MOS transistor. Furthermore, the interlayer insulating film 24
Through the contact hole opened in the source region 16a
A bit line 32 connected to the. However, since the bit line 32 is originally invisible in the cross section shown in FIG. 1, it is shown by a broken line in FIG. Thus, the MOS transistor formed in the active region, the capacitor connected to the drain region 16b of this MOS transistor, and the source region 16a of the MOS transistor.
A DRAM is composed of the bit line 32 connected to the gate line 20 and the gate electrode 20 used as a word line.

Next, a method of manufacturing the DRAM shown in FIG.
This will be described with reference to FIGS. 3 to 8. Here, FIGS.
3A and 3B are process cross-sectional views for explaining a method of manufacturing the DRAM of FIG. For example, using a thermal oxidation method, a thickness of 100 to 1700 is formed on a silicon substrate 10 as a semiconductor substrate.
After the silicon oxide film 12a having a thickness of 10 nm is formed, a resist 34 is applied on the silicon oxide film 12a. Then, the resist 34 is patterned into the shape of the element isolation region by using a lithography technique (see FIG. 3).

Next, RIE (Reacti) using the resist 34 patterned in the shape of the element isolation region as a mask.
The silicon oxide film 12a is selectively etched by ve Ion etching (reactive ion etching) to form an element isolation insulating film 12 made of a silicon oxide film. Then, the resist 34 is peeled off (see FIG. 4). In the steps shown in FIGS. 3 and 4, the silicon oxide film 12a is formed using a thermal oxidation method, and the silicon oxide film 12a is patterned into the shape of the element isolation region to form the element isolation insulating film 12. However, instead of this, a silicon oxide film or a silicon nitride film is formed on the silicon substrate 10 by using, for example, the CVD method, and the CVD oxide film or the CVD nitride film is patterned into the shape of the element isolation region to perform element isolation. The insulating film 12 may be formed.

Then, a selective epitaxial growth method is used to form a single crystal silicon layer having a thickness substantially equal to that of the element isolation insulating film 12 on the exposed silicon substrate 10 in the active region surrounded by the element isolation insulating film 12. 14 is selectively epitaxially grown (see FIG. 5). Here, the thickness of the single crystal silicon layer 14 is set to the insulating film 1 for element isolation.
The thickness of the single crystal silicon layer 14 and the device isolation insulating film 12 is made flat so that the thickness of the single crystal silicon layer 14 and the element isolation insulating film 12 are good, and processing such as resist patterning and etching in subsequent steps is facilitated. This is because.

Regarding the conditions for the selective epitaxial growth of the single crystal silicon layer 14, see H. Hada, et al., “A.
Self-Aligned Contact Technology Using Anisotropica
l Selective Epitaxial Silicon For Giga-Bit DRAMs ",
IEEE, IEDM, p.665, (1995) was referred to. This document describes the case of selectively epitaxially growing a single crystal silicon layer only in the contact portion.
It can also be applied to the case of the present embodiment.

Further, if necessary, a predetermined impurity is ion-implanted to adjust the surface concentration of the single crystal silicon layer 14 in the active region, or a predetermined impurity is formed to form a P-well or an N-well. It is also possible to perform ion implantation of impurities.

Then, the gate oxide film 1 having a thickness of, for example, 5 to 30 nm is formed on the single crystal silicon layer 14 by using a thermal oxidation method.
8 is formed. Then, a polycrystalline silicon layer or a polycide layer having a thickness of 50 to 400 nm is formed on the gate oxide film 18, and then patterned into a predetermined shape to form the gate electrode 20 made of the polycrystalline silicon layer or the polycide layer. Are formed (see FIG. 6).

Next, using the gate electrode 20 and the element isolation insulating film 12 as a mask, N-type or P-type impurities are introduced into the surface of the single crystal silicon layer 14 to form low-concentration impurity regions opposite to each other. Subsequently, after forming a sidewall 22 made of, for example, a silicon oxide film or a silicon nitride film on the side surface of the gate electrode 20, the gate electrode 20, the sidewall 22 and the element isolation insulating film 12 are used as a mask.
Again, N-type or P-type impurities are introduced into the surface of the single crystal silicon layer 14 to form high-concentration impurity regions facing each other. Thus, the source region 16a and the drain region 16b of the LDD structure composed of the high-concentration impurity region and the low-concentration impurity region on the channel side thereof are formed opposite to each other. At this time,
When the source region 16a and the drain region 16b are formed, impurities are introduced using the element isolation insulating film 12 as a mask. Therefore, the end of the drain region 16b opposite to the channel side is formed on the element isolation insulating film 12. I will come into contact with you.

In this way, in the active region, the source region 16a and the drain region 16b formed facing the surface of the single crystal silicon layer 14 and the channel region sandwiched between the source region 16a and the drain region 16b are formed. Then, a MOS transistor composed of the gate electrode 20 formed through the gate oxide film 18 is formed (see FIG. 7).

Next, an interlayer insulating film 24 is deposited on the entire surface. Then, after forming a contact hole in the interlayer insulating film 24 on the drain region 16b, the storage electrode 26 connected to the drain region 16b through the contact hole is formed. Subsequently, a plate electrode 30 is formed on the storage electrode 26 with a capacitor insulating film 28 interposed therebetween. In this way, a capacitor composed of the storage electrode 26 and the plate electrode 30 with the capacitor insulating film 28 sandwiched therebetween is formed by connecting to the drain region 16b of the MOS transistor. At the same time, after forming a contact hole in the interlayer insulating film 24 on the source region 16a, the bit line 32 connected to the source region 16a through the contact hole is formed.

Thus, the MOS transistor formed in the active region, the capacitor connected to the drain region 16b of this MOS transistor, and the bit line 32 connected to the source region 16a of the MOS transistor.
And the gate electrode 20 used as a word line are manufactured (see FIG. 8).

As described above, according to the DRAM of this embodiment, the end of the drain region 16b of the MOS transistor formed in the active region on the side opposite to the channel side is in contact with the element isolation insulating film 12. As shown by the arrow in FIG. 2, the leak current I flowing out from the drain region 16b connected to the storage electrode 26 is a leak current component Ia (including a subthreshold leak current) flowing in the gate direction and the drain region 16b. It is limited to the leak current component Ib flowing from the bottom toward the silicon substrate 10, and the leak current component Ic flowing toward the element isolation region disappears.
That is, the total leak current I can be reduced.

Due to the reduction of the leak current I, the DRAM
Since the retention characteristic of is improved, it is possible to operate at a low voltage. Further, since the refresh cycle can be lengthened, low power consumption can be achieved. Therefore, lower voltage and lower power consumption of the DRAM can be promoted.

By increasing the effect of reducing the leak current I and improving the retention characteristic,
Since the data can be held even when the power is turned off, it is possible to reduce the power supply for holding the data in the standby, which has been necessary until now. It can also be used as a non-volatile memory such as a flash memory.

Further, according to the method of manufacturing a DRAM of the present embodiment, after the element isolation insulating film 12 is formed in the element isolation region on the silicon substrate 10, the element isolation insulating film 12 is surrounded by the element isolation insulating film 12. In order to insulate and separate the single crystal silicon layer 14 forming an element by selectively epitaxially growing the single crystal silicon layer 14 having the same thickness as the element isolation insulating film 12 on the exposed silicon substrate 10 in the active region. The problem of element isolation using the conventional LOCOS method can be solved. That is, LO
Since the active region is not reduced by bird's beak generated in COS oxidation, the active region and the element isolation region can be formed in a desired pattern, and the line width of the active region can be easily controlled.
The miniaturization of RAM can be promoted.

Further, since the width and thickness of the element isolation insulating film 12 can be controlled arbitrarily, even if the width of the element isolation insulating film 12 is reduced in order to further miniaturize the DRAM, the LOCOS is reduced. Unlike the oxide film, the thickness of the element isolation insulating film 12 does not decrease, a desired thickness can be secured, and good element isolation characteristics can be obtained even in a fine element isolation region. it can.

Further, in the single crystal silicon layer 14 formed by selective epitaxial growth on the silicon substrate 10, crystal defects are not generated by the stress generated during LOCOS oxidation. Since there is no increase in the leak current that occurs, the retention characteristic in the DRAM can be improved.

Furthermore, since the thicknesses of the element isolation insulating film 12 and the single crystal silicon layer 14 can be respectively controlled arbitrarily, and it is extremely easy to make the thicknesses substantially equal to each other, the LOCOS oxidation is performed. In this case, it is possible to prevent the flatness from being deteriorated by rising from the surface of the silicon substrate as in the case of 1), and to form a step between the single crystal silicon layer 14 in the active region and the isolation insulating film 12 in the isolation region. It is possible to obtain good flatness. Therefore,
It is possible to facilitate processing such as resist patterning and etching in the subsequent steps.

(Second Embodiment) A DRAM according to a second embodiment of the present invention will be described with reference to FIGS. 9 and 10. Here, FIG. 9 is a cross-sectional view showing the DRAM according to the present embodiment, and FIG. 10 is an enlarged view of a 1-bit memory cell of the DRAM of FIG. The same elements as those of the DRAM according to the first embodiment shown in FIGS. 1 and 2 are designated by the same reference numerals and the description thereof will be omitted.

In a device isolation region on a silicon substrate 10 as a semiconductor substrate, a device isolation insulating film 1 made of a silicon oxide film or a silicon nitride film having a thickness of 100 to 1700 nm.
2 is formed. In the active region on the silicon substrate 10 surrounded by the element isolation insulating film 12, the single crystal silicon layer 14a having a thickness of 50 to 900 nm is selectively formed via the silicon oxide film 36 having a thickness of 50 to 800 nm. Has been done. That is, the side surface and the bottom surface of the single crystal silicon layer 14a in the active region are the element isolation insulating film 1
2 and the silicon oxide film 36 have an SOI structure that is insulated and isolated in an island shape.

Further, on the surface of the single crystal silicon layer 14a, the source region 16a and the drain region 1 of the LDD structure are formed.
6b are formed to face each other. And drain region 1
The end of 6b on the side opposite to the channel side is in contact with the element isolation insulating film 12, and the lower end of the drain region 16b is in contact with the silicon oxide film 36.
Further, on the channel region sandwiched between the source region 16a and the drain region 16b, for example, a gate oxide film 18 having a thickness of 5 to 30 nm is interposed, for example, a thickness of 50 to 400 nm.
Gate electrode 20 is formed. A sidewall 22 is formed on the side surface of the gate electrode 20.

In this way, in the active region, the source region 16a and the drain region 16b formed facing the surface of the single crystal silicon layer 14a, and the channel region sandwiched between the source region 16a and the drain region 16b. A MOS transistor composed of a gate electrode 20 formed via a gate oxide film 18 is formed thereon.

In addition, the drain region 16b is formed through the contact hole opened in the interlayer insulating film 24 deposited on the entire surface.
A storage electrode 26 connected to is formed. A plate electrode 30 is formed on the storage electrode 26 via a capacitor insulating film 28. Thus, the storage electrode 26 and the plate electrode 3 with the capacitor insulating film 28 interposed therebetween are provided.
A capacitor composed of 0 and 0 is formed so as to be connected to the drain region 16b of the MOS transistor. Further, a bit line 32 connected to the source region 16a via a contact hole opened in the interlayer insulating film 24 is formed.

Thus, the MOS transistor formed in the active region, the capacitor connected to the drain region 16b of this MOS transistor, and the MOS
A DRAM is composed of the bit line 32 connected to the source region 16a of the transistor and the gate electrode 20 used as a word line.

Next, a method of manufacturing the DRAM shown in FIG.
This will be described with reference to FIGS. Here, FIG. 11 to FIG. 15 are process cross-sectional views for explaining a method of manufacturing the DRAM of FIG. Similar to the steps shown in FIGS. 3 to 5, the silicon substrate 10 as a semiconductor substrate is used.
After forming an element isolation insulating film 12 having a thickness of 100 to 1700 nm in the upper element isolation region, a selective epitaxial growth method is used to form an active region on the silicon substrate 10 surrounded by the element isolation insulating film 12. , A single crystal silicon layer 14 having a thickness substantially equal to that of the element isolation insulating film 12 is selectively epitaxially grown (see FIG. 11).

Next, oxygen (O) is ion-implanted at a depth of 50 to 900 nm from the surface of the single crystal silicon layer 14 by using an ion implantation method, and then heat treatment is performed.
Bottom surface of single crystal silicon layer 14 or single crystal silicon layer 1
4 to the interface between the silicon substrate 10 and the thickness of 50 to 800 n
m silicon oxide film 36 is formed. Due to the formation of the silicon oxide film 36, the single crystal silicon layer 14 has a thickness of 5
It becomes the single crystal silicon layer 14a of 0 to 900 nm. In this way, the single crystal silicon layer 14a is formed into an SOI structure in which the side surface and the bottom surface are insulated and separated into island shapes by the element isolation insulating film 12 and the silicon oxide film 36 (see FIG. 12).

Next, after forming a gate oxide film 18 having a thickness of 5 to 30 nm on the single crystal silicon layer 14a, for example, a thickness of 50 to 400 nm is formed on the gate oxide film 18.
The gate electrode 20 is formed of the polycrystalline silicon layer or the polycide layer (see FIG. 13).

Then, using the gate electrode 20 and the element isolation insulating film 12 as a mask, the single crystal silicon layer 14a is formed.
Impurities are introduced into the surface to form low-concentration impurity regions oppositely to each other, and subsequently, a sidewall 22 made of, for example, a silicon oxide film or a silicon nitride film is formed on a side surface of the gate electrode 20. Using the element isolation insulating film 12 as a mask, impurities are again introduced into the surface of the single crystal silicon layer 14a, and the single crystal silicon layer 1
A high-concentration impurity region reaching the silicon oxide film 36 on the bottom surface of 4a is formed oppositely. Thus, the source region 16a and the drain region 16b having the LDD structure are formed opposite to each other.
Therefore, the end of the drain region 16b on the side opposite to the channel side is in contact with the element isolation insulating film 12, and the lower end of the drain region 16b is in contact with the silicon oxide film 36.

In this way, the single crystal silicon layer 14a is formed.
It is composed of a source region 16a and a drain region 16b formed opposite to the surface, and a gate electrode 20 formed on a channel region sandwiched between the source region 16a and the drain region 16b with a gate oxide film 18 interposed therebetween. Forming a MOS transistor (see FIG. 14).

Next, after depositing the interlayer insulating film 24 on the entire surface, a contact hole is opened in the interlayer insulating film 24 on the drain region 16b, and the storage electrode 26 connected to the drain region 16b through this contact hole is formed. . Subsequently, the plate electrode 30 is formed on the storage electrode 26 with the capacitor insulating film 28 interposed therebetween. In this way,
A capacitor composed of the storage electrode 26 and the plate electrode 30 sandwiching the capacitor insulating film 28 therebetween is formed so as to be connected to the drain region 16b of the MOS transistor. At the same time, after forming a contact hole in the interlayer insulating film 24 on the source region 16a, the bit line 32 connected to the source region 16a through the contact hole is formed.

Thus, the MOS transistor formed in the active region, the capacitor connected to the drain region 16b of this MOS transistor, and the bit line 32 connected to the source region 16a of the MOS transistor.
And the gate electrode 20 used as a word line are manufactured (see FIG. 15).

In the method of manufacturing the DRAM according to the present embodiment, as shown in FIG. 12, the single crystal silicon layer 14 is selected in the active region surrounded by the element isolation insulating film 12 on the silicon substrate 10. After the step of epitaxially growing epitaxially, MO is formed on the single crystal silicon layer 14a.
Before the step of forming the S transistor, oxygen ions are implanted from the surface of the single crystal silicon layer 14 to form a silicon oxide film 36 on the bottom surface of the single crystal silicon layer 14 or on the interface between the single crystal silicon layer 14 and the silicon substrate 10. Has formed,
The process of forming the silicon oxide film 36 by implanting oxygen ions is not limited to this stage.
That is, it may be during or after the step of forming the MOS transistor, as long as it is after the step of selectively epitaxially growing the single crystal silicon layer 14. However, when the gate electrode 20 is formed, the gate electrode 20
Oxygen ion implantation is suppressed by this, and the position and thickness of the silicon oxide film 36 formed below the gate electrode 20 may change.

As described above, according to the DRAM of this embodiment, the end of the drain region 16b of the MOS transistor formed in the active region on the side opposite to the channel side is in contact with the element isolation insulating film 12. Moreover, since the lower end of the drain region 16b is in contact with the silicon oxide film 36, the leakage current I flowing out from the drain region 16b connected to the storage electrode 26 is indicated by the arrow in FIG.
Is limited to the leak current component Ia (including subthreshold leak current) flowing in the gate direction, and the leak current component Ib flowing in the silicon substrate 10 direction from the bottom of the drain region 16b and the leak current component Ic flowing in the element isolation region direction. Disappear. That is, the leak current I can be further reduced as compared with the DRAM according to the first embodiment. Due to the decrease in the leak current I, the retention characteristic of the DRAM is further improved and the refresh cycle can be further lengthened, so that the lower voltage and lower power consumption of the DRAM can be further promoted. Also,
Since the effect of reducing the leak current I is larger than that of the DRAM according to the first embodiment, further improvement of the retention characteristic can reduce the power supply for holding data in the standby mode and can reduce the power consumption in the flash memory. The feasibility of using it as a non-volatile memory becomes even higher.

Further, according to the method of manufacturing the DRAM of the present embodiment, after the element isolation insulating film 12 is formed in the element isolation region on the silicon substrate 10, the element isolation insulating film 12 is surrounded by the element isolation insulating film 12. A single crystal silicon layer 14 having a thickness substantially equal to that of the isolation insulating film 12 is selectively epitaxially grown on the exposed silicon substrate 10 in the active region, and then oxygen ions are implanted from the surface of the single crystal silicon layer 14. By forming a silicon oxide film 36 on the bottom surface of the single crystal silicon layer 14 or on the interface between the single crystal silicon layer 14 and the silicon substrate 10, the single crystal silicon layer 14a forming an element has its side surface and bottom surface for element isolation. Since the SOI structure in which the insulating film 12 and the silicon oxide film 36 are insulated and separated into islands is formed, it is the same as in the case of the first embodiment. A, it is possible to solve the problem of isolation using a conventional LOCOS method, it is possible to further improve the isolation characteristics than in the case of the first embodiment.

(Third Embodiment) A DRAM according to a third embodiment of the present invention will be described with reference to FIGS. Here, FIG. 16 shows a DRAM according to the present embodiment.
17 is an enlarged view of a 1-bit memory cell of the DRAM of FIG. In addition, FIG. 9 and FIG.
The same elements as those of the DRAM according to the second embodiment shown in FIG.

A thickness of 50 to 800 is formed on the silicon substrate 38.
A silicon oxide film 40 having a thickness of 10 nm is formed to serve as an insulating substrate. And the silicon oxide film 40 of this insulating substrate
In the upper element isolation region, an element isolation insulating film 1 made of a silicon oxide film or a silicon nitride film having a thickness of 50 to 900 nm.
2 is formed. In the active region on the silicon oxide film 40 surrounded by the element isolation insulating film 12,
A single crystal silicon layer 14b having a thickness substantially equal to that of the element isolation insulating film 12 is selectively formed. That is, the single crystal silicon layer 14b in the active region has an SOI structure in which the side surface and the bottom surface are insulated and isolated in an island shape by the element isolation insulating film 12 and the silicon oxide film 40.

On the surface of the single crystal silicon layer 14b, the source region 16a and the drain region 1 having the LDD structure are formed.
6b are formed to face each other. And drain region 1
An end of 6b opposite to the channel side is in contact with the element isolation insulating film 12, and a lower end of the drain region 16b is in contact with the silicon oxide film 40. Further, on the channel region sandwiched between the source region 16a and the drain region 16b, for example, the gate oxide film 18 having a thickness of 5 to 30 nm.
Through the gate electrode 2 having a thickness of 50 to 400 nm, for example.
0 is formed. Also, on the side surface of the gate electrode 20,
The sidewall 22 is formed.

In this way, the single crystal silicon layer 14b is formed.
It is composed of a source region 16a and a drain region 16b formed opposite to the surface, and a gate electrode 20 formed on a channel region sandwiched between the source region 16a and the drain region 16b with a gate oxide film 18 interposed therebetween. MOS transistor is formed.

In addition, the drain region 16b is formed through the contact hole opened in the interlayer insulating film 24 deposited on the entire surface.
A storage electrode 26 connected to the storage electrode 26 is formed.
A plate electrode 30 is formed on the capacitor 6 via the capacitor insulating film 28. Thus, the capacitor insulating film 28
A capacitor composed of a storage electrode 26 and a plate electrode 30 sandwiching the capacitor is formed so as to be connected to the drain region 16b of the MOS transistor. Further, a bit line 32 connected to the source region 16a via a contact hole opened in the interlayer insulating film 24 is formed.

In this way, the MOS transistor formed in the active region, the capacitor connected to the drain region 16b of this MOS transistor, and the MOS
A DRAM is composed of the bit line 32 connected to the source region 16a of the transistor and the gate electrode 20 used as a word line.

Next, a method of manufacturing the DRAM shown in FIG. 16 will be described with reference to FIGS. Here, FIG.
8 to 23 are process cross-sectional views for explaining the method of manufacturing the DRAM of FIG. Similar to the steps shown in FIGS. 3 to 5, a thickness of 100 to 1700 nm is formed in the element isolation region on the silicon substrate 10 as a semiconductor substrate.
After forming the element isolation insulating film 12, the selective isolation epitaxial growth method is used to form an active region on the silicon substrate 10 surrounded by the element isolation insulating film 12 with a thickness substantially equal to that of the element isolation insulating film 12. The single crystal silicon layer 14 is selectively epitaxially grown (see FIG. 18).

Next, CMP is performed from the back side of the silicon substrate 10.
(Chemical Mechanical Polishing) is performed to remove the silicon substrate 10 to expose the bottom surfaces of the element isolation insulating film 12 and the single crystal silicon layer 14, and then further to the element isolation insulating film 12 and the single crystal. Silicon layer 1
The CMP of the bottom surface of No. 4 is advanced, and the thickness of each is 50 to 90.
The device isolation insulating film 12a and the single crystal silicon layer 14b having a thickness of 0 nm are formed. Here, instead of CMP, an etching method may be used to remove the silicon substrate 10 and partially remove the bottom surfaces of the element isolation insulating film 12 and the single crystal silicon layer 14 (see FIG. 19).

Then, on a separately prepared silicon substrate 38, a thickness of 50 to 800 nm is formed by a thermal oxidation method or a CVD method.
The silicon oxide film 40 is formed as an insulating substrate.
Then, the surface of the silicon oxide film 40 on the silicon substrate 38 is bonded to the bottom surface of the element isolation insulating film 12a and the single crystal silicon layer 14b. This adhesion is possible by bringing them into close contact and applying heat (see FIG. 20).

Next, on the single crystal silicon layer 14b of the SOI structure, the side and bottom surfaces of which are insulated and isolated in an island shape by the element isolation insulating film 12a and the silicon oxide film 40,
For example, after forming the gate oxide film 18 having a thickness of 5 to 30 nm, for example, a thickness of 50 to 40 is formed on the gate oxide film 18.
A gate electrode 20 composed of a 0 nm polycrystalline silicon layer or a polycide layer is formed (see FIG. 21).

Then, using the gate electrode 20 and the element isolation insulating film 12a as a mask, the single crystal silicon layer 14 is formed.
b. Impurities are introduced to the surface b to form low-concentration impurity regions opposite to each other, and subsequently, a sidewall 22 made of, for example, a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode 20, and then the gate electrode 20 and the sidewall. By using 22 and the element isolation insulating film 12a as a mask, impurities are again introduced into the surface of the single crystal silicon layer 14b to form a high-concentration impurity region reaching the silicon oxide film 40 on the bottom surface of the single crystal silicon layer 14b. Thus, the source region 16a and the drain region 16b having the LDD structure are formed opposite to each other. Therefore, the end of the drain region 16b opposite to the channel side is in contact with the element isolation insulating film 12a, and the lower end of the drain region 16b is in contact with the silicon oxide film 40.

In this way, the single crystal silicon layer 14b is formed.
It is composed of a source region 16a and a drain region 16b formed opposite to the surface, and a gate electrode 20 formed on a channel region sandwiched between the source region 16a and the drain region 16b with a gate oxide film 18 interposed therebetween. Forming a MOS transistor (see FIG. 22).

Next, after depositing an interlayer insulating film 24 on the entire surface, a contact hole is opened in the interlayer insulating film 24 on the drain region 16b, and a storage electrode 26 connected to the drain region 16b through this contact hole is formed. . Then, a capacitor insulating film 28 is formed on the storage electrode 26.
The plate electrode 30 is formed through. In this way, the capacitor composed of the storage electrode 26 and the plate electrode 30 with the capacitor insulating film 28 sandwiched therebetween is replaced by a MOS transistor.
It is formed so as to be connected to the drain region 16b of the transistor. At the same time, the interlayer insulating film 2 on the source region 16a
4 is formed with a contact hole, and the bit line 32 is connected to the source region 16a through the contact hole.
To form

In this way, the MOS transistor formed in the active region, the capacitor connected to the drain region 16b of this MOS transistor, and the bit line 32 connected to the source region 16a of the MOS transistor.
And the gate electrode 20 used as the word line are manufactured (see FIG. 23).

In the method of manufacturing the DRAM according to the present embodiment, as shown in FIGS. 19 and 20, the single crystal silicon layer is formed in the active region on the silicon substrate 10 surrounded by the element isolation insulating film 12. After the step of selectively epitaxially growing 14
Before the step of forming a MOS transistor in 4b, the silicon substrate 10 is removed, and further, CMP is performed to polish the bottom surfaces of the element isolation insulating film 12 and the single crystal silicon layer 14,
The silicon oxide film 4 on the bottom surfaces of the polished element isolation insulating film 12a and the single crystal silicon layer 14b and the silicon substrate 38
However, the CMP and bonding steps are not limited to this stage. That is, if it is after the step of selectively epitaxially growing the single crystal silicon layer 14, it may be during or after the step of forming the MOS transistor, or during or after the step of forming the capacitor.

As described above, according to the DRAM of this embodiment, the end of the drain region 16b of the MOS transistor formed in the active region on the side opposite to the channel side is in contact with the element isolation insulating film 12. Further, since the lower end portion of the drain region 16b is in contact with the silicon oxide film 40, the leakage current I flowing out from the drain region 16b connected to the storage electrode 26 is indicated by the arrow in FIG.
Is limited to the leak current component Ia (including subthreshold leak current) flowing in the gate direction, and the leak current component Ib flowing in the silicon substrate 38 direction from the bottom of the drain region 16b and the leak current component Ic flowing in the element isolation region direction. Disappear. That is, the leak current I can be reduced similarly to the DRAM according to the second embodiment. Due to the decrease in the leak current I, the retention characteristic of the DRAM is improved, and the refresh cycle can be lengthened, so that the voltage reduction and the power consumption reduction of the DRAM can be promoted. Further, the effect of reducing the leak current I is the DRAM according to the second embodiment.
Similarly, since the retention characteristic is further improved, the feasibility of reducing the power supply for holding data at the time of standby and using it as a nonvolatile memory such as a flash memory is further enhanced.

Further, according to the method of manufacturing the DRAM of the present embodiment, the element isolation insulating film 12 is formed in the element isolation region on the silicon substrate 10, and the element isolation insulating film 1 is formed.
On the exposed silicon substrate 10 in the active region surrounded by 2, a single crystal silicon layer 14 having a thickness almost equal to that of the element isolation insulating film 12 is selectively epitaxially grown, and then the silicon substrate 10 is removed by CMP. After further forming the element isolation insulating film 12a and the single crystal silicon layer 14b having a predetermined thickness, the silicon formed on the silicon substrate 38 prepared separately from the bottom surfaces of the element isolation insulating film 12a and the single crystal silicon layer 14b. By adhering to the surface of the oxide film 40, the single crystal silicon layer 14b forming the element forms an SOI structure in which the side surface and the bottom surface are insulated and isolated in an island shape by the element isolation insulating film 12 and the silicon oxide film 40. Therefore, as in the case of the second embodiment, the problem of element isolation using the conventional LOCOS method is solved. Preparative it is, it is possible to further improve the isolation characteristics.

[0088]

As described in detail above, according to the semiconductor device of the present invention, the element isolation insulating film is formed in the element isolation region on the semiconductor substrate and surrounded by the element isolation insulating film. Since the single crystal silicon layer is selectively formed in the active region on the semiconductor substrate, the problem of element isolation using the conventional LOCOS method can be solved. That is, since the active region is not reduced by the bird's beak generated in the LOCOS oxidation, the active region and the element isolation region can be formed in a desired pattern, and the line width control of the active region is facilitated, and the semiconductor device Can be further miniaturized.

Further, since the width and thickness of the element isolation insulating film can be controlled arbitrarily, even if the width of the element isolation insulating film is reduced in order to miniaturize the semiconductor device, L
Unlike the OCOS oxide film, the thickness of the element isolation insulating film does not decrease, a desired thickness can be secured, and good element isolation characteristics can be obtained even in a fine element isolation region. it can. Furthermore, since the single crystal silicon layer is selectively formed on the semiconductor substrate, the crystal defect is not generated by the stress generated during the LOCOS oxidation, and the leak current caused by the crystal defect is increased. Nor. In this way, finer and better element isolation characteristics than element isolation using the conventional LOCOS method can be obtained, so that leakage current flowing out from the drain region connected to the storage electrode is reduced and retention characteristics are improved. Improved,
It is possible to reduce the voltage and power consumption of the semiconductor device, and it is possible to reduce the power supply for holding data during standby.

Further, the single crystal silicon layer forming the element has the SOI structure in which the side surface and the bottom surface are insulated and isolated in the island shape by the element isolation insulating film and the insulating film, so that the element isolation characteristic is further improved. Can be made. Further, since the end of the drain region opposite to the channel side is in contact with the element isolation insulating film, the leak current flowing out from the drain region connected to the storage electrode is a leak current component (subthreshold) flowing in the gate direction. (Including a leak current) and a leak current component flowing from the bottom of the drain region toward the semiconductor substrate, and there is no leak current component flowing toward the element isolation region, so that the leak current can be reduced.

Further, since the end of the drain region on the side opposite to the channel side is in contact with the element isolation insulating film and the lower end of the drain region is in contact with the insulating film, the drain connected to the storage electrode is formed. The leak current flowing from the region is limited to the leak current component (including the subthreshold leak current) flowing in the gate direction, and the leak current component flowing in the semiconductor substrate direction from the bottom of the drain region and the leak current component flowing in the element isolation region direction. Is eliminated, the leak current can be further reduced. The retention characteristic is improved due to the decrease in the leak current, so that the operation at a low voltage becomes possible. Further, since the refresh cycle can be lengthened, low power consumption can be achieved. Therefore, lower voltage and lower power consumption of the semiconductor device can be promoted. In addition, since the retention characteristic improves, the data can be retained even when the power is turned off. Therefore, it is possible to reduce the number of power sources for holding data in the standby state, which has been required until now. It can also be used as a non-volatile memory such as a flash memory.

Further, according to the method for manufacturing a semiconductor device of the present invention, the element isolation insulating film is formed in the element isolation region on the silicon substrate, and the active layer on the silicon substrate surrounded by the element isolation insulating film is formed. By selectively epitaxially growing the single crystal silicon layer in the region, the problem of element isolation using the conventional LOCOS method can be solved. That is, since the active region is not reduced by the bird's beak generated in the LOCOS oxidation, the active region and the element isolation region can be formed in a desired pattern, and the line width control of the active region is facilitated, and the semiconductor device Can be further miniaturized.

Further, since the width and thickness of the element isolation insulating film can be controlled arbitrarily, even if the width of the element isolation insulating film is reduced so as to miniaturize the semiconductor device, L
Unlike the OCOS oxide film, the thickness of the element isolation insulating film does not decrease, a desired thickness can be secured, and good element isolation characteristics can be obtained even in a fine element isolation region. it can. In addition, since the single crystal silicon layer is selectively formed on the semiconductor substrate, the crystal defects are not generated by the stress generated during the LOCOS oxidation, and the leak current caused by the crystal defects is increased. Nor. Furthermore, the thicknesses of the element isolation insulating film and the single crystal silicon layer can be controlled arbitrarily, and it is extremely easy to make the thicknesses of the two substantially equal.
It is possible to prevent the flatness from being deteriorated by rising from the surface of the silicon substrate as in the case of COS oxidation, and to obtain good flatness without a step between the element isolation insulating film and the single crystal silicon layer. it can. Further, the element isolation characteristics can be further improved by forming an SOI structure in which the side and bottom surfaces of the single crystal silicon layer forming the element are insulated and isolated by the element isolation insulating film and the insulating film. .

Further, a source region and a drain region are formed on the surface of the single crystal silicon layer by impurity ion implantation using the gate electrode and the element isolation insulating film as a mask, and the end of the drain region opposite to the channel side is the element isolation. By making contact with the insulating film for use, the leak current flowing out from the drain region is divided into a leak current component (including subthreshold leak current) flowing in the gate direction and a leak current component flowing in the semiconductor substrate direction from the bottom of the drain region. Since there is no leak current component flowing in the element isolation region direction, the leak current can be reduced.

Further, a source region and a drain region are formed on the surface of the single crystal silicon layer by impurity ion implantation using the gate electrode and the element isolation insulating film as a mask, and the end of the drain region opposite to the channel side is the element isolation. The leak current flowing out from the drain region becomes a leak current component (including a subthreshold leak current) flowing in the gate direction by contacting the insulating film for insulation and the lower end of the drain region contacting the insulating film. The leakage current component flowing from the bottom of the drain region toward the semiconductor substrate and the leakage current component flowing toward the element isolation region are eliminated, so that the leakage current can be further reduced. The retention characteristic is improved due to the decrease in the leak current, so that the operation at a low voltage becomes possible. Further, since the refresh cycle can be lengthened, low power consumption can be achieved. Therefore, lower voltage and lower power consumption of the semiconductor device can be promoted. In addition, since the retention characteristic improves, the data can be retained even when the power is turned off. Therefore, it is possible to reduce the number of power sources for holding data in the standby state, which has been required until now. It can also be used as a non-volatile memory such as a flash memory.

[Brief description of drawings]

FIG. 1 is a sectional view showing a DRAM according to a first embodiment of the present invention.

FIG. 2 is an enlarged view of a 1-bit memory cell of the DRAM of the DRAM of FIG.

3A to 3C are process cross-sectional views (No. 1) for explaining the method for manufacturing the DRAM of FIG.

FIG. 4 is a process sectional view (2) for explaining the method for manufacturing the DRAM of FIG. 1;

FIG. 5 is a process sectional view (3) for explaining the method for manufacturing the DRAM in FIG. 1;

6A to 6C are process cross-sectional views (No. 4) for explaining the method for manufacturing the DRAM of FIG.

FIG. 7 is a process sectional view (5) for explaining the method for manufacturing the DRAM of FIG. 1;

FIG. 8 is a process sectional view (6) for explaining the method for manufacturing the DRAM in FIG. 1;

FIG. 9 is a sectional view showing a DRAM according to a second embodiment of the present invention.

10 is an enlarged view of a 1-bit memory cell of the DRAM of FIG. 9;

FIG. 11 is a process sectional view (1) for explaining the method for manufacturing the DRAM of FIG. 9;

FIG. 12 is a process sectional view (2) for explaining the method for manufacturing the DRAM in FIG. 9;

FIG. 13 is a process sectional view (3) for explaining the method for manufacturing the DRAM in FIG. 9;

FIG. 14 is a process sectional view (4) for explaining the method for manufacturing the DRAM in FIG. 9;

FIG. 15 is a process sectional view (5) for explaining the method for manufacturing the DRAM of FIG. 9;

FIG. 16 is a sectional view showing a DRAM according to a third embodiment of the present invention.

17 is an enlarged view of a 1-bit memory cell of the DRAM of FIG.

FIG. 18 is a process sectional view (1) for explaining the method for manufacturing the DRAM of FIG. 16;

FIG. 19 is a process sectional view (2) for explaining the method for manufacturing the DRAM of FIG. 16;

FIG. 20 is a process sectional view (3) for explaining the method for manufacturing the DRAM of FIG. 16;

FIG. 21 is a process sectional view (4) for explaining the method for manufacturing the DRAM of FIG. 16;

FIG. 22 is a process sectional view (5) for explaining the method for manufacturing the DRAM of FIG. 16;

FIG. 23 is a process sectional view (6) for explaining the method for manufacturing the DRAM in FIG. 16;

FIG. 24 is a cross-sectional view showing a 1-bit memory cell of a conventional DRAM.

FIG. 25 is a cross-sectional view for explaining the LOCOS method.

[Explanation of symbols]

10 ... Silicon substrate, 12 ... Element isolation insulating film, 1
4, 14a, 14b ... Single crystal silicon layer, 16a.
Source region, 16b ... Drain region, 18 ... Gate oxide film, 20 ... Gate electrode, 22 ... Sidewall, 24 ... Interlayer insulating film, 26 ... Storage electrode, 28 ...
Capacitor insulating film, 30 ... Plate electrode, 32 ... Bit line, 34 ... Resist, 36 ... Silicon oxide film,
38 ... Silicon substrate, 40 ... Silicon oxide film, 50
... Silicon substrate, 52 ... LOCOS oxide film, 54a
... source region, 54b ... drain region, 56 ... gate oxide film, 58 ... gate electrode, 60 ... interlayer insulating film, 62 ... storage electrode, 64 ... capacitor insulating film, 6
6 ... Plate electrode, 68 ... Silicon oxide film, 70 ...
… Silicon nitride film, 72… Birds beak, 74… Crystal defect.

Claims (13)

[Claims] 1. A semiconductor substrate, an element isolation insulating film formed in an element isolation region on the semiconductor substrate, and an active region on the semiconductor substrate selectively surrounded by the element isolation insulating film. A gate insulating film is formed on the formed single crystal silicon layer, a source region and a drain region formed opposite to the surface of the single crystal silicon layer, and a channel region sandwiched between the source region and the drain region. A storage electrode connected to the drain region through a gate electrode formed through the contact electrode and a contact hole formed in the interlayer insulating film deposited over the entire surface, and formed over the storage electrode through a capacitor insulating film Semiconductor device having a plate electrode formed thereon. 2. The semiconductor device according to claim 1, wherein an insulating film is formed between the single crystal silicon layer and the semiconductor substrate, and the single crystal silicon layer is formed by the insulating film and the element isolation insulating film. A semiconductor device characterized by being insulated and separated in an island shape. 3. The semiconductor device according to claim 1, wherein an end of the drain region opposite to the channel side is in contact with the element isolation insulating film. 4. The semiconductor device according to claim 2, wherein an end of the drain region opposite to the channel side is in contact with the element isolation insulating film, and a lower end of the drain region is the insulating film. A semiconductor device characterized by being in contact with a film. 5. A first step of forming an element isolation insulating film in an element isolation region on a semiconductor substrate, and single crystal silicon in an active region on the semiconductor substrate surrounded by the element isolation insulating film. A second step of selectively epitaxially growing a layer, and a source region and a drain region are formed opposite to each other on the surface of the single crystal silicon layer, and on the channel region sandwiched between the source region and the drain region, And a third step of forming a gate electrode via a gate insulating film. 6. The method of manufacturing a semiconductor device according to claim 5, wherein a storage electrode is formed on the drain region via a contact hole opened in an interlayer insulating film, and then a capacitor insulating film is formed on the storage electrode. A method of manufacturing a semiconductor device, comprising a fourth step of forming a plate electrode via 7. The method for manufacturing a semiconductor device according to claim 5, wherein an insulating film is formed on a bottom surface of the single crystal silicon layer, and the single crystal silicon layer is formed by the insulating film and the element isolation insulating film. A method for manufacturing a semiconductor device, comprising the step of insulatingly separating the islands. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of insulatingly separating the single crystal silicon layer into islands by the insulating film and the element isolation insulating film is a bottom surface of the single crystal silicon layer. Method of manufacturing a semiconductor device, which comprises a step of implanting oxygen ions into an interface portion or an interface portion between the single crystal silicon layer and the semiconductor substrate to form an oxide film. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the step of insulatingly isolating the single crystal silicon layer in an island shape by the insulating film and the element isolation insulating film includes polishing the semiconductor substrate from the back surface. Alternatively, after removing a part of the semiconductor substrate and the element isolation insulating film and the single crystal silicon layer by etching, an insulating substrate having an insulating film formed on the surface is separately prepared, and the element isolation insulating film and A method of manufacturing a semiconductor device, comprising a step of adhering a bottom surface of the single crystal silicon layer and a surface of the insulating film. 10. The method of manufacturing a semiconductor device according to claim 5, wherein the first step oxidizes a surface of the semiconductor substrate to form an oxide film on the semiconductor substrate, After forming a resist patterned in the shape of the element isolation region on the oxide film,
A method of manufacturing a semiconductor device, comprising the step of etching the oxide film using the resist as a mask to form the oxide film in an element isolation region on the semiconductor substrate. 11. The method of manufacturing a semiconductor device according to claim 5, wherein in the first step, an insulating film is deposited on the entire surface of the semiconductor substrate, and an element isolation region is formed on the insulating film. A step of forming a resist patterned in the shape of, and then etching the insulating film using the resist as a mask to form the insulating film in an element isolation region on the semiconductor substrate. Production method. 12. The method of manufacturing a semiconductor device according to claim 5, wherein in the third step, a gate electrode is formed on the single crystal silicon layer via a gate insulating film, and then the gate is formed. Impurity ions are implanted into the surface of the single crystal silicon layer by using the electrodes and the insulating film for element isolation as a mask to form a source region and a drain region opposite to each other on the surface of the single crystal silicon layer, and a channel of the drain region. A method of manufacturing a semiconductor device, comprising the step of making an end portion on the side opposite to the side contact the insulating film for element isolation. 13. The method of manufacturing a semiconductor device according to claim 7, wherein in the third step, a gate electrode is formed on the single crystal silicon layer via a gate insulating film. Impurity ions are implanted into the surface of the single crystal silicon layer by using the gate electrode and the isolation insulating film as a mask to form a source region and a drain region on the surface of the single crystal silicon layer, and the drain. The end of the region opposite to the channel side is in contact with the element isolation insulating film,
A method of manufacturing a semiconductor device, which is a step of contacting a lower end of the drain region with the insulating film.