JPH09321168A - Semiconductor package and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable reliable mounting of a semiconductor device by relaxing a thermal stress acting on a junction part in mounting the semiconductor device, and realize a multi-pin structure by enabling an increase in size of the semiconductor device. SOLUTION: In this device, a semiconductor element 30 is mounted on an element mounting surface of a circuit board 10, and an external connection terminal 12, such as, a solder ball, is electrically connected to an electrode pad 14 formed on a mounting surface of the circuit board 10. In this case, an insulating buffer film layer 40 having a Young's modulus not greater than 1.0×10<4> kgf/mm<2> and a thickness not smaller than 0.05mm is applied onto the mounting surface of the circuit board 10. At a portion of the insulating buffer film layer 40 corresponding to the electrode pad 14, a through-hole 42 is provided in a penetrating manner. A continuity portion 44 made of a conductive material is formed in the through-hole 42, and the electrode pad 14 and the external connection terminal 12 are connected with each other by the continuity portion 44.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a semiconductor device capable of suitably relieving thermal stress acting on a joint between a semiconductor device and a mounting substrate during mounting.

[0002]

2. Description of the Related Art In a BGA type semiconductor device in which a ceramic substrate or a plastic substrate (resin substrate) is used as a circuit board, the number of external connection terminals for connecting the semiconductor device and a mounting board tends to increase. The circuit board on which the semiconductor element is mounted is becoming larger. But,
When the circuit board becomes large in this way, the thermal stress acting on the joint between the semiconductor device and the mounting board when the semiconductor device is mounted is caused by the difference in the thermal expansion coefficients of the mounting board and the circuit board. However, the size of the joint becomes large and the joint is damaged.

FIG. 9 shows a conventional structure of a joint portion in which a solder ball is joined as an external connection terminal 12 to a ceramic circuit board 10. Reference numeral 14 is a terminal pad formed on the ceramic circuit board 10 by a conventionally known metallizing method or the like, and the solder balls of the external connection terminals 12 are bonded to the terminal pads 14 via the low melting point solder 16. In such a joining method, the thermal stress caused by the difference in thermal expansion coefficient between the ceramic circuit board 10 and the mounting board is mainly due to the low melting point solder 1
6 acts on the solder joint, and the solder joint is damaged by thermal fatigue.

As a method of preventing the problem that the solder joint portion is damaged by the thermal stress as described above, as shown in FIG. 10, the solder joint portion 18 is formed so as to be embedded in the ceramic circuit board 10, and the solder joint portion is formed. There is a configuration in which the external connection terminal 12 is joined to the portion 18. The solder joint portion 18 is formed by forming a solder filling hole 20 in a portion of the ceramic circuit board 10 where the terminal pad 14 is formed and filling the hole 20 with solder.

As described above, in the structure in which the solder joint portion 18 is provided in the ceramic circuit board 10 and the external connection terminals 12 are joined, the solder joint portion which is weak against distortion is reinforced and held by the high-strength ceramic circuit board 10. Therefore, the strength of the entire bonded portion can be improved, which makes it possible to provide a semiconductor device having high durability against thermal fatigue.

[0006]

In order to avoid the thermal stress generated at the joint between the semiconductor device and the mounting substrate due to the difference in the thermal expansion coefficient between the semiconductor device and the mounting substrate when the semiconductor device is mounted, Unless a method of reinforcing the joint is adopted, it is a measure to limit the size of the package (circuit board) on which the semiconductor element is mounted so that excessive thermal stress does not act. However, if the size of the package is limited, it becomes difficult to increase the number of pins, and the application as a semiconductor device is limited.

The above-described method of forming the solder joint portion 18 in the ceramic circuit board 10 solves the problem of thermal stress acting on the joint portion by receiving thermal stress at a portion having high strength and less likely to be damaged. This makes it possible to increase the size of the package. On the other hand, the present invention seeks to mitigate the thermal stress acting on the joint between the semiconductor device and the mounting substrate, thereby avoiding the problem of thermal stress acting on the joint. The problem of thermal stress acting on the joint when the semiconductor device is mounted on the mounting board is not limited to the semiconductor device using the ceramic circuit board as described above, and is also applicable to the semiconductor device using the plastic circuit board and the like. It is also a problem.

The present invention alleviates the thermal stress acting on the joint between the semiconductor device and the mounting board when the semiconductor device is mounted on the mounting board as described above, and causes a problem such as damage or peeling of the joint. It is an object of the present invention to provide a semiconductor package and a semiconductor device that can reliably hold the bonded portion without causing the connection and that can be used as a product with high connection reliability.

[0009]

The present invention achieves the above object.
In order to do so, the following configuration is provided. That is, the semiconductor package
Solder on the circuit board on which the semiconductor element is mounted.
If the external connection terminals such as balls are electrically connected,
The terminal pad provided is provided, and the terminal pad is provided
On the outer surface of the circuit board, Young's modulus 1.0 × 10 ^Fourkgf / mm^Two
Below, an insulating layer with a thickness of 0.05 mm or more
An edge buffer layer is deposited and the terminal pad of the insulating buffer layer is formed.
It is characterized in that a through-hole is transparently provided at a portion corresponding to
You. In addition, a metal layer is adhered to the inner wall surface of the through hole.
Also reduces the thermal stress that acts on the joint.
can do. Further, as the insulating buffer layer, glass is used.
Fiber-containing BT (Bismaleimide Triazine) Resin
Is preferably used. In addition, the insulating buffer layer is made of a different material.
It is also possible to form multiple layers by using materials to relieve thermal stress.
It is suitable above. Also, as an insulating buffer layer, epoxy resin
Oil, BT resin, polyimide resin, polyimide siloxane
Resin, polyester resin, silicone rubber, polyurethane
Organic materials selected from tongue resin can be used
You.

Further, as a semiconductor device, a semiconductor element is mounted on an element mounting surface of a circuit board of the semiconductor package, and a conductive portion formed by filling a conductive material in the through hole is formed, and the terminal is formed by the conductive portion. The pad and the external connection terminal are electrically connected. Further, a semiconductor element is mounted on the element mounting surface of the circuit board of the semiconductor package, and a conducting portion formed by filling a conductive material in the through hole is formed, and the conducting portion is connected to the terminal pad, The external connection terminal is formed in a bump shape integrally with the conductive portion so as to project from the surface of the insulating buffer layer.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 1 shows a first semiconductor device according to the present invention.
It is sectional drawing which shows the embodiment. In the semiconductor device of this embodiment, a semiconductor element 30 is mounted on a circuit board 10 (semiconductor package) obtained by laminating ceramic green sheets such as alumina or aluminum nitride in multiple layers and firing them.
A solder ball as the external connection terminal 12 is joined to the connection surface (mounting surface) with the mounting substrate. Semiconductor element 3
0 is die-attached to the bottom surface of the cavity recess 32, is electrically connected to the wiring pattern 34 by the wire bonding method, and is sealed by the cap 36.

The wiring pattern 34 is formed inside the circuit board 10 by a conventionally known method.
It is electrically connected to the terminal pad 14 formed on the mounting surface of the circuit board 10 via a and the via 34b. Terminal pad 14
Are arranged in an array at predetermined intervals.

Reference numeral 40 denotes an insulating buffer layer which is adhered to the surface of the circuit board 10 on which the terminal pads 14 are formed. In the semiconductor device of this embodiment, the insulating buffer layer 40 is interposed between the terminal pad 14 and the external connection terminal 12, and the terminal pad 14 is provided.
And the external connection terminal 12 are electrically connected. The insulating buffer layer 40 is provided for the purpose of relieving thermal stress acting on the external connection terminals 12 or the terminal pads 14 when the semiconductor device is mounted on a mounting board made of a ceramic or resin substrate. Therefore, the insulating buffer layer 40 is made of a material having a predetermined flexibility to ensure a predetermined thickness.

The electrical connection between the terminal pad 14 and the external connection terminal 12 is made through the conducting portion 44 provided in the insulating buffer layer 40. The conductive portion 44 is formed by filling a through hole 42 provided in the insulating buffer layer 40 corresponding to each terminal pad 14 with a conductive material such as solder. The conductive portion 44 is formed after the semiconductor element 30 is mounted on the circuit board 10 because it is heated by die attachment when the semiconductor element 30 is mounted on the circuit board 10. The conductive portion 44 may be formed in advance before mounting the semiconductor element 30 using high melting point solder or the like.

The terminal pad 14 is connected to the conductive portion 44 at the inner bottom surface of the through hole 42, and the external connection terminal 12 such as a solder ball is joined to the outer surface of the conductive portion 44. In this way, a semiconductor device in which the terminal pad 14 and the external connection terminal 12 are electrically connected and the semiconductor element 30 and the external connection terminal 12 are electrically connected is obtained.

The semiconductor device of this embodiment is characterized in that the terminal pad 14 formed on the mounting surface of the circuit board 10 is not directly joined to the external connection terminal 12 such as a solder ball, but is provided with a conductive portion 44. The buffer layer 40 is disposed between the terminal pad 14 and the external connection terminal 12, and the conductive portion 44 is provided.
The terminal pad 14 and the external connection terminal 12 are connected via the.

The insulating buffer layer 40 functions to relax the stress by mounting the semiconductor device on a mounting substrate and deforming the insulating buffer layer 40 when an external force such as a thermal stress acts on the joint. That is, in the semiconductor device according to the present embodiment, the insulating buffer layer 40 holds the joint portion, and at the same time, the insulating buffer layer 40 is deformed when stress acts on the joint portion to slightly displace the joint portion. It prevents the stress from directly acting on. In this way, it is possible to prevent the joint portion from being damaged by thermal stress or the like generated when the semiconductor device is mounted.

(Second Embodiment) Although the first embodiment described above is a cavity-up type semiconductor device, the insulating buffer layer 40 is formed on the surface of the circuit board 10 on which the terminal pads 14 are formed.
The semiconductor device having the same can be similarly applied to a cavity-down type product as shown in FIG. In the case of the embodiment shown in FIG. 2 also, by providing the insulating buffer layer 40, it is possible to effectively relieve the thermal stress that acts on the bonding portion when the semiconductor device is mounted. A potting resin 38 seals the semiconductor element 30. Further, as another embodiment of the cavity-down type, the present invention can be similarly applied to a semiconductor device with a heat dissipation plate, which is provided by penetrating an element mounting hole in the circuit board 10 and a heat dissipation plate is joined to the outer surface of the element mounting portion.

(Third Embodiment) FIG. 3 shows a third semiconductor device.
An embodiment is shown. In this embodiment, the two insulating buffer layers 40 are provided.
b, 40c. In this way, the effect of forming the insulating buffer layer with a plurality of layers is that by combining the insulating buffer layers formed of different materials,
The point is that the thermal stress acting on the joint as a whole can be effectively suppressed.

For example, the thermal expansion coefficient of the insulating buffer layer 40b on the side in contact with the circuit board 10 is set to a value close to the thermal expansion coefficient of the circuit board 10, and the thermal expansion coefficient of the insulating buffer layer 40c on the outer surface side is the thermal expansion of the mounting board. By setting the value close to the coefficient,
Circuit board 1 compared to the case where only one insulating buffer layer is provided
It is possible to reduce the difference in the coefficient of thermal expansion between 0 and the insulating buffer layer 40b and the difference in the coefficient of thermal expansion between the insulating buffer layer 40c and the mounting substrate, and to reduce the thermal stress acting on the joint as a whole. It can be suitably mitigated.

When the insulating buffer layer 40 is adhered to the circuit board 10, the substrate may warp due to the difference in thermal expansion coefficient between the substrate and the insulating buffer layer 40. However, as described above, a plurality of insulating buffer layers are provided. The method of forming the insulating buffer layer with a layer so that the coefficient of thermal expansion of the insulating buffer layer has an inclination is effective from the viewpoint that the warp of the substrate can be preferably prevented. Further, by forming the insulating buffer layer 40 in a plurality of layers, it is possible to match the thermal expansion coefficients of the semiconductor device and the mounting substrate without making the entire insulating buffer layer 40 thicker than necessary.

(Fourth Embodiment) FIG. 4 shows a fourth semiconductor device.
An embodiment is shown. The present embodiment is characterized in that the metal layer 46 is formed on the inner wall surface of the through hole 42 provided in the insulating buffer layer 40 formed on the circuit board 10. In the through holes 42 provided in the insulating buffer layer 40 in each of the above-described embodiments, except for the terminal pads 14 exposed on the inner bottom surface, the inner wall surface of the through holes 42 and the conductive material such as solder have no wettability, and the conductive portion 44 is Join only on the inner bottom surface. In this embodiment, a metal layer 46 is provided on the inner wall surface of the through hole 42 so that the entire inner wall surface of the through hole 42 and the conductive material such as solder are wet and bonded.

FIG. 5 shows an enlarged view of the portion to which the external connection terminal 12 is joined. The terminal pad 14 is located on the inner bottom surface of the through hole 42, and the metal layer 46 is formed on the inner wall surface of the through hole 42.
The conducting portion 44 is joined to and supported by the entire inner surface of the through hole 42. In the embodiment, the metal layer 46 a is formed by edging the edge of the opening of the through hole 42.
When the external connection terminal 12 such as a solder ball is joined, a is provided for the purpose of ensuring the wettability at the edge of the conductive portion 44 and ensuring that the external connection terminal 12 is joined.

As described above, the insulating buffer layer 40 is provided on the surface of the circuit board 10 on which the terminal pads 14 are formed, and the external connection terminals 12 are bonded to alleviate external force such as thermal stress acting on the bonded portions. The method is not limited to the semiconductor device using the ceramic circuit board as in the above embodiment, but can be similarly applied to the semiconductor device using a plastic circuit board, a glass circuit board, a silicon circuit board, or the like. By adopting such a configuration, it is possible to improve the reliability of the connection portion when the semiconductor device is mounted on the mounting board, it is possible to increase the size of the semiconductor package, and to increase the number of pins. It becomes possible to respond appropriately.

The external connection terminals 12 to be joined to the substrate are not limited to solder balls, but may be, for example, metal spheres made of copper, nickel, or the like, the outer surfaces of which are solder-plated, and lead pins for surface mounting or insertion. Etc. can be used. Further, instead of providing the external connection terminal 12 as a separate body from the conducting portion 44, the conducting portion 44 of the low melting point solder provided in the insulating buffer layer 40 is projected outward from the opening portion of the through hole 42 in a bump shape and externally connected. It can also be a terminal.

[0026]

【Example】

Example 1 An example of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG. In the semiconductor device of this embodiment, a BT (bismaleimide triazine) resin (Young's modulus of 1.0 ×) containing glass fiber having a thickness of 0.2 mm is used as an insulating buffer layer 40 on a ceramic circuit board on which a semiconductor element is mounted.
10 ⁴ kgf / mm ² or less).

In the embodiment, 92% alumina ceramic is used as the circuit board 10. Wiring pattern 34, internal wiring pattern 34a, and via 34 are formed on this alumina ceramic.
b. In order to form the terminal pad 14, a metallizing paste such as tungsten is screen-printed in a predetermined pattern on an alumina ceramic green sheet that has been processed into a predetermined shape by previously forming holes in the cavity for mounting semiconductor elements. After laminating the ceramic green sheets, they were fired at a predetermined temperature to obtain a circuit board 10 (FIG. 6 (a)). The terminal pad 14 is 0.8 in the embodiment.
The diameter was 64 mm.

Next, the insulating buffer layer 40 is formed on the circuit board 10.
BT resin prepreg having a thickness of about 60 μm is used as an adhesive film to form a BT resin plate 40a containing a glass fiber having a thickness of 0.2 mm on the surface of the circuit board 10 on which the terminal pads 14 are formed. ℃, 30kg / cm
Bonding is performed by heating and pressing at ² (Fig. 6 (b)). A through hole 42 is formed in advance in the glass fiber-containing BT resin plate 40a in alignment with the terminal pad 14. Also, the B
A T resin prepreg is also provided with a through hole in alignment with the through hole 42 so that the terminal pad 14 is exposed at the bottom surface of the through hole 42 with the glass fiber-containing BT resin plate 40a bonded. In the embodiment, the diameter of the through hole penetrating the glass fiber-containing BT resin plate 40a and the BT resin-based prepreg is 0.684 mm.

After the glass fiber-containing BT resin plate 40a is adhered to the circuit board 10, the semiconductor element 30 is attached to the circuit board 10.
With. After the semiconductor element 30 is die-attached to the cavity recess 32 of the circuit board 10 and the semiconductor element 30 and the wiring pattern 34 are wire-bonded, a cap 36 is sealed around the opening of the cavity recess 32 to form the semiconductor element 30. It is sealed (FIG. 6 (c)).

Next, in order to form the conducting portion 44 in the through hole 42, the glass fiber-containing BT resin board 40a is supported upward to support the circuit board 10 while the glass fiber-containing BT resin board 40a is supported.
A pin made of tin-lead eutectic solder having a diameter of about 0.6 mm is inserted into the through hole 42 provided in the resin plate 40a so that it is heated, and the pin is melted in the through hole 42 to form the conductive portion 44. To do. FIG. 6D shows a state in which the conducting portion 44 is formed in the through hole 42. By appropriately setting the length of the pin of the tin-lead eutectic solder set in the through hole 42, the through hole 42
Can be just met.

A conductive portion 44 is formed in a bump shape on the outside of the through hole 42.
In the case of forming the protrusion, the length of the solder pin set in the through hole 42 may be adjusted so that when the solder is melted, the solder pin rises like a bump in the through hole 42.
The conductive material forming the conductive portion 44 is not limited to the tin-lead eutectic solder, and tin-bismuth,
Low melting point alloys such as tin-antimony, tin-silver, tin-indium can be used.

After the conductive portion 44 is formed, solder balls are bonded to the outer surface of the conductive portion 44 as the external connection terminals 12 as shown in FIG.
Is obtained. A high melting point solder is used for the solder ball, and the low melting point alloy of the conductive portion 44 is melted to bond the solder ball. When mounting the semiconductor device on the mounting substrate, a low melting point solder may be attached to one or both of the electrodes on the mounting substrate side and the solder balls of the semiconductor device, and the low melting point solder may be melted for mounting.

In the semiconductor device of this embodiment, the glass fiber-containing BT resin plate 40a acts as the insulating buffer layer 40, and the thermal stress acting on the joint portion when the semiconductor device is mounted can be appropriately relaxed. That is, the external connection terminal 12
When a stress is applied to the insulating buffer layer 40, the insulating buffer layer 40 is deformed to relieve the stress so that the excess stress does not directly act on the joint. Since the conductive portion 44 formed on the insulating buffer layer 40 does not bond to the insulating buffer layer 40, the insulating buffer layer 4
It can be moved independently of 0, and this can also effectively alleviate thermal stress.

In the above embodiment, the BT resin (Young's modulus of 1.0 × 10 ⁴ kgf / mm ² or less) having a thickness of 0.2 mm was used as the material for the insulating buffer layer 40. As the organic material forming the layer 40, it is of course possible to use other materials, for example, epoxy resin, polyimide resin, polyimide siloxane resin, polyester resin, silicone rubber, polyurethane resin and the like.

The thickness of the insulating buffer layer 40 may be appropriately selected depending on the material used for the insulating buffer layer 40, the material of the semiconductor package, the size of the semiconductor package, etc., but the insulating buffer layer 40 has a buffering effect. Therefore, a thickness of about 0.05 mm or more is required. That is,
The insulating buffer layer 40 can obtain a required buffering action by having a certain thickness or more, and when the insulating buffer layer 40 has a thickness of about 20 μm like a protective film such as a solder resist covering the surface of a conventional printed circuit board. It is not possible to exert a sufficient buffering effect. If the insulating buffer layer 40 is too thick, the substrate will warp, so that the maximum thickness is about 1 mm.

Further, the organic material used for the insulating buffer layer 40 is required to have some flexibility so that the joint can be displaced. As flexibility, Young's modulus is about 1.0 x 10
⁴ kgf / mm ² or less is required. If the insulating buffer layer 40 is made of a material that is difficult to deform, the thermal stress acting on the joint cannot be effectively relaxed, which is not suitable in this respect. Although alumina ceramic is used as the circuit board 10 in this embodiment, aluminum nitride, mullite, silicon dioxide, boron nitride, or the like can be used as the circuit board.

(Embodiment 2) A method of manufacturing the semiconductor device shown in FIG. 4 will be described with reference to FIGS. The semiconductor device shown in FIG. 4 has an insulating buffer layer 40 formed on the circuit board 10.
The metal layer 46 is formed on the inner wall surface of the through hole 42. FIG. 7A shows an organic material 50 for forming the insulating buffer layer 40. This organic material 50 has a glass fiber-containing BT resin plate similar to that used in Example 1 as a base material, and copper foil 52 is adhered and formed on both surfaces of the base material. The organic material 50 has a thickness of about 150 μm.

FIG. 7B shows a state in which the organic material 50 is perforated and a through hole 54 for forming the conducting portion 44 for joining the external terminal 12 is provided. The through hole 54 is the circuit board 1.
It is formed by drilling or the like in accordance with the arrangement position of the 0 terminal pad 14. Next, through holes 54 are formed by through-hole plating.
A metal layer 46 is formed on the inner wall surface of the (FIG. 7 (c)). Metal layer 4
6 can be formed by a method of performing electroless copper plating on the inner surface of the through hole 54 and then performing electrolytic copper plating, or a method of performing copper plating by direct plating. As a result, the inner wall surface of the through hole 54 and the copper foil 52 on the surface of the organic material 50 are continuous. The through hole plating is one means for metallizing the inner wall surface of the through hole 54, and another method such as a sputtering method may be used.

Next, the metal layer 46 on the inner wall surface of the through hole 54 and the copper foil 52 on the surface are removed by etching, leaving the metal layer 46a at the opening edges of the upper and lower surfaces of the through hole 54 (FIG. 7 (d)). . The surfaces of the metal layers 46 and 46a are preferably plated with nickel by an electrolytic plating method or the like. Next, in the same manner as in Example 1, a thickness of about 6 was applied to the surface of the organic material 50 for adhesion.
A 0 μm BT resin-based prepreg 56 is applied. This BT resin-based prepreg 56 was previously provided with a through hole in alignment with the through hole 54, and was superposed and adhered to the organic material 50 (FIG. 7 (e)).

The organic material 50 thus obtained is used as the circuit board 1.
The semiconductor package having the insulating buffer layer 40 is obtained by aligning with 0 and bonding to the circuit board 10 by heating and pressurizing as in the first embodiment. In this embodiment, the glass fiber-containing BT resin plate, which is the base material of the organic material 50, is the insulating buffer layer 40, and the through hole 54 is the through hole 4 for forming the conducting portion 44.
2 and the inner wall surface of the through hole 42 is covered with the metal layer 46. FIG. 8 shows a state in which the insulating buffer layer 40 obtained by the above method is bonded to the circuit board 10 by aligning it.

The conducting portion 44 can be formed by adhering the organic material 50 to the circuit board 10 and then inserting a pin made of a low melting point metal such as solder into the through hole 42 as in the first embodiment. In the state of 7 (e), the through hole 54 is filled with a conductive material such as a high melting point solder paste to form the conductive portion 44, and the conductive portion 4 is formed.
It is also possible to adhere the insulating buffer layer 40 formed with No. 4 to the circuit board 10.

[0042]

As described above, in the semiconductor package and the semiconductor device according to the present invention, an insulating buffer layer having a Young's modulus smaller than that of the circuit board is attached to the mounting surface of the circuit board, and the insulating buffer layer is interposed. With the configuration in which the external connection terminals are connected, when the semiconductor device is mounted on the mounting board, the thermal stress acting on the joint due to the difference in thermal expansion coefficient between the circuit board and the mounting board can be effectively relaxed. Therefore, the reliability of the semiconductor device at the time of mounting can be improved. Further, when the inner wall surface of the through hole forming the conductive portion of the insulating buffer layer is coated with the metal layer, the joint area of the joint portion increases, so that the connection reliability of the joint portion can be further improved. As described above, since the thermal stress acting on the joint can be effectively relaxed, it is possible to increase the size of the semiconductor package, and it is possible to effectively cope with the increase in the number of pins. Play.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a sectional view showing a second embodiment of a semiconductor device according to the present invention.

FIG. 3 is a sectional view showing a third embodiment of the semiconductor device according to the present invention.

FIG. 4 is a sectional view showing a fourth embodiment of a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a configuration in the vicinity of a joint of an external connection terminal according to a fourth embodiment.

FIG. 6 is an explanatory diagram showing the manufacturing method of the semiconductor device of the first embodiment.

FIG. 7 is an explanatory diagram showing a method of manufacturing an insulating buffer layer used for manufacturing the semiconductor device of the fourth embodiment.

FIG. 8 is an explanatory diagram showing the manufacturing method of the semiconductor device of the fourth embodiment.

FIG. 9 is a cross-sectional view showing a conventional configuration of a joint portion of an external connection terminal.

FIG. 10 is a cross-sectional view showing another conventional configuration of the joint portion of the external connection terminal.

[Explanation of symbols]

 10 Ceramic Substrate 12 External Connection Terminal 14 Terminal Pad 30 Semiconductor Element 32 Cavity Recess 34 Wiring Pattern 40 Insulation Buffer Layer 40a Glass Fiber BT Resin Board 40 Insulation Buffer Layer 42 Through Hole 44 Conducting Portion 46 Metal Layer 46a Metal Layer 50 Organic Material 52 Copper foil 56 BT resin type prepreg

Claims (7)

[Claims] 1. A terminal board to which an external connection terminal such as a solder ball is electrically connected and attached is provided on a mounting surface of a circuit board on which a semiconductor element is mounted, and the circuit board provided with the terminal pad. An insulating buffer layer having a Young's modulus of 1.0 × 10 ⁴ kgf / mm ² or less and a thickness of 0.05 mm or more and having an electrical insulating property is adhered and formed on the outer surface of, and corresponds to the terminal pad of the insulating buffer layer. A semiconductor package characterized in that a through hole is transparently provided in a portion to be formed. 2. The semiconductor package according to claim 1, wherein a metal layer is deposited on the inner wall surface of the through hole. 3. The semiconductor package according to claim 1, wherein the insulating buffer layer is made of glass fiber-containing BT (bismaleimide triazine) resin. 4. The semiconductor package according to claim 1, wherein the insulating buffer layer is formed in a plurality of layers using different materials. 5. The insulating buffer layer is made of an organic material selected from epoxy resin, BT resin, polyimide resin, polyimide siloxane resin, polyester resin, silicone rubber and polyurethane resin. Semiconductor package. 6. A semiconductor element is mounted on the element mounting surface of the circuit board of the semiconductor package according to claim 1, a conductive portion is formed by filling a conductive material in the through hole. The semiconductor device is characterized in that the terminal pad and the external connection terminal are electrically connected by the conductive portion. 7. A conductive portion is formed by mounting a semiconductor element on an element mounting surface of a circuit board of the semiconductor package according to claim 1, and filling the through hole with a conductive material. The semiconductor device is characterized in that the conductive portion is connected to the terminal pad, and the external connection terminal is formed in a bump shape protruding integrally with the conductive portion from the surface of the insulating buffer layer.