JPH09321139A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide manufacture of a contact hole which enables the wiring pitch of a lower wiring layer to be twice the minimum work dimension F. SOLUTION: An interlayer insulating film 11a made of a silicon oxide film is overlaid with a stopper film 113a made of a silicon nitride film and a sacrifice film 151a made of a BPSG film. By taper etching using a photoresist film pattern 171a having an aperture diameter F as a mask, a dummy contact hole 181a is formed in the sacrifice film 151a. The stopper film 113a and the interlayer insulating film 111a are anisotropically dry-etched to form a contact hole 117a having an aperture diameter F-2d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a contact hole for connecting an upper wiring layer to a lower wiring layer.

[0002]

2. Description of the Related Art Miniaturization of individual semiconductor elements provided on a semiconductor substrate and densification of semiconductor devices provided on a semiconductor substrate on which these semiconductor elements are integrated are still being vigorously pursued. These miniaturization and densification greatly depend on the evolution of the minimum processing dimension (= F) defined by the lithography technology, but if only it depends on this evolution, satisfactory miniaturization and densification can be achieved. Can not. For example, if attention is focused only on the surface of the semiconductor substrate or the lower wiring layers formed on the surface, it is easy to set the minimum line width and the minimum spacing of these lower wiring layers to F. Further, if attention is paid only to the contact holes provided in the insulating film used for connection between the lower wiring layer and the upper wiring layer formed on the insulating film covering the semiconductor substrate, it is easy to set these opening diameters to F. Is. Further, if attention is paid only to the upper wiring layers, it is easy to set the minimum line width and the minimum spacing of these upper wiring layers to F as in the above. However, it is not easy to form a semiconductor device that can be practically used by combining such a lower wiring layer, a contact hole, and an upper wiring layer. The reason why it is not easy depends on the reason related to the lithography process. A semiconductor device in which semiconductor elements are integrated is formed by making full use of a plurality of lithography processes and the like. At this time, an alignment margin of the photo mask is required between the respective lithography steps. Therefore, it is necessary to widen the line width at least in the lower wiring layer portion where the contact holes reach, in consideration of the alignment margin.
It is necessary to set it larger than F.

In recent years, by adopting various kinds of self-aligned contact holes, it is possible to make the line width F at least in the lower wiring layer portion which the contact holes reach. For example, US Pat. No. 5,318,925 discloses the use of self-aligned contact holes for the node contact holes of DRAM. node·
The opening diameter of the contact hole is made equal to the width of the source / drain diffusion layer of the transistor constituting the memory cell of the DRAM. According to the above patent specification, the insulating film spacer is formed on the side surface of the contact hole, and as a result, the effective opening diameter at the lower end of the contact hole (node / contact hole) is larger than that at the upper end of the contact hole. It becomes possible to narrow it. Therefore, even if the opening diameter of the contact hole is made equal to the line width of the lower wiring layer (source / drain diffusion layer of the transistor forming the memory cell of the DRAM), no problem will occur.

Referring to FIG. 33, which is a schematic sectional view of the manufacturing process of the semiconductor device, the method of manufacturing the semiconductor device described in the above-mentioned US Pat. No. 5,318,925 is as follows.

First, a field oxide film 202 is formed in an element isolation region on the surface of a P-type silicon substrate 201, and a gate oxide film is formed in the element isolation region. After the word line also serving as the gate electrode is formed, the N ⁺ type source / drain diffusion layer 208 is self-aligned with the gate electrode in the element formation region.
Is formed. These N ⁺ type source / drain diffusion layers 208 have a predetermined line width. An (first) interlayer insulating film 212 having a flat upper surface is formed, and a conductor film pattern 261 is formed on the surface of the interlayer insulating film 212. Due to misalignment in the lithography process, a part of each of the conductor film patterns 261 overlaps with each of the N ⁺ type source / drain diffusion layers 208 via the interlayer insulating film 212. After the (second) interlayer insulating film 232 covering the interlayer insulating film 212 is formed, the opening diameter of the same value as the above predetermined line width is formed on the surface of the interlayer insulating film 232 (first). A photoresist film pattern 275 is formed. By the first anisotropic dry etching using the photoresist film pattern 275 as a mask, the interlayer insulating film 232 is selectively etched to the vicinity of the bottom surface thereof, and an opening 283 is formed in the interlayer insulating film 232. It These openings 283 hang on a part of the conductor film pattern 261 (due to misalignment) [FIG. 33 (a)].

Further, a photo resist film pattern 275
By the second anisotropic dry etching using as a mask, the conductor film pattern 261 is selectively etched, and the bit line 224 is left. Furthermore, by the third anisotropic dry etching using the photoresist film pattern 275 as a mask, the interlayer insulating films 232, 2 are formed.
12 is selectively etched to form a node contact hole 238 reaching the N ⁺ type source / drain diffusion layer 208. Subsequently, an insulating film 255 having a predetermined film thickness is formed on the entire surface [FIG. 33 (b)].

Next, the insulating film 255 is etched back to leave an insulating film spacer 239 covering the side surface of the node contact hole 238. These insulating film spacers 239 do not have a surface that can be defined as an upper surface. The side surface of the insulating film spacer 239 except the vicinity of the upper end of the node contact hole 238 is substantially the P-type silicon substrate 20.
1 has a plane perpendicular to the surface of the node contact hole 2
The side surface of the insulating film spacer 239 near the upper end of 38 forms a curved surface from the vertical side surface and reaches the upper end of the node contact hole 238. If the predetermined film thickness is set to a value larger than the alignment margin, the lower end of the effective node contact hole provided with the insulating film spacer 239 does not protrude from the N ⁺ type source / drain diffusion layer 208. Become. After the conductor film 264 is formed on the entire surface, a (second) photoresist film pattern 276 having a width wider than the predetermined line width is formed on the surface of the conductor film 264 [FIG. 33]. (C)].

The conductor film 264 is patterned by the fourth anisotropic dry etching using the photoresist film pattern 276 as a mask to form the storage node electrode 244 [FIG. 33 (d)].

[0009]

The above-mentioned US Pat. No. 531
If the semiconductor device manufacturing method described in the specification of 8925 is applied, an N ⁺ -type source (which is a lower wiring layer)
The line width of the drain diffusion layer (however, it is the line width in the direction parallel to the word line, not the line width of the N ⁺ type source / drain diffusion layer in the direction parallel to the bit line (= interval between word lines)). ) Is easy to be F. (Note that it is impossible to make the word line spacing closer to F by the self-aligned contact hole described in the above-mentioned US Pat. No. 5,318,925. This node contact hole is adjacent to the word line. Since the part of is the channel region part (the part that directly functions as the gate electrode), the word line width (gate length) when forming the node contact hole
Etching to narrow the area cannot be performed. However, if only the self-aligned contact holes having the insulating film spacer formed on the side surface are adopted, the wiring pitch (D
In RAM, it is not easy to bring at least the word line wiring pitch) to 2F. US Pat. No. 53
The reason will be described below by taking the self-aligned contact hole described in the specification of 18925 as an example. Note that the bit line and the storage node electrode will be considered here as the intermediate wiring layer and the upper wiring layer, respectively.

First, with reference to FIG. 34, which is a schematic cross-sectional view of the manufacturing process of a semiconductor device, a problem in the case where the conductor film forming the upper wiring layer is thick will be described.

A field oxide film 202 and an N ⁺ type source / drain diffusion layer 208 are formed on the surface of a P type silicon substrate 201.
a is formed. The line width of these N ⁺ type source / drain diffusion layers 208a is F. An (first) interlayer insulating film 212 having a flat upper surface is formed, and the interlayer insulating film 2 is formed.
A conductor film pattern (not shown) is formed on the surface of 12. (Second) interlayer insulating film 2 covering the interlayer insulating film 212
32a is formed. The upper surface of the interlayer insulating film 232a is flattened. A first photoresist film pattern (not shown) having an opening diameter of F is formed on the surface of the interlayer insulating film 232a. By the first anisotropic dry etching using the first photoresist film pattern as a mask, the interlayer insulating film 232a is selectively etched to the vicinity of the bottom surface thereof, and an opening is formed in the interlayer insulating film 232a. To be done.

Further, the conductive film pattern is selectively etched by the second anisotropic dry etching using the first photoresist film as a mask, and the intermediate wiring layer 224a is left. In addition, the first photo
By the third anisotropic dry etching using the resist film pattern as a mask, the interlayer insulating films 232a and 212 are selectively etched to form contact holes 238a reaching the N ⁺ type source / drain diffusion layers 208a.
Then, an insulating film having a predetermined film thickness is formed on the entire surface, the insulating film is etched back, and an insulating film spacer 239a covering the side surface of the contact hole 238a is left. The shape of these insulating film spacers 239a is substantially the same as the shape of the insulating film spacers 239 shown in FIG. If the predetermined film thickness is set to a value larger than the alignment margin, the lower end of the effective contact hole provided with the insulating film spacer 239a is the N ⁺ type source / drain diffusion layer 2.
It will not leak out from 08a. After the thick conductor film 264aa is formed on the entire surface, the conductor film 264a is formed.
A photoresist film pattern 2 having a width F on the surface of a
76aa is formed (FIG. 34 (a)).

The conductor film 264aa is patterned by the fourth anisotropic dry etching using the photoresist film pattern 276aa as a mask to form an upper wiring layer 244aa having a line width F (see FIG. 34 (b). )].

Here, the photoresist film pattern 27
It is not easy to form 6aa in a self-aligned manner immediately above the contact hole 238a (via the conductor film 264aa). Therefore, a part of the side surface of the photoresist film pattern 276aa is located on the insulating film spacer 239a. As a result, a shape defect of the upper wiring layer 244aa (at a portion where the upper wiring layer 244aa is in direct contact with the insulating film spacer 239a) occurs, and problems in quality reliability such as mechanical strength and moisture resistance are likely to occur.

Next, with reference to FIG. 35, which is a schematic cross-sectional view of the manufacturing process of the semiconductor device, a problem in the case where the thickness of the conductor film forming the upper wiring layer is thin will be described.

By the same method as the formation of the semiconductor device shown in FIG. 34, the formation of the contact hole 238a and the formation of the insulating film spacer 239a are performed. next,
A thin conductor film 264ab is formed on the entire surface. Subsequently, a photoresist film pattern 276ab is formed on the surface of the conductor film 264a (for the purpose of making its pattern width F) [FIG. 35 (a)].

The conductor film 264a is patterned by the fourth anisotropic dry etching using the photoresist film pattern 276ab as a mask, and the upper wiring layer 244 is formed.
Ab is formed [FIG.35 (b)].

Here, first, a problem occurs in the shape of the photoresist film pattern 276ab. A part of the portion which should be the end portion of the second photoresist film pattern of interest is the insulating film spacer 2 (at the portion where the surface is curved).
It will be located directly above 39a. Therefore, at the time of exposure for forming the second photoresist film pattern, a shape defect occurs in the photoresist film pattern 276ab due to the reflection of light from the curved surface of the spacer 239a. Pattern 27
The width of 6ab is narrower than F. As a result of forming the upper wiring layer 244ab by patterning using the photoresist film pattern 276ab as a mask, the line width of the upper wiring layer 244ab at the upper end of the contact hole 238a is also F.
It becomes narrower. Therefore, in addition to the problem of the upper wiring layer 244aa, the upper wiring layer 244ab also has a problem of quality reliability in electrical characteristics.

In order to avoid these problems, conventionally, the upper end of the contact hole is completely covered with the upper wiring layer.
Therefore, even if the self-aligned contact hole having an opening diameter of F is adopted, the line width of the upper wiring layer is wider than that of F. For this reason, even if the spacing between the upper wiring layers is F, the wiring pitch of the upper wiring layer becomes wider than 2F, and accordingly, the wiring pitch of the lower wiring layer must be wider than 2F.

Therefore, an object of the method of manufacturing a semiconductor device of the present invention is to provide a method of manufacturing a contact hole which enables the wiring pitch of a lower wiring layer to be twice the minimum processing dimension F. Another object of the present invention is to provide a method for manufacturing a node contact hole in a COB type DRAM, in which the wiring pitch of at least word lines is set to 2F and the cell size of a memory cell can be reduced.

[0021]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a lower wiring layer on the surface of a semiconductor substrate and forming an interlayer insulating film covering the surface of the semiconductor substrate, A step of forming a stopper film covering the surface of the interlayer insulating film, and forming a sacrificial film having a required film thickness made of a material capable of selectively anisotropic dry etching selectively on the stopper film, A step of forming a first photoresist film pattern having a first opening diameter on the surface of the sacrificial film, and a first anisotropic dry step using the first photoresist film pattern as a mask. Forming a dummy contact hole in the sacrificial film by etching, the dummy contact hole having an upper end having a first opening diameter and a lower end having a second opening diameter narrower than the first opening diameter; photo·
A step of removing the resist film pattern, a step of forming an opening having a second opening diameter in the stopper film by second anisotropic dry etching, and a step of selectively removing the sacrificial film. And a step of forming a contact hole having the second opening diameter and reaching the lower wiring layer in the interlayer insulating film by third anisotropic dry etching using the opening as a mask, and A conductive film is formed on the first conductive layer, and a fourth anisotropic dry etching is performed using the second photoresist film pattern as a mask to form an upper wiring layer made of the conductive film. I am trying.

Preferably, the first opening diameter is the minimum processing dimension (= F), the minimum wiring width and the minimum spacing of the lower wiring layer are F, respectively, and the minimum wiring width and the minimum wiring width of the upper wiring layer are respectively. The intervals are F, respectively.

In a preferred first aspect of the method for manufacturing a semiconductor device of the present invention, a lower wiring layer having a minimum line width and a minimum spacing of F is formed on the surface of the semiconductor substrate, and is formed of a silicon oxide film. A step of forming an interlayer insulating film on the entire surface, and a stopper film made of a silicon nitride film are formed on the surface of the interlayer insulating film, and a PSG film or BP is formed.
A step of forming a sacrificial film having a required film thickness of an SG film on the entire surface, and a step of forming a first photoresist film pattern of F having a first opening diameter on the surface of the sacrificial film. And by the first anisotropic dry etching using the first photoresist film pattern as a mask, the second upper end has a first opening diameter and the lower end has a second opening diameter narrower than the first opening diameter. A step of forming a dummy contact hole having an opening diameter in the sacrificial film, a step of removing the first photoresist film pattern, and a second anisotropic dry etching process are performed to form a second contact hole in the stopper film. The second opening is formed by a step of forming an opening having an opening diameter of 2, a step of selectively removing the sacrificial film, and a third anisotropic dry etching using the opening as a mask. Has a caliber and reaches the above lower wiring layer A step of forming a contact hole in the interlayer insulating film, a conductive film is formed on the entire surface, and the conductive film is formed by fourth anisotropic dry etching using the second photoresist film pattern as a mask. Patterning to form an upper wiring layer having a minimum line width and a minimum spacing of F, respectively.

Preferably, the interlayer insulating film is composed of a first interlayer insulating film and a second interlayer insulating film covering the first interlayer insulating film, and a minimum on the surface of the first interlayer insulating film. An intermediate wiring layer having an interval of F is formed. More preferably, there is a step of patterning the stopper film by fifth anisotropic dry etching using the second photoresist film pattern as a mask.

In a preferred second aspect of the method for manufacturing a semiconductor device of the present invention, a lower wiring layer having a minimum line width and a minimum interval of F is formed on the surface of the semiconductor substrate or the surface, and is formed of a silicon oxide film. A step of forming an interlayer insulating film on the entire surface, and a step of forming a stopper film made of a first conductor film on the surface of the interlayer insulating film to form a PSG film or BP
A step of forming a sacrificial film having a required film thickness of an SG film on the entire surface, and a step of forming a first photoresist film pattern of F having a first opening diameter on the surface of the sacrificial film. And by the first anisotropic dry etching using the first photoresist film pattern as a mask, the second upper end has a first opening diameter and the lower end has a second opening diameter narrower than the first opening diameter. A step of forming a dummy contact hole having an opening diameter in the sacrificial film, a step of removing the first photoresist film pattern, and a second anisotropic dry etching process are performed to form a second contact hole in the stopper film. The second opening is formed by a step of forming an opening having an opening diameter of 2, a step of selectively removing the sacrificial film, and a third anisotropic dry etching using the opening as a mask. Has a caliber and reaches the above lower wiring layer Forming a contact hole in the interlayer insulating film, forming a second conductor film covering the stopper film, etching back the second conductor film and the stopper film, and A step of leaving a contact plug made of a second conductor film in the contact hole, and a fourth anisotropic method in which a third conductor film is formed on the entire surface and the second photoresist film pattern is used as a mask. Patterning the third conductor film by a conductive dry etching to form an upper wiring layer having a minimum line width and a minimum spacing of F, respectively.

Preferably, the second conductor film and the third conductor film are made of the same material.

In a preferred third aspect of the method for manufacturing a semiconductor device of the present invention, a lower wiring layer having a minimum line width and a minimum spacing of F is formed on the surface of the semiconductor substrate, and is formed of a silicon oxide film. A step of forming an interlayer insulating film on the entire surface, and a step of forming a stopper film made of a first conductor film on the surface of the interlayer insulating film to form a PSG film or BP
A step of forming a sacrificial film having a required film thickness of an SG film on the entire surface, and a step of forming a first photoresist film pattern of F having a first opening diameter on the surface of the sacrificial film. And by the first anisotropic dry etching using the first photoresist film pattern as a mask, the second upper end has a first opening diameter and the lower end has a second opening diameter narrower than the first opening diameter. A step of forming a dummy contact hole having an opening diameter in the sacrificial film, a step of removing the first photoresist film pattern, and a second anisotropic dry etching process are performed to form a second contact hole in the stopper film. The second opening is formed by a step of forming an opening having an opening diameter of 2, a step of selectively removing the sacrificial film, and a third anisotropic dry etching using the opening as a mask. Has a caliber and reaches the above lower wiring layer A step of contact holes formed in the interlayer insulating film that, the second conductive film is formed on the entire surface, the second
The second conductor film and the stopper film are patterned by the fourth anisotropic dry etching and the fifth anisotropic dry etching using the photoresist film pattern of FIG. And a minimum distance of F, respectively, and a step of forming an upper wiring layer having a laminated structure.

[0028]

Next, the present invention will be described with reference to the drawings.

Referring to FIGS. 1 and 2 which are schematic cross-sectional views of a manufacturing process of a semiconductor device, a gate electrode of a MOS transistor and an N ⁺ type source / drain diffusion layer formed on a surface of a silicon substrate as an example of a lower wiring layer. Then, the first embodiment of the present invention is as follows. The semiconductor device here is formed by a manufacturing method based on the 0.2 μm design rule, and the minimum processing dimension F is 0.2 μm (20
0 nm), alignment margin is 0.04 μm (4
0 nm).

First, a field oxide film 102a having a film thickness of about 250 nm is formed in the element isolation region on the surface of the P-type silicon substrate 101a. A gate oxide film 103a having a film thickness of about 8 nm is formed in the element formation region on the surface of the P-type silicon substrate 101a. After the gate electrode 104a made of a tungsten polycide film having a film thickness of about 150 nm is formed, the N ⁺ type source / drain diffusion layer 106a having a junction depth of about 150 nm is formed. Here, the minimum line width (gate length) and the minimum interval of the gate electrode 104a and the minimum line width (gate width) and the minimum interval of the N ⁺ -type source / drain diffusion layer 106a are respectively F
(= 200 nm). An interlayer insulating film 111a made of a silicon oxide film is formed on the entire surface by atmospheric pressure vapor deposition method (APCVD) or reduced pressure vapor deposition method (LPCVD). The surface of the interlayer insulating film 111a is preferably flattened by chemical mechanical polishing (CMP).
The film thickness of the interlayer insulating film 111a immediately above the N ⁺ type source / drain diffusion layer 106a is about 400 nm. Film thickness 50
stopper film 113a made of a silicon nitride film of about nm
Are formed on the entire surface by LPCVD [Fig. 1
(A)].

Next, a BP having a film thickness of about 570 nm (= h)
The sacrificial film 151a made of the SG film is formed of tetra ethoxy.
Silane (TEOS; Si (OC_TwoH_Five)_Four),ozone
(O_Three ), Tri-methyl phosphate (TMP; P
O (OCH_Three)_Three) And tri-methyl borate (T
MB; B (OCH_Three)_Three) As a raw material by LPCVD
Is formed on the entire surface. A PSG film is used as the sacrificial film.
You may use. Then, the (first) opening diameter and the minimum power
(First) photoresist film pattern with turn width F
The turn 171a is formed on the surface of the sacrificial film 151a.
You. The opening of this photoresist film 171a is generally
Gate electrode 104a and N⁺Type source / drain diffusion
It is provided directly above the layer 106a, and the opening of these openings is
Electrode 104a and N⁺Type source / drain diffusion layer
The protrusion from just above 106a is an alignment margin
(40 nm) or less.

Subsequently, a first anisotropic dry etching is performed using the photoresist film 171a as a mask, and the sacrificial film 151a is taper-etched to form a dummy contact hole 181a [FIG. 1].
(B)]. In this first anisotropic dry etching, the flow rate of tetrafluoro methane (CF ₄ ) is 60 sccc.
m, the flow rate of trifluoro methane (CHF ₃ ) is 60
sccm, the flow rate of argon (Ar) is 800 sccm,
The pressure is 130 Pa. Under this condition, the taper angle θ (inclination with respect to the vertical plane) is about 6 °, the value of d is about 60 nm (a value larger than the alignment margin), and the dummy contact hole 181
The opening diameter at the upper end of a is equal to the first opening diameter (= F) and the opening diameter at the lower end (= second opening diameter) is F-2d (= 80n).
m). Tapering etching is possible by this first anisotropic dry betting, because the side surface of the contact hole formed by this etching is a fluorocarbon polymer (C which is a reaction product generated during this etching). _This is because it is easily covered by _X F _Y ). θ depends on the conditions of the first anisotropic dry etching, and d depends on θ and h.

Next, second anisotropic dry etching is performed, and the second opening diameter (F-
An opening with 2d) is formed. In this second anisotropic dry etching, the flow rate of CF ₄ is 60 sccm,
CHF ₃ flow rate is 30 sccm, Ar flow rate is 800 s
It is carried out under the conditions of ccm and pressure of 200 Pa. This second anisotropic dry etching produces less reaction products than the first anisotropic dry etching. This second
Before and after the anisotropic dry etching of the photoresist film 171a (and the dummy contact hole 181a).
Reaction product (which covers the side surface of the) is removed.

After that, a third anisotropic dry film is formed by using at least the opening provided in the stopper film 113a as a mask.
After the etching, the gate electrode 104a or the N ⁺ type source / drain diffusion layer 1 is formed on the interlayer insulating film 111a.
A contact hole 117a reaching 06a is formed. These contact holes 117a have a second opening diameter (F-2d
= 80 nm). Therefore, these contact holes 117a do not protrude from the gate electrode 104a and the N ⁺ type source / drain diffusion layer 106a. As is clear from this result, according to the first embodiment, the wiring pitch of the lower wiring layer can be set to 2F. During this etching, the sacrificial film 151aa is also anisotropically etched, leaving the sacrificial film 151aa [FIG. 1 (c)]. In this third anisotropic dry etching, the flow rate of CHF ₃ is 50 sccm, carbon monoxide (C
The flow rate of O) is 250 sccm and the pressure is 7 Pa. This third anisotropic dry etching etches the silicon oxide film substantially selectively. The etching rate of the silicon oxide film in the third anisotropic dry etching is about 20 times the etching rate of the silicon nitride film.

Next, the remaining sacrificial film 151aa is selectively removed by gas etching using hydrogen fluoride (HF). Interlayer insulating film 111a, stopper film 113
Since a is formed of a silicon oxide film and a silicon nitride film, respectively, at the time of this gas etching, the stopper film 113a (and the opening provided therein),
There is no effect on the interlayer insulating film 111a and the contact hole 117a. The removal of the sacrificial film by the gas etching may be performed immediately after the opening is formed in the stopper film 113a.

After that, for example, N ^{+ having a} film thickness of about 250 nm is formed.
A conductive film 161a made of a type polycrystalline silicon film (N ⁺ type at the film forming stage) is formed on the entire surface by LPCVD.
The conductor film 161a may be a tungsten / silicide film formed by sputtering and having a film thickness of about 150 nm instead of the N ⁺ -type polycrystalline silicon film. It may be a titanium silicide film formed by sputtering. When the N ⁺ -type polycrystalline silicon film is adopted, this film thickness is large because the sheet resistance is higher than that of the tungsten silicide film. Then, the conductor film 161a
Second photoresist film pattern 173a on the surface of
Is formed. Since the contact hole 117a has an opening diameter of F-2d, it becomes easy to set the minimum pattern width and the minimum interval of these second photoresist film patterns 173a to F [FIG. 2 (a)].

Then, a photoresist film pattern 173 is formed.
The conductor film 161a is patterned by the fourth anisotropic dry etching using a as a mask, and the upper wiring layer 1
23a is formed [FIG. 2 (b)].

The cell size of the memory cell of the COB type DRAM in which the capacitor is formed at a position higher than the bit line is usually about 11F ^{2 to} 13F ² . If the manufacturing method according to the first embodiment is applied to the formation of the memory cell of the DRAM in the COB type, the cell size is 10F.
It is easy to reduce to about ² .

Prior to the description of the manufacturing method according to the application example of the first embodiment, first, FIG. 3 which is a schematic plan view of a memory cell of a COB type DRAM and FIG. 4 which is a schematic sectional view are shown. The configuration of the memory cell of the DRAM obtained as a result of this application example will be described with reference to FIG. Note that FIG. 3A is a schematic plan view showing the structure below the bit line.
(B) is a schematic plan view that clearly shows the positional relationship among bit contact holes, bit lines, node contact holes, and storage node electrodes. 4A, 4B and 4C are schematic cross-sectional views taken along the lines AA, BB and CC of FIG.

The MOS transistor has a gate oxide film 103.
a, a word line 105a also serving as a gate electrode, an N ⁺ type source / drain diffusion layer 107a and an N ⁺ type source / drain diffusion layer 108a. Word line 105
a is formed of a tungsten polycide film having a film thickness of about 150 nm. The minimum distance between these word lines 105a and the line width in the channel region are F,
The wiring pitch of a is 2F. The junction depth of the N ⁺ type source / drain diffusion layers 107a and 108a is about 150 nm, and the line width of the N ⁺ type source / drain diffusion layer 108a and the N ⁺ type source / drain diffusion layer 1
The minimum line width of 07a is F. These MOS transistors have a first interlayer insulating film 112 made of a silicon oxide film.
a. The surface of the interlayer insulating film 112a is flattened, and the N ⁺ type source / drain diffusion layer 107 is formed.
a, the film thickness of the interlayer insulating film 112a immediately above 108a is 30
It is about 0 nm.

The bit contact hole 1 reaching the N ⁺ type source / drain diffusion layer 107a is formed in the interlayer insulating film 112a.
18a is provided. Bit contact hole 118
The manufacturing method described in the above-mentioned US Pat. No. 5,318,925 is adopted for forming a, and an insulating film made of a silicon oxide film having a film thickness of d (= 60 nm) is formed on the side surface of the bit contact hole 118a. Spacers 119 are provided. The opening diameter of the upper end of the bit contact hole 118a is F (= 200 nm), and the effective opening diameter of the lower end is F-2d (= 80 nm). Due to this manufacturing method (not shown in the drawing), the bit contact hole 1
In the portion adjacent to 18a, the line width of the word line 105a is F
It is thinner. However, since these portions of the word line 105a are formed on the surface of the field oxide film 102a, there is no problem such as a short gate length. A bit line 124a directly connected to the N ⁺ type source / drain diffusion layer 107a through the bit contact hole 118a is provided on the surface of the interlayer insulating film 112a. Bit line 124a has a film thickness of 150 nm
The bit line 124a has a line width and an interval of 1.5 F and F, respectively.

The interlayer insulating film 112a is covered with a second interlayer insulating film 132a made of a silicon oxide film having a flattened surface and a film thickness of about 300 nm. The interlayer insulating film 132a is covered with a stopper film 134a made of a silicon nitride film having a film thickness of about 50 nm. Book first
The node contact hole 138a formed by applying the embodiment of FIG.
It penetrates a and 112a and reaches the N ⁺ type source / drain diffusion layer 108a. Node contact hole 1
The opening diameter of 38a is F-2d (= 80 nm), the average distance between the word line 105a or the bit line 124a and the node contact hole 138a is d, and the minimum distance (considering the alignment deviation) is d- ". alignment·
Margin ”(= 20 nm). The storage node electrode (at the portion filling the node contact hole 138a) and the word line 105a or the bit line 124
If a silicon oxide film having a film thickness of 20 nm is interposed between a and a, insulation separation between them can be secured.

N through the node contact hole 138a
^The storage node electrode 144a directly connected to the ⁺ type source / drain diffusion layer 108a is the stopper film 134.
It is provided on the surface of a. Storage node electrode 144a is made of an N ⁺ -type polycrystalline silicon film having a film thickness of about 800 nm, and storage node electrode 144a has widths, lengths, and intervals of 1.5F, 3F, and F. The surface of the storage node electrode 144a is made of a tantalum oxide (Ta ₂ O ₃ ) film having a film thickness of about 10 nm (this film thickness is about 2.5 nm when converted to a silicon oxide film). The capacitor insulating film 145a is covered with a cell plate electrode 146a made of a titanium nitride film having a film thickness of about 100 nm.

Because of this structure, the first
The cell size of the DRAM memory cell to which the above embodiment is applied is 10F ² (= 4F × 2.5F).

3, 4, and 5, which are schematic cross-sectional views of the manufacturing process along line AA in FIG. 3, and FIG. 6, and FIG. 7, which is a schematic cross-sectional view of the manufacturing process along line BB in FIG. 8 and FIG. 9 which is a cross-sectional schematic view of the manufacturing process along the CC line in FIG. 3, the DR of the application example of the first embodiment and the above embodiment is referred to.
The AM is formed as follows.

First, a field oxide film 102a having a film thickness of about 250 nm is formed in the element isolation region on the surface of the P-type silicon substrate 101a. A gate oxide film 103a having a film thickness of about 8 nm is formed in the element formation region on the surface of the P-type silicon substrate 101a. Each element forming region has a T shape, and these element forming regions are regularly arranged. After the word line 105a made of a tungsten polycide film having a film thickness of about 150 nm is formed, 15
N ⁺ type source / drain diffusion layers 107a and 108a having a junction depth of about 0 nm are formed. APCVD
Alternatively, a silicon oxide film is deposited on the entire surface by LPCVD or the like, and the surface thereof is planarized by CMP,
The interlayer insulating film 112a having a film thickness of about 300 nm is formed. By the same method as the manufacturing method described in the above-mentioned US Pat. No. 5,318,925, the film thickness d (= 60
nm) insulating film spacer 119 made of a silicon oxide film
With N ⁺ type source / drain diffusion layer 107a
And a bit contact hole 118a having an opening diameter of F at the upper end is formed in the interlayer insulating film 112a. A tungsten silicide film having a film thickness of about 150 nm is formed on the entire surface by sputtering. This tungsten silicide film is patterned to form a bit line 124a having a line width of 1.5F and a space F (FIG. 3).
(A), FIG. 4, FIG. 5 (a), FIG. 7 (a), FIG.
(A)].

Next, a silicon oxide film is deposited on the entire surface by APCVD or LPCVD, and the surface thereof is flattened by CMP to form an interlayer insulating film 132a having a film thickness of about 300 nm. Then, the stopper film 134 made of a silicon nitride film having a film thickness of 50 nm is formed.
a is formed on the entire surface by LPCVD [FIG.
(B), FIG. 7 (b), FIG. 9 (b)].

Next, a BP having a film thickness of about 570 nm (= h)
The sacrificial film 153a made of the SG film or the PSG film is L
It is formed on the entire surface by PCVD. Then, the opening diameter is F
And the minimum pattern width is 1.5F (first)
The photoresist film pattern 175a is the sacrificial film 153.
It is formed on the surface of a. This photoresist film 17
The opening of 5a is almost the N ⁺ type source / drain diffusion layer 1
It is provided directly above 08a. Photo resist film 17
By the first anisotropic dry etching using 5a as a mask, the sacrificial film 153a is taper-etched to form the dummy contact hole 183a. The opening diameter of the upper end of the dummy contact hole 183a is F,
The opening diameter at the lower end is F-2d (= 80 nm), and the taper angle θ is about 6 ° [FIG. 5 (c), FIG. 7 (c), FIG. 9 (c)].

Next, a second anisotropic dry etching is performed, and the second opening diameter (F-
An opening with 2d) is formed. Before and after this second anisotropic dry etching, the photoresist film 1
75a (and the reaction product which covers the side surface of the dummy contact hole 183a) is removed.

After that, the third anisotropic dry film is formed using at least the opening provided in the stopper film 134a as a mask.
Etching is performed to form a node contact hole 138a penetrating the stapper film 134a, the interlayer insulating film 132a and the interlayer insulating film 112a and reaching the N ⁺ type source / drain diffusion layer 108a. The opening diameter of these node contact holes 138a has F-2d (= 80 nm). Therefore, these node contact holes 138a do not protrude from the N ⁺ type source / drain diffusion layer 108a and do not hang on the word line 105a or the bit line 124a. As is clear from this result, by applying the first embodiment, the wiring pitch of the word lines 105a can be set to 2F.
At the time of this etching, the sacrificial film 153a is also anisotropically etched, and the sacrificial film 153aa is left [FIG. 3, FIG. 4, FIG. 6 (a), FIG. 8 (a), and FIG. 9 (d)].

Next, the remaining sacrificial film 153aa is selectively removed by gas etching using HF.
The removal of the sacrificial film by the gas etching may be performed immediately after the opening is formed in the stopper film 134a. Conductor film 165a made of an N ⁺ -type polycrystalline silicon film (N ⁺ -type at the film formation stage) having a film thickness of about 800 nm
Are formed on the entire surface by LPCVD. Then, a second photoresist film pattern 176a is formed on the surface of the conductor film 165a. The minimum pattern width and the minimum interval of these second photoresist film patterns 176a reflect the line width and the interval of the bit lines 124a to be 1.5.
F, F [Fig. 3, Fig. 4, Fig. 6 (b), Fig. 8 (b),
FIG. 9 (e)].

Next, a photoresist film pattern 176
The conductor film 165a is patterned by the fourth anisotropic dry etching using a as a mask,
The node electrode 144a is formed. A capacitive insulating film 145a made of a tantalum oxide film having a film thickness of about 10 nm is formed on the entire surface by plasma-enhanced vapor phase epitaxy (PECVD). This PECVD uses penta-ethoxy-tantalum (Ta (OC ₂ H ₅ ) ₅ ) vaporized at a temperature of about 170 ° C. and oxygen (O ₂ ) as raw material gases at a pressure of about 130 Pa and a temperature of about 470 ° C. Done under temperature. Further, a cell plate electrode 146a made of a titanium nitride film having a film thickness of about 100 nm is formed on the entire surface by sputtering, and the memory cell of the DRAM to which the first embodiment is applied is completed [FIG. 4].

Referring to FIGS. 10 and 11 which are schematic cross-sectional views of the manufacturing process of the semiconductor device, the second embodiment of the present invention is the same as the first embodiment in that the stopper film is also patterned after the formation of the upper wiring layer. The difference from the first embodiment is as follows. Also in the second embodiment, the minimum processing dimension F is 200 nm and the alignment margin is 40 nm.

First, a field oxide film 102b with a film thickness of about 250 nm and a gate oxide film 103b with a film thickness of about 8 nm are formed in the device isolation region and device forming region on the surface of the P-type silicon substrate 101b. Gate electrode 104b made of a tungsten polycide film with a film thickness of about 150 nm
Then, the N ⁺ type source / drain diffusion layer 106b having a junction depth of about 150 nm is formed.
The minimum line width (gate length) and the minimum interval of the gate electrode 104b and the minimum line width (gate width) and the minimum interval of the N ⁺ type source / drain diffusion layer 106b are F, respectively. An interlayer insulating film 111b having a flattened surface and made of a silicon oxide film having a film thickness of about 400 nm is formed on the entire surface. A stopper film 113b made of a silicon nitride film having a film thickness of about 50 nm is formed on the entire surface [FIG.
(A)].

Next, a BP having a film thickness of about 570 nm (= h)
A sacrificial film 151b made of an SG film or a PSG film is formed on the entire surface. A (first) photoresist film pattern 171b having an opening diameter (and minimum pattern width) of F
Are formed on the surface of the sacrificial film 151b. First anisotropic dry etching is performed using the photoresist film 171b as a mask, and the sacrificial film 151b is tapered.
The dummy contact hole 181b is formed by etching. The opening diameter at the upper end, the opening diameter at the lower end, and the taper angle θ of the dummy contact hole 181b are F and F, respectively.
F-2d (= 80 nm) and about 6 ° [FIG.
(B)].

Next, for example, after removing the photoresist film pattern 171b, a second anisotropic dry etching is performed, and the opening diameter (F-2
An opening with d) is formed. For example, the sacrificial film 151
After removing b by HF gas etching, third anisotropic dry etching is performed using the opening provided in the stopper film 113b as a mask, and the interlayer insulating film 11 is formed.
A contact hole 117b reaching the gate electrode 104b or the N ⁺ type source / drain diffusion layer 106b is formed in 1b. Since these contact holes 117b also have an opening diameter of F-2d (= 80 nm), these contact holes 117b also do not protrude from the gate electrode 104b and the N ⁺ type source / drain diffusion layer 106b. As a result, the wiring pitch of the lower wiring layer can be set to 2F also in the second embodiment [FIG.
(C)].

Thereafter, for example, N ^{+ having a} film thickness of about 250 nm is formed.
A conductive film 161b made of a type polycrystalline silicon film (N ⁺ type in the film forming step) is formed on the entire surface, and a second photoresist film pattern 173b is formed on the surface of the conductive film 161b. Since the contact hole 117b has an opening diameter of F-2d, it is easy to set the minimum pattern width and the minimum interval of these second photoresist film patterns 173b to F [FIG. 11 (a)].

Next, a photoresist film pattern 173
The conductor film 161b is patterned by the fourth anisotropic dry etching using b as a mask, and the upper wiring layer 1
23b is formed. Further, the stopper film 113b is patterned by the fifth anisotropic dry etching,
The stopper film 113ba is left [FIG. 11 (b)].

The second embodiment has the effects of the first embodiment. With the application as described above, the effect peculiar to the second embodiment is not realized, but CO
When the second embodiment is applied a plurality of times, like the application of the second embodiment to the formation of a memory cell of a B-type DRAM, it is unique to the second embodiment. The effect becomes apparent.

Referring to FIG. 12 which is a schematic plan view of the memory cell of the COB type DRAM and FIG. 13 which is a schematic sectional view, the configuration of the memory cell of the DRAM to which the second embodiment is applied is as follows. It is as follows. FIG.
2 (a) is a schematic plan view showing a structure below the bit line, and FIG. 12 (b) is a bit contact hole, a bit line,
FIG. 3 is a schematic plan view showing a positional relationship between a node contact hole and a storage node electrode. FIG. 13 (a),
12B and 12C are schematic cross-sectional views taken along the lines AA, BB, and CC of FIG.

The MOS transistor has a gate oxide film 103.
b, a word line 105b also serving as a gate electrode, an N ⁺ type source / drain diffusion layer 107b and an N ⁺ type source / drain diffusion layer 108b. Word line 105
b is formed of a tungsten polycide film having a thickness of about 150 nm. Spacing between these word lines 105b,
The line width is F, and the wiring pitch of the word lines 105b is 2F.
It is. The junction depth of the N ⁺ type source / drain diffusion layers 107b and 108b is about 150 nm, and the line width of the N ⁺ type source / drain diffusion layer 108b and the minimum line width of the N ⁺ type source / drain diffusion layer 107b are It is F. These MOS transistors are covered with a first interlayer insulating film 112b made of a silicon oxide film. The surface of the interlayer insulating film 112b is flattened and
^The film thickness of the interlayer insulating film 112b immediately above the ⁺ type source / drain diffusion layers 107b and 108b is about 300 nm.

The bit contact hole 1 reaching the N ⁺ type source / drain diffusion layer 107b is formed in the interlayer insulating film 112b.
18b is provided. Bit contact hole 118
The second embodiment is applied to the formation of b, and the opening diameter of the bit contact hole 118b is F-2d (= 8).
0 nm). The bit line 124b directly connected to the N ⁺ type source / drain diffusion layer 107b through the bit contact hole 118b is formed of the interlayer insulating film 112b through the stopper film 114ba (which is left under the bit line 124b). It is provided on the surface. Bit line 124
b is a tungsten-silicide film having a film thickness of about 150 nm, and the line width and spacing of the bit lines 124b are F.
It is.

The interlayer insulating film 112b has a flattened surface and is covered with a second interlayer insulating film 132b made of a silicon oxide film having a thickness of about 350 nm. Book second
The node contact hole 138b formed by applying the above embodiment penetrates the interlayer insulating films 132b and 112b and reaches the N ⁺ type source / drain diffusion layer 108b. The opening diameter of the node contact hole 138b is also F-2d.
(= 80 nm), the word line 105b or the bit line 124b and the node contact hole 138b.
The average spacing between the storage node electrode and the word line 105a or the bit line 1 is d, and the minimum spacing is d- "alignment margin" (= 20 nm).
Insulation separation between 24b can be secured.

N through the node contact hole 138b
^The storage node electrode 144b directly connected to the ⁺ type source / drain diffusion layer 108b is (storage.
Stopper film 13 left directly under the node electrode 144b)
It is provided on the surface of the interlayer insulating film 132b via 4ba. The storage node electrode 144b has a film thickness of 80.
The storage node electrode 144b is made of an N ⁺ -type polycrystalline silicon film of about 0 nm, and the storage node electrode 144b has a width, a length, and an interval of F,
It is 3F and F. Storage node electrode 1
The surface of 44b is covered with a capacitance insulating film 145b made of a tantalum oxide film with a thickness of about 10 nm, and this capacitance insulating film 145b is further covered with a cell plate electrode 146b made of a titanium nitride film with a thickness of about 100 nm.

Since the memory cell of the DRAM to which the present second embodiment is applied has the above-mentioned configuration, the cell size of the memory cell of this DRAM is 8F ² (which is an ideal value). = 4F × 2F).

12, FIG. 13 and FIG. 14, FIG. 15 and FIG. 1 which are schematic sectional views of the manufacturing process along the line AA in FIG.
6, FIG. 17, FIG. 18 and FIG. 19 which are schematic sectional views of the manufacturing process along the line BB of FIG. 12, and FIG. 20 and FIG. 21 which are schematic sectional views of the manufacturing process along the line CC of FIG. Referring also together, the DRA of the application example of the second embodiment and the embodiment
M is formed as follows.

First, a field oxide film 102b having a thickness of about 250 nm is formed in the element isolation region on the surface of the P-type silicon substrate 101b. A gate oxide film 103b having a film thickness of about 8 nm is formed in the element formation region on the surface of the P-type silicon substrate 101b. Each element forming region has a T shape, and these element forming regions are regularly arranged. After the word line 105b made of a tungsten polycide film having a film thickness of about 150 nm is formed, 15
N ⁺ type source / drain diffusion layers 107b and 108b having a junction depth of about 0 nm are formed. APCVD
Alternatively, a silicon oxide film is deposited on the entire surface by LPCVD or the like, and the surface thereof is planarized by CMP,
The interlayer insulating film 112b having a film thickness of about 300 nm is formed. A (first) stopper film 114b made of a silicon nitride film having a film thickness of about 50 nm is formed on the entire surface. Next, a (first) sacrificial film 152b made of a BPSG film or a PSG film having a film thickness of about 570 nm (= h) is formed on the entire surface. Aperture diameter (and minimum pattern width) F (first stage first) photoresist film pattern 1
72b is formed on the surface of the sacrificial film 152b. The first anisotropic dry etching of the first step is performed using the photoresist film 172b as a mask, and the sacrificial film 15 is formed.
2b is tapered and etched to form a dummy contact hole 182b. Dummy contact hole 182
Opening diameter at the upper end of b, opening diameter at the lower end, and taper angle θ
Are about F, F-2d (= 80 nm) and 6 °, respectively (FIG. 14 (a), FIG. 17 (a), FIG. 20).
(A)].

Next, for example, after removing the photoresist film pattern 172b, the second anisotropic dry etching in the first stage is performed, and the stopper film 114b has an opening diameter (F-2d). An opening is formed. For example, after removing the sacrificial film 152b by HF gas etching, a third anisotropic dry etching of the first stage is performed using the opening provided in the stopper film 114b as a mask to form the interlayer insulating film 112b. A contact hole 118b reaching the N ⁺ type source / drain diffusion layer 107b is formed. These contact holes 118b also have an opening diameter of F-2.
Since d (= 80 nm), these contact holes 118b also do not protrude from the N ⁺ -type source / drain diffusion layer 107b, so that the wiring pitch of the word lines 105b can be set to 2F. [Fig. 12 (a),
13, FIG. 14 (b), FIG. 17 (b), FIG.
(B)].

Thereafter, a conductor film 163b made of, for example, a tungsten-silicide film having a film thickness of about 150 nm is formed on the entire surface, and a second-step second photoresist film pattern 174b is formed on the surface of the conductor film 163b. To be done. Since the contact hole 118b has an opening diameter of F-2d, it is easy to set the minimum pattern width and the minimum interval of these photoresist film patterns 174b to F [FIG. 14 (c), FIG. 17 (c), FIG. 20 (c)].

Next, a photoresist film pattern 174
The conductor film 163b is patterned by the fourth anisotropic dry etching in the first step using b as a mask to form the bit line 124b. Further, the stopper film 114b is patterned by the fifth anisotropic dry etching in the first step, and the stopper film 114ba is left [FIG. 12, FIG. 13, FIG. 15 (a), FIG. 18 (a), FIG.
0 (d)].

Next, the surface is flattened and a (second) interlayer insulating film 132b made of a silicon oxide film having a film thickness of about 350 nm is formed. The film thickness of the interlayer insulating film 132b is the interlayer insulating film 134 (of the application example of the first embodiment).
The thickness larger than the thickness a is due to the stopper film 114ba left immediately below the bit line 124b. Film thickness 50n
(second) stopper film 13 made of a silicon nitride film of m
4b is formed on the entire surface. BPS with a film thickness of about 570 nm
(Second) sacrificial film 153 made of G film or PSG film
b is formed on the entire surface. Subsequently, a (first second stage) photoresist film pattern 175b having an opening diameter and a minimum pattern width of F is formed on the surface of the sacrificial film 153b. A second stage of first anisotropic dry etching is performed using the photoresist film 175b as a mask, and the sacrificial film 153b is taper-etched to form a (second) dummy contact hole 183b. . The diameter of the upper end of the dummy contact hole 183b is F
The opening diameter at the lower end is F-2d (= 80 nm), and the taper angle θ is about 6 ° [FIG. 15 (b), FIG. 18 (b), FIG. 20 (e)].

Next, after the photoresist film 175b is removed, a second anisotropic dry etching step is performed, and the stopper film 134b has a second opening diameter (F-
An opening with 2d) is formed. After removing the sacrificial film 153b, the second anisotropic dry etching of the second stage is performed using the opening provided in the stopper film 134b as a mask, and the stopper film 134b and the interlayer insulating film 132 are removed.
b through the interlayer insulating film 112b and the N ⁺ type source
A node contact hole 138b reaching the drain diffusion layer 108b is formed. The opening diameter of these node contact holes 138b is F-2d (= 80 nm) [FIG. 12, FIG. 13, FIG. 15 (c), FIG. 18 (c), FIG. 20 (f)].

The application to the formation of the DRAM of the above-mentioned first embodiment was applied only once. This is because, in the first embodiment, there is no step of removing the stopper film provided on the surface of the interlayer insulating film. On the other hand, in the second embodiment (for example, the bit line 124
Since there is a step of removing the stopper film (such as the fifth anisotropic dry etching in the first stage after the formation of b), it is applied to the formation of the bit contact hole 118b, and further, the node contact hole 138b. The second embodiment can be applied to the formation of the above. That is, the second embodiment can be applied a plurality of times only when anisotropic dry etching for forming each contact hole (after forming each dummy contact hole) is performed. This is because it is performed for the interlayer insulating film composed of only the same material.

Next, a conductor film 16 made of an N ⁺ -type polycrystalline silicon film (N ⁺ -type at the film formation stage) having a film thickness of about 800 nm.
5b is formed on the entire surface by LPCVD. continue,
The second photo of the second step is formed on the surface of the conductor film 165b.
A resist film pattern 176b is formed. The minimum pattern width and minimum spacing of these photoresist film patterns 176b are F, respectively, reflecting the line width and spacing of the bit lines 124b [FIG. 12, FIG. 13, FIG. 16, FIG.
9, FIG. 21].

Then, a photoresist film pattern 173 is formed.
The conductor film 165b is patterned by the second anisotropic dry etching of the second stage using b as a mask to form the storage node electrode 144b. Further, the stopper film 134b is subjected to the second stage fifth anisotropic dry etching to leave the stopper film 134ba. A capacitive insulating film 145b made of a tantalum oxide film having a film thickness of about 10 nm is formed on the entire surface by PECVD. Furthermore, a cell plate electrode 146b made of a titanium nitride film having a film thickness of about 100 nm is formed on the entire surface by sputtering, and D in the case where the first embodiment is applied.
The memory cell of RAM is completed [FIG. 12, FIG. 13].

Referring to FIGS. 22 and 23, which are schematic cross-sectional views of the manufacturing process of the semiconductor device, in the third embodiment of the present invention, the stopper film is made of a conductor film and the contact hole has a contact plug. Is formed and the stopper film is removed before the formation of the upper wiring layer, which is as follows. Also in the third embodiment, the minimum processing dimension F is 200 nm and the alignment margin is 40 nm.

First, a field oxide film 102c with a film thickness of about 250 nm and a gate oxide film 103c with a film thickness of about 8 nm are formed in the device isolation region and device forming region on the surface of the P-type silicon substrate 101c. Gate electrode 104c made of a tungsten polycide film with a thickness of about 150 nm
Then, the N ⁺ type source / drain diffusion layer 106c having a junction depth of about 150 nm is formed.
The minimum line width (gate length) and minimum interval of the gate electrode 104c and the minimum line width (gate width) and minimum interval of the N ⁺ type source / drain diffusion layer 106c are F, respectively. An interlayer insulating film 111c made of a silicon oxide film having a flattened surface and a film thickness of about 400 nm is formed on the entire surface. For example, a stopper film 115c made of a first conductor film such as an N ⁺ -type polycrystalline silicon film having a film thickness of about 50 nm is formed on the entire surface [FIG. 22 (a)]. The stopper film is not limited to the N ⁺ type polycrystalline silicon film.
The stopper film is required to function as an etching mask during anisotropic dry etching when forming a contact hole in the interlayer insulating film after the opening is formed in the stopper film, Further, since the sacrificial film formed on the stopper film can be selectively removed without any trouble, a tungsten silicide film, a titanium nitride film or the like may be used as the stopper film.

Next, a sacrificial film 151c made of a BPSG film or a PSG film with a film thickness of about 570 nm is formed on the entire surface. A (first) photoresist film pattern 171c having an opening diameter (and minimum pattern width) of F is formed on the surface of the sacrificial film 151c. First anisotropic dry etching is performed using the photoresist film 171c as a mask, and the sacrificial film 151c is taper-etched to form a dummy contact hole 181c. The opening diameter at the upper end, the opening diameter at the lower end, and the taper angle θ of the dummy contact hole 181c are F and F-2, respectively.
d (= 80 nm) and about 6 ° [FIG.
(B)].

Next, for example, after removing the photoresist film pattern 171c, the second anisotropic dry etching is performed, and the opening diameter (F-2
An opening with d) is formed. In this second anisotropic dry etching, the flow rate of chlorine (Cl ₂ ) is 200 s.
ccm, the flow rate of hydrogen bromide (HBr) is 75 sccm, the pressure is 60 Pa, and the RF power is 250 W. For example, after removing the sacrificial film 151c by HF gas etching, third anisotropic dry etching is performed using the opening provided in the stopper film 115c as a mask, and the gate electrode 104c is formed on the interlayer insulating film 111c.
Alternatively, a contact hole 117c reaching the N ⁺ type source / drain diffusion layer 106c is formed. Since these contact holes 117c also have an opening diameter of F-2d (= 80 nm), these contact holes 117c also do not protrude from the gate electrode 104c and the N ⁺ type source / drain diffusion layer 106c. As a result, also in the third embodiment, the wiring pitch of the lower wiring layer can be set to 2F [FIG. 22 (c)].

Next, the second conductor film 161c made of an N ⁺ -type polycrystalline silicon film having a film thickness of about 80 nm is formed by LPCV.
It is formed on the entire surface by D [FIG. 23 (a)]. The conductor film 161c is preferably made of the same material as the stopper film 115c.

Subsequently, the conductor film 161c and the stopper film 115c are etched back, and the contact hole 117 is formed.
Contact plug 1 made of the second conductor film in c
21 is left-formed. Then, for example, a film thickness of 150 nm
A third conductor film 162c made of a tungsten silicide film is formed on the entire surface by, for example, sputtering. A second photo film is formed on the surface of the conductor film 162c.
A resist film pattern 173c is formed. It is easy to set the minimum pattern width and the minimum interval of these second photoresist film patterns 173c to F (FIG. 23).
(B)].

Then, a photoresist film pattern 173 is formed.
The conductor film 162c is patterned by the fourth anisotropic dry etching using c as a mask, and the upper wiring layer 1
23c is formed [FIG.23 (c)].

The third embodiment has the effects of the second embodiment. Further, in the third embodiment, since the conductor film is adopted as the stopper film, when the stopper film is removed by forming an opening in the stopper film or etching back, the first and second This can be performed more easily than the embodiment. Furthermore, since the stopper film made of an insulating film (silicon nitride film) is not left between the upper wiring layer and the interlayer insulating film, the parasitic capacitance between the upper wiring layer and the lower wiring layer is not limited to the third embodiment. The embodiment is more advantageous than the first and second embodiments.

The third embodiment can also be applied to the formation of DRAM memory cells. Referring to FIG. 24, which is a schematic plan view of a memory cell of a COB type DRAM, and FIG. 25, which is a schematic cross-sectional view, a D to which the second embodiment is applied.
The memory cell of the RAM will be described. Note that FIG.
FIG. 24A is a schematic plan view showing a structure below the bit line, and FIG. 24B shows a bit contact hole, a bit line,
FIG. 3 is a schematic plan view showing a positional relationship between a node contact hole and a storage node electrode. FIG. 25 (a),
24B and 24C are schematic cross-sectional views taken along the lines AA, BB, and CC of FIG. 24.

The MOS transistor has a gate oxide film 103.
c, a word line 105c also serving as a gate electrode, an N ⁺ type source / drain diffusion layer 107c and an N ⁺ type source / drain diffusion layer 108c. Word line 105
c is formed of a tungsten polycide film having a film thickness of about 150 nm. Spacing between these word lines 105c,
The line width is F, and the wiring pitch of the word lines 105c is 2F.
It is. The depth of the junction between the N ⁺ type source / drain diffusion layers 107c and 108c is about 150 nm, and the line width of the N ⁺ type source / drain diffusion layer 108c and the minimum line width of the N ⁺ type source / drain diffusion layer 107c are It is F. These MOS transistors are covered with a first interlayer insulating film 112c made of a silicon oxide film. The surface of the interlayer insulating film 112c is flattened, and N
^The film thickness of the interlayer insulating film 112c immediately above the ⁺ type source / drain diffusion layers 107c and 108c is about 300 nm.

The bit contact hole 1 reaching the N ⁺ type source / drain diffusion layer 107c is formed in the interlayer insulating film 112c.
18c is provided. Bit contact hole 118
The third embodiment is applied to the formation of c, and the opening diameter of the bit contact hole 118c is F-2d (= 8).
0 nm). The bit contact hole 118c is made of, for example, an N ⁺ -type polycrystalline silicon film (first)
A contact plug 122 is provided. bit·
The N ⁺ type source / drain diffusion layer 107c is formed through the contact plug 122 provided in the contact hole 118c.
A bit line 124c connected to is provided on the surface of the interlayer insulating film 112c. Bit line 124c has a film thickness of 15
The tungsten silicide film having a thickness of about 0 nm is used, and the line width and the interval of the bit line 124c are F, respectively.

The inter-layer insulation film 112c has a flattened surface and is made of a second silicon oxide film having a thickness of 300 nm.
Is covered with the interlayer insulating film 132c. The node contact hole 138c to which the third embodiment is applied is
It penetrates through the interlayer insulating films 132c and 112c and reaches the N ⁺ type source / drain diffusion layer 108c. The opening diameter of the node contact hole 138c is F-2d (= 80n
m). A (second) contact plug 142 made of, for example, an N ⁺ -type polycrystalline silicon film is provided in the node contact hole 138c.

The storage node electrode 144c connected to the N ⁺ type source / drain diffusion layer 108c through the contact plug 142 provided in the node contact hole 138c is provided on the surface of the interlayer insulating film 132c. . The storage node electrode 144c has a film thickness of 800
It consists of nm of N ⁺ -type polycrystalline silicon film, the storage node electrode 144c of the width, length and spacing F, 3
F and F. Storage node electrode 14
The surface of 4c is covered with a capacitance insulating film 145c made of a tantalum oxide film with a thickness of about 10 nm, and this capacitance insulating film 145c is further covered with a cell plate electrode 146c made of a titanium nitride film with a thickness of about 100 nm.

The cell size of the memory cell of the DRAM to which the third embodiment is applied is also an ideal value of 8F.
² (= 4F × 2F).

Referring to FIGS. 26 and 27 which are schematic cross-sectional views of the manufacturing process of the semiconductor device, in the fourth embodiment of the present invention, the stopper film is made of a conductor film and the upper wiring layer is made of a stopper film. It has a feature that it is composed of a laminated structure film as a lower layer, and is as follows. Also in the fourth embodiment, the minimum processing dimension F is 200 nm and the alignment margin is 40 nm.

First, a field oxide film 102d with a film thickness of about 250 nm and a gate oxide film 103d with a film thickness of about 8 nm are formed in the device isolation region and device forming region on the surface of the P-type silicon substrate 101d. Gate electrode 104d made of a tungsten polycide film with a thickness of about 150 nm
Then, the N ⁺ type source / drain diffusion layer 106d having a junction depth of about 150 nm is formed.
The minimum line width (gate length) and minimum interval of the gate electrode 104d and the minimum line width (gate width) and minimum interval of the N ⁺ type source / drain diffusion layer 106d are F, respectively. An interlayer insulating film 111d having a flattened surface and made of a silicon oxide film having a film thickness of about 400 nm is formed on the entire surface. For example, a stopper film 115d made of a first conductor film such as an N ⁺ -type polycrystalline silicon film having a film thickness of about 50 nm is formed on the entire surface [FIG. 26 (a)]. Also in the fourth embodiment, the stopper film is not limited to the N ⁺ type polycrystalline silicon film.

Next, a sacrificial film 151d made of a BPSG film or a PSG film with a film thickness of about 570 nm is formed on the entire surface. A (first) photoresist film pattern 171d having an opening diameter (and minimum pattern width) of F is formed on the surface of the sacrificial film 151d. First anisotropic dry etching is performed using the photoresist film 171d as a mask, and the sacrificial film 151d is taper-etched to form a dummy contact hole 181d. The opening diameter at the upper end, the opening diameter at the lower end, and the taper angle θ of the dummy contact hole 181d are F and F-2, respectively.
d (= 80 nm) and about 6 ° (FIG. 26).
(B)].

Next, for example, after removing the photoresist film pattern 171d, a second anisotropic dry etching is performed, and the opening diameter (F-2
An opening with d) is formed. For example, the sacrificial film 151
After removing d by HF gas etching, third anisotropic dry etching is performed using the opening provided in the stopper film 115d as a mask, and the interlayer insulating film 11 is formed.
A contact hole 117d reaching the gate electrode 104d or the N ⁺ type source / drain diffusion layer 106d is formed in 1d. Since these contact holes 117d also have an opening diameter of F-2d (= 80 nm), these contact holes 117d also do not protrude from the gate electrode 104d and the N ⁺ type source / drain diffusion layer 106d. As a result, also in the fourth embodiment, the wiring pitch of the lower wiring layer can be set to 2F (FIG. 26).
(C)].

Next, for example, the second conductor film 161d made of a tungsten silicide film having a film thickness of about 150 nm.
Are formed on the entire surface by sputtering. A second photoresist film pattern 173d is formed on the surface of the conductor film 161d. It is easy to set the minimum pattern width and the minimum interval of these second photoresist film patterns 173d to F [FIG. 27 (a)].

Then, a photoresist film pattern 173 is formed.
The conductor film 161d is patterned by the fourth anisotropic dry etching using d as a mask.
1da remains. Further, the stopper film 115d is patterned by the fifth anisotropic dry etching,
The stopper film 115da is left. As a result, the upper wiring layer 123d in which the conductor film 161da is laminated on the stopper film 115da is formed [FIG. 27 (c)].

The fourth embodiment has the effects of the third embodiment.

Referring to FIG. 28, which is a schematic plan view of a memory cell of a COB type DRAM, and FIG. 29, which is a schematic cross-sectional view, the structure of the memory cell of a DRAM to which the fourth embodiment is applied. Will be described. 28A is a schematic plan view showing the structure below the bit line.
(B) is a schematic plan view showing the positional relationship among bit contact holes, bit lines, node contact holes, and storage node electrodes. 29 (a), (b) and (c) are schematic sectional views taken along the lines AA, BB and CC in FIG.

The MOS transistor has a gate oxide film 103.
d, a word line 105d also serving as a gate electrode, an N ⁺ type source / drain diffusion layer 107d and an N ⁺ type source / drain diffusion layer 108d. Word line 105
d is formed of a tungsten polycide film having a thickness of about 150 nm. Spacing between these word lines 105d,
The line width is F, and the wiring pitch of the word lines 105d is 2F.
It is. The depth of the junction between the N ⁺ type source / drain diffusion layers 107d and 108d is about 150 nm, and the line width of the N ⁺ type source / drain diffusion layer 108d and the minimum line width of the N ⁺ type source / drain diffusion layer 107d are It is F. These MOS transistors are covered with a first interlayer insulating film 112d made of a silicon oxide film. The surface of the interlayer insulating film 112d is flattened, and N
^The film thickness of the interlayer insulating film 112d immediately above the ⁺ type source / drain diffusion layers 107d and 108d is about 300 nm.

A bit contact hole 1 reaching the N ⁺ type source / drain diffusion layer 107d is formed in the interlayer insulating film 112d.
18d is provided. Bit contact hole 118
The fourth embodiment is applied to the formation of d, etc.,
The opening diameter of the bit contact hole 118d is F-2d (=
80 nm). The bit line 124d, which is directly connected to the N ⁺ type source / drain diffusion layer 107d through the bit contact hole 118d and extends on the surface of the interlayer insulating film 112d, has a laminated structure. The bit line 124d in the bit contact hole 118d is made of a laminated film of a barrier film 163d and a conductor film 164, and the bit line 124d on the surface of the interlayer insulating film 112d is a stopper film 116d and a barrier film formed respectively. Membrane 16
It is composed of a laminated film of 3d and a conductor film 164. The stopper film 116d is made of, for example, an N ⁺ -type polycrystalline silicon film having a film thickness of about 50 nm, the barrier film 163d is made of a laminated film of a titanium film and a titanium nitride film, and the conductor film 164 is, for example, on the surface of the interlayer insulating film 112d. And a titanium silicide film having a thickness of about 150 nm. The line width and spacing of the bit lines 124d are F, respectively.

The interlayer insulating film 112d is a second silicon oxide film having a flattened surface and having a film thickness of 350 nm.
Is covered with the interlayer insulating film 132d. The node contact hole 138d to which the second embodiment is applied is
Interlayer insulating film 1 having an opening diameter of F-2d (= 80 nm)
It penetrates through 32d and 112d and reaches the N ⁺ type source / drain diffusion layer 108d. The cylinder type storage node electrode 144d is formed on the N ⁺ type source / drain diffusion layer 108 through the node contact hole 138d.
It is directly connected to d.

The storage node electrode 144d has a film thickness of 50 left directly covering the surface of the interlayer insulating film 132d.
The thickness of the stopper film 135da made of an N ⁺ -type polycrystalline silicon film of about nm and the film thickness 1 which directly covers the surface of the stopper film 135da and fills the inside of the node contact hole 138d.
And the conductive film 165da consisting 00nm approximately N ⁺ -type polycrystalline silicon film, a conductive film 167 made of N ⁺ -type polycrystalline silicon film having a thickness of about 50nm to cover the side surface of the stopper film 135da and conductor film 165da directly Consists of.
The surface of the storage node electrode 144d has a film thickness of 10 nm.
And a capacitance insulating film 145d made of a tantalum oxide film, and the capacitance insulating film 145d has a film thickness of 100.
Cell plate electrode 1 made of titanium nitride film of about nm
It is covered by 46d.

The cell size of the memory cell of the DRAM to which the fourth embodiment is applied is also an ideal value of 8F.
² (= 4F × 2F). Further, when forming the cylinder type storage node electrode, it is easy to form a thick laminated conductor film including a stopper film on the second interlayer insulating film. The application of this embodiment is more advantageous than the application of other embodiments and embodiments.

28, 29, 30 and 31, which are schematic cross-sectional views of the manufacturing process along the line AA in FIG. 28, and FIG.
32, which is a schematic cross-sectional view of the manufacturing process on the CC line of FIG. 8, how the storage node electrode in the application example of the fourth embodiment is formed will be described.

First (consisting of N ⁺ type polycrystalline silicon film)
A contact hole 118d reaching the N ⁺ type source / drain diffusion layer 107d is formed in the first interlayer insulating film 112d by utilizing the opening provided in the stopper film, and a bit line 124d is formed. Second interlayer insulating film 13
2d, a second stopper film 136d (made of an N ⁺ type polycrystalline silicon film) is formed. After that, a second sacrificial film or the like is formed, and by using a dummy contact hole or the like formed in the sacrificial film, a node contact hole 138d reaching the N ⁺ type source / drain diffusion layer 108d is formed [FIG. 28, FIG. 29, FIG. 30 (a), and FIG.
(A)].

Next, a conductor film 165d made of an N ⁺ type polycrystalline silicon film having a film thickness of about 50 nm is formed on the entire surface by LPCVD. PSG film 1 with a film thickness of about 400 nm
54 is an LP made from TEOS, TMP, and ozone
It is formed on the entire surface by CVD. Then, the PSG film 15
A photoresist film pattern 176d having a width of F, a length of 3F and an interval of F is formed on the surface of FIG. 4 [FIGS. 30 (b) and 32 (b)].

Using the photoresist film pattern 176d as a mask, the PSG film 154 is selectively subjected to anisotropic dry etching, leaving the PSG film 155. further,
The conductor film 165d and the stopper film 136d are selectively anisotropically dry-etched using the photoresist film pattern 176d as a mask, and the conductor film 165da and the stopper film 136da are left. After the photoresist film pattern 176d is removed, the conductor film 166 made of an N ⁺ -type polycrystalline silicon film with a film thickness of about 50 nm.
Are formed on the entire surface by LPCVD [FIG.
(A), FIG. 32 (c)].

Next, the conductor film 166 is etched back, and the conductor film 167 covering the side surface of the PSG film 155 is left [FIG. 31 (b), FIG. 32 (d)]. This allows
The formation of the storage node electrode 144d of this application example including the stopper film 135da, the conductor film 165da, and the conductor film 167 is completed.

Next, the PSG film 155 is removed by HF gas etching. A capacitive insulating film 145d made of a tantalum oxide film with a thickness of about 10 nm is formed by PECVD, and the surface of the storage node electrode 144d is covered with the capacitive insulating film 145d. Further, a cell plate electrode 146d made of a titanium nitride film having a film thickness of about 100 nm is formed by sputtering, and the surface of the capacitor insulating film 145d is covered by the cell plate electrode 146d, so that the memory cell of the DRAM according to the present application example. The formation is completed [FIGS. 28 and 29].

[0109]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the stopper film is formed on the interlayer insulating film covering the lower wiring layer, and the sacrificial film is further formed. Due to the taper etching using the first anisotropic dry etching, the dummy bottom opening diameter is smaller than the top opening diameter.
Contact holes are formed in the sacrificial film. By the second anisotropic dry etching, an opening having an opening diameter equal to the lower end opening diameter is formed in the stopper film. At least a third anisotropic dry film utilizing the opening provided in the stopper film
By etching, a contact hole having an opening diameter equal to the lower end opening diameter is formed in the interlayer insulating film. Therefore, by setting the upper end opening diameter to be equal to the minimum processing dimension F, it becomes easy to set the wiring pitch of the lower wiring layer to 2F.

Further, by applying the present invention to the formation of at least the node contact holes of the memory cell of the DRAM, it becomes easy to set the wiring pitch of the word lines to 2F and the cell size to 10F ² or less. .

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the manufacturing process of the first embodiment.

FIG. 3 is a schematic plan view of an application example of the first embodiment.

FIG. 4 is a schematic sectional view of an application example of the first embodiment.

FIG. 5 is a schematic cross-sectional view of the manufacturing process of the application example of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along the line AA of FIG. 3;

FIG. 6 is a schematic sectional view of a manufacturing process of an application example of the first embodiment, and is a schematic sectional view of the manufacturing process taken along the line AA of FIG. 3;

FIG. 7 is a schematic sectional view of a manufacturing process of an application example of the first embodiment, and is a schematic sectional view of the manufacturing process taken along the line BB of FIG. 3;

FIG. 8 is a schematic sectional view of a manufacturing process of an application example of the first embodiment, and is a schematic sectional view of the manufacturing process taken along the line BB of FIG. 3;

FIG. 9 is a schematic cross-sectional view of the manufacturing process of the application example of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along the line CC of FIG. 3;

FIG. 10 is a schematic sectional view of a manufacturing process according to the second embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of the manufacturing process of the second embodiment.

FIG. 12 is a schematic plan view of an application example of the second embodiment.

FIG. 13 is a schematic sectional view of an application example of the second embodiment.

FIG. 14 is a schematic sectional view of a manufacturing process of an application example of the second embodiment, and is a schematic sectional view of the manufacturing process taken along the line AA of FIG. 12;

FIG. 15 is a schematic sectional view of a manufacturing process of an application example of the second embodiment, and is a schematic sectional view of the manufacturing process taken along the line AA of FIG. 12;

16 is a schematic sectional view of a manufacturing step of an application example of the second embodiment, and is a schematic sectional view of the manufacturing step taken along the line AA of FIG.

FIG. 17 is a schematic sectional view of a manufacturing process of an application example of the second embodiment, and is a schematic sectional view of the manufacturing process taken along the line BB of FIG. 12;

FIG. 18 is a schematic sectional view of a manufacturing step of an application example of the second embodiment, and is a schematic sectional view of the manufacturing step taken along the line BB of FIG. 12;

FIG. 19 is a schematic sectional view of a manufacturing step of an application example of the second embodiment, and is a schematic sectional view of the manufacturing step taken along the line BB of FIG. 12;

FIG. 20 is a schematic sectional view of a manufacturing step of an application example of the second embodiment, and is a schematic sectional view of a manufacturing step taken along the line CC of FIG. 12;

21 is a schematic sectional view of a manufacturing step of an application example of the second embodiment, and is a schematic sectional view of a manufacturing step taken along a line CC of FIG.

FIG. 22 is a schematic cross-sectional view of the manufacturing process according to the third embodiment of the present invention.

FIG. 23 is a schematic cross-sectional view of the manufacturing process of the third embodiment.

FIG. 24 is a schematic plan view of an application example of the third embodiment.

FIG. 25 is a schematic sectional view of an application example of the third embodiment.

FIG. 26 is a cross-sectional schematic view of the manufacturing process according to the fourth embodiment of the present invention.

FIG. 27 is a schematic cross-sectional view of the manufacturing process of the fourth embodiment.

FIG. 28 is a schematic plan view of an application example of the fourth embodiment.

FIG. 29 is a schematic sectional view of an application example of the fourth embodiment.

FIG. 30 is a schematic sectional view of a manufacturing step of an application example of the fourth embodiment, and is a schematic sectional view of a manufacturing step taken along the line AA of FIG. 28.

FIG. 31 is a schematic sectional view of a manufacturing step of an application example of the fourth embodiment, and is a schematic sectional view of the manufacturing step taken along the line AA of FIG. 28.

32 is a schematic sectional view of a manufacturing step of an application example of the fourth embodiment, and is a schematic sectional view of the manufacturing step taken along the line CC of FIG. 28. FIG.

FIG. 33 is a schematic cross-sectional view of the manufacturing process of the semiconductor device, for explaining the conventional manufacturing method of the semiconductor device.

FIG. 34 is a cross-sectional schematic diagram of the manufacturing process of the semiconductor device, for illustrating the problem of the conventional manufacturing method.

FIG. 35 is a cross-sectional schematic diagram of the manufacturing process of the semiconductor device, for illustrating the problem of the conventional manufacturing method.

[Explanation of symbols]

101a to 101d, 201 P-type silicon substrate 102a to 102d, 202 Field oxide film 103a to 104d Gate oxide film 104a to 104d Gate electrode 105a to 105d Word line 106a to 106d, 107a to 107d, 108a to
108d, 208, 208a N ⁺ type source / drain diffusion layers 111a-111d, 112a-112d, 132a-
132d, 212, 232, 232a Interlayer insulating film 113a, 113b, 113ba, 114b, 114b
a, 115c, 115d, 115da, 116d, 13
4a, 134b, 134ba, 136d, 136da
Stopper film 117a to 117d, 238a Contact hole 118a to 118d Bit contact hole 119, 239, 239a Insulating film spacer 121, 122, 142 Contact plug 123a to 123d, 276aa, 276ab Upper wiring layer 124a to 124d, 224 Bit line 138a ˜138d, 238 node contact holes 144a˜144d, 244 storage node electrodes 145a˜145d capacitance insulating film 146a˜146d cell plate electrodes 151a, 151aa, 151b˜151d, 152
b, 153a, 153aa, 153b Sacrificial film 154, 155 PSG film 161a to 161d, 161da, 162c, 163
b, 164, 165a, 165b, 165d, 165d
a, 166, 167, 264, 264aa, 264ab
Conductor film 163d Barrier film 171a to 171d, 172b, 173a to 173c,
174b, 175a, 175b, 176a, 176b,
275, 276, 276aa, 276ab Photoresist film patterns 181a, 181b, 181d, 182b, 183a,
183b Dummy contact hole 224a Intermediate wiring layer 255 Insulating film 261 Conductor film pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8242 H01L 27/10 681B 681A

Claims (8)

[Claims] 1. A step of forming a lower wiring layer on the surface of a semiconductor substrate or on the surface and forming an interlayer insulating film covering the surface of the semiconductor substrate; and forming a stopper film covering the surface of the interlayer insulating film, Forming a sacrificial film having a required film thickness of a material capable of performing anisotropic dry etching selectively with respect to the stopper film, and forming a first opening diameter on the surface of the sacrificial film. Forming a first photo resist film pattern, and the first anisotropic dry etching using the first photo resist film pattern as a mask, the upper end has a first opening diameter, Forming a dummy contact hole having a second opening diameter whose lower end is smaller than the first opening diameter in the sacrificial film; removing the first photoresist film pattern; Anisotropic dry etch Thereby forming an opening having a second opening diameter in the stopper film, selectively removing the sacrificial film, and performing third anisotropic dry etching using the opening as a mask. Forming a contact hole having the second opening diameter and reaching the lower wiring layer in the interlayer insulating film, forming a conductor film on the entire surface, and masking the second photoresist film pattern. And a step of forming an upper wiring layer made of the conductor film by the fourth anisotropic dry etching described above. 2. The minimum processing dimension (=
F), wherein the minimum line width and the minimum spacing of the lower wiring layer are F, and the minimum line width and the minimum spacing of the upper wiring layer are F, respectively.
The manufacturing method of the semiconductor device described in the above. 3. A step of forming a lower wiring layer having a minimum line width and a minimum spacing of F on the surface of the semiconductor substrate and forming an interlayer insulating film made of a silicon oxide film on the entire surface, and a silicon nitride film. Forming a stopper film made of F on the surface of the interlayer insulating film and forming a sacrificial film having a required thickness of a PSG film or a BPSG film on the entire surface; and forming a sacrificial film of F on the surface of the sacrificial film. The step of forming a first photoresist film pattern having an opening diameter of 1 and the first anisotropic dry etching using the first photoresist film pattern as a mask, the upper end of the first photoresist film pattern is Forming a dummy contact hole having an opening diameter and a lower end having a second opening diameter narrower than the first opening diameter in the sacrificial film; and removing the first photoresist film pattern. A step of forming an opening having a second opening diameter in the stopper film by second anisotropic dry etching; a step of selectively removing the sacrificial film; Forming a contact hole having the second opening diameter and reaching the lower wiring layer in the interlayer insulating film by a third anisotropic dry etching using the mask as a mask, and forming a conductor film on the entire surface. Then, the conductor film is patterned by fourth anisotropic dry etching using the second photoresist film pattern as a mask to form an upper wiring layer having a minimum line width and a minimum spacing of F, respectively. A method of manufacturing a semiconductor device, comprising: 4. The interlayer insulating film comprises a first interlayer insulating film and a second interlayer insulating film covering the first interlayer insulating film,
4. An intermediate wiring layer having a minimum distance of F is formed on the surface of the first interlayer insulating film.
The manufacturing method of the semiconductor device described in the above. 5. The semiconductor device according to claim 3, further comprising a step of patterning the stopper film by fifth anisotropic dry etching using the second photoresist film pattern as a mask. Production method. 6. A step of forming a lower wiring layer having a minimum line width and a minimum spacing of F on the surface of the semiconductor substrate, and forming an interlayer insulating film made of a silicon oxide film on the entire surface, A step of forming a stopper film made of a conductor film on the surface of the interlayer insulating film and a sacrificial film having a required film thickness made of a PSG film or a BPSG film on the entire surface; A step of forming a first photoresist film pattern having a first opening diameter consisting of, and a first anisotropic dry etching using the first photoresist film pattern as a mask, Forming a dummy contact hole having a first opening diameter and a lower end having a second opening diameter narrower than the first opening diameter in the sacrificial film; and the first photoresist film pattern. Remove A step of forming an opening having a second opening diameter in the stopper film by second anisotropic dry etching; a step of selectively removing the sacrificial film; Forming a contact hole having the second opening diameter and reaching the lower wiring layer in the interlayer insulating film by a third anisotropic dry etching using the mask as a mask; A step of forming a second conductor film, and a step of etching back the second conductor film and the stopper film to leave a contact plug made of the second conductor film in the contact hole. , A third conductor film is formed on the entire surface, and the third conductor film is patterned by the fourth anisotropic dry etching using the second photoresist film pattern as a mask to obtain the minimum line width. And the minimum interval And a step of forming an upper wiring layer made of F, respectively. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the second conductor film and the third conductor film are made of the same material. 8. A step of forming a lower wiring layer having a minimum line width and a minimum spacing of F on the surface of the semiconductor substrate, and forming an interlayer insulating film made of a silicon oxide film on the entire surface. A step of forming a stopper film made of a conductor film on the surface of the interlayer insulating film and a sacrificial film having a required film thickness made of a PSG film or a BPSG film on the entire surface; A step of forming a first photoresist film pattern having a first opening diameter consisting of, and a first anisotropic dry etching using the first photoresist film pattern as a mask, Forming a dummy contact hole having a first opening diameter and a lower end having a second opening diameter narrower than the first opening diameter in the sacrificial film; and the first photoresist film pattern. Remove A step of forming an opening having a second opening diameter in the stopper film by second anisotropic dry etching; a step of selectively removing the sacrificial film; Forming a contact hole having the second opening diameter and reaching the lower wiring layer in the interlayer insulating film by the third anisotropic dry etching using the mask as a mask; The second conductive film and the stopper film are formed by a fourth anisotropic dry etching and a fifth anisotropic dry etching which form a body film and use the second photoresist film pattern as a mask. To form an upper wiring layer having a laminated structure, the uppermost wiring layer having a minimum line width and a minimum spacing F, and a method for manufacturing a semiconductor device.