JPH09307441A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To utilize the resolution of an A/D converter optimizingly by adjusting an amplification factor of an amplifier so that a maximum amplitude of the amplifier is matched with an input voltage range of the A/D converter and then, adjusting the offset of the amplifier. SOLUTION: A maximum amplitude measurement circuit 6a obtains a 1st level difference between a 1st output signal 5a when a signal of a minimum level in analog input signals is inputted to an amplifier 2 and a 2nd output signal 5b, when a signal of a maximum level in the analog input signals is inputted to the amplifier 2. An input voltage range measurement 6b obtains a 2nd level difference between a maximum allowable input voltage Vrefh of an A/D converter and a minimum allowable input voltage Vrefl of the A/D converter. An amplification factor adjustment circuit 4 adjusts the simplification factor of the amplifier 2 so that the 1st level difference is equal to the 2nd level difference. The amplification factor of the amplifier 2 is confirmed when the level differences are equal to each other. Then the offset of the amplifier 2 is adjusted at the confirmed amplification factor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for amplifying an analog signal, converting it into a digital signal and outputting the digital signal.

[0002]

2. Description of the Related Art Conventionally, in the field of facsimiles, scanners, etc., a signal which an analog image signal from a photoelectric conversion sensor is amplified by an amplifier, converted into a digital signal by an AD converter (analog / digital converter), and output. Processing circuits are widely used. With this kind of signal processing circuit,
In order to perform high-accuracy signal processing that makes full use of the resolution of the AD converter, it is desirable that the maximum amplitude of the amplifier and the input voltage range of the AD converter be operated in a matched state. Therefore, various proposals have been made conventionally, and for example, Japanese Patent Laid-Open No. 2-116265 discloses the following signal processing circuit.

FIG. 4 is a block diagram showing an example of a conventional signal processing circuit described in the above publication. As shown in FIG. 4, in this signal processing circuit, the analog image signal input from the photoelectric conversion sensor 1 is AGC whose amplification degree can be adjusted.
The signal is amplified by an (Automatic Gain Control) amplifier 20, converted into a digital signal by the AD converter 3, and output from the output terminal 10. The output signal of the AD converter 3 is also input to the memory 17 and the amplification degree adjusting circuit 4.

Next, the operation of this signal processing circuit will be described. First, the output signal (dark output signal) of the photoelectric conversion sensor 1 when the document illuminating light is turned off is amplified by the AGC amplifier 20 and converted into a digital signal (dark digital signal) by the AD converter 3. The dark digital signal is stored in the memory 17. On the other hand, the amplification degree adjusting circuit 4 detects a white reference signal based on a white reference signal serving as a reference, for example, a digital signal output from the AD converter 3 when the reference white plate is read by the photoelectric conversion sensor 1, and the white reference signal is detected. The AGC amplifier 2 outputs an amplification degree adjustment signal for adjusting the amplification degree of the AGC amplifier 20 so that the reference signal has a constant level.
Enter 0. This amplification degree adjustment signal is also input to the multiplier 18, and the multiplier 18 is input according to this amplification degree adjustment signal.
The multiplier of is determined. Simultaneously with the start of scanning the document, the dark digital signal stored in the memory 17 is read. The read dark digital signal is corrected by being multiplied by the multiplier in the multiplier 18,
It is converted into an analog signal by the DA (digital / analog) converter 19, and the reference voltage Vref of the AD converter 3 is converted.
Is entered as Therefore, the operation of the AD converter 3 for converting the analog signal output from the AGC amplifier 20 into digital is performed on the basis of this analog signal voltage, that is, the analog voltage corresponding to a product of the dark-time digital signal from the memory 17 multiplied by a multiplier. Be seen.

However, in the above signal processing circuit,
When the white reference signal changes due to aging of the illuminance of the illumination light, the multiplier of the multiplier 18 is also changed, and the reference voltage Vref of the AD converter 3 is also corrected accordingly. Therefore, the input voltage range of the AD converter 3 is narrowed depending on the correction amount, and the AD converter 3 is used in a state where the resolution originally possessed by the AD converter 3 cannot be fully utilized, which may reduce the AD conversion accuracy. .

In addition to the above example, for example, the following signal processing circuit has been proposed. FIG. 5 is a block diagram showing another example of the conventional signal processing circuit. As shown in FIG. 5, in this signal processing circuit, the dark reference signal input from the photoelectric conversion sensor 1 in advance is held in the sample hold circuit 20, and then the white reference signal is input from the photoelectric conversion sensor 1. The analog subtractor 21 obtains the offset adjustment signal of the AGC amplifier 20 based on the white reference signal and the dark output signal held in the sample hold circuit 20. Next, the white reference signal input from the sensor 1 is A
The signal is amplified by the GC amplifier 20 and converted into a digital signal by the AD converter 3, and the digital signal is input to the amplification degree adjusting circuit 4, and the amplification degree adjusting circuit 4 generates an amplification degree adjusting signal based on the digital signal. The amplification degree of the AGC amplifier 20 is adjusted by the amplification degree adjustment signal.

However, in this signal processing circuit, the offset adjustment is first performed, and then the amplification degree adjustment is performed, so that the offset previously adjusted is affected by this amplification degree adjustment. Therefore, if the offset adjustment is performed after the amplification degree is adjusted, the amplification degree that has been adjusted at the bending angle is distorted. No matter how many times the offset adjustment and the amplification degree adjustment are performed, it is difficult to completely eliminate the deviation between the two. As described above, the circuit of FIG. 5 has a problem that the offset adjustment and the amplification degree adjustment cannot be made compatible with each other, and the resolution originally possessed by the AD converter cannot be maximized.

[0008]

SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a highly accurate signal processing circuit which can make the most of the resolution of an AD converter.

[0009]

A signal processing circuit according to the present invention which achieves the above object, comprises an amplifier which amplifies and outputs an analog signal and which can be freely adjusted in amplification degree and offset.
In a signal processing circuit including an AD converter for inputting the output signal of the amplifier and converting it into a digital signal, a signal from the amplifier when the minimum level signal of the analog input signals is input to the amplifier. Maximum amplitude measurement for determining a first level difference between a first output signal and a second output signal from the amplifier when the highest level signal of the analog input signal is input to the amplifier. A circuit, an input voltage range measuring circuit for determining a second level difference between the maximum allowable input voltage of the AD converter and the minimum allowable input voltage of the AD converter, and the first level difference having the second level difference. Amplification level adjusting circuit that adjusts the amplification level of the amplifier so as to be equal to the level difference between the output level of one of the first output signal and the second output signal and the minimum allowable input voltage. And a comparator that compares one of the maximum allowable input voltages with one of the allowable input voltages on the side corresponding to the one output signal, and the level of the one output signal is equal to the one allowable input voltage. And an offset adjusting circuit for adjusting the offset of the amplifier.

Here, the signal processing circuit includes a sample hold circuit for holding at least one of the minimum level signal and the maximum level signal of the analog input signal in a stage preceding the amplifier, It may be provided with a multiplexer for selecting any one signal of the output signal of the sample hold circuit and the analog input signal bypassing the sample hold circuit.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram showing a first embodiment of a signal processing circuit of the present invention. In this signal processing circuit, an analog signal input from the sensor 1 is amplified by an amplifier 2 whose amplification degree and offset can be freely adjusted, converted into a digital signal by an AD converter 3, and output from an output terminal 10.

Hereinafter, the amplification degree adjustment and the offset adjustment of the signal processing circuit of this embodiment will be described in detail with reference to the circuit diagram of FIG. First, the minimum level signal of the analog input signal is taken into the signal processing circuit. That is, for example, in the case of processing the image signal from the photoelectric conversion sensor 1, the dark reference signal is input to the amplifier 2 which can freely adjust the amplification degree and the offset. In order to input the dark reference signal, the illumination light (not shown) is turned off or the photoelectric conversion sensor 1 is shielded, and then the output signal of the photoelectric conversion sensor 1 is input to the amplifier 2.

The amplifier 2 whose amplification degree and offset can be freely adjusted is constructed, for example, as shown in FIG. FIG. 2 is a circuit diagram of an amplifier used in this embodiment, which is capable of freely adjusting the amplification degree and the offset. As shown in FIG. 2, the amplifier 2 includes an operational amplifier 11, a fixed resistor 12, a variable resistor 13, an input terminal 14, a control signal input terminal 15, and an output terminal 16. In this amplifier 2, the amplification degree determined by the resistance ratio between the fixed resistor 12 and the variable resistor 13 is adjusted by changing the resistance value of the variable resistor 13, and the control signal input from the control signal input terminal 15 is used. The offset is adjusted.

Returning to FIG. 1, the description will be continued. The dark reference signal output from the amplifier 2 is the sample hold circuit 5a.
Is held. Next, the maximum level signal of the analog input signals is taken into the signal processing circuit. That is, when processing the image signal from the photoelectric conversion sensor 1, the white reference signal is input to the amplifier 2. To input the white reference signal, the reference white plate is read by the photoelectric conversion sensor 1 and the output signal thereof is input to the amplifier 2. The white reference signal output from the amplifier 2 is held in the sample hold circuit 5b.

The output signals of the sample hold circuit 5a and the sample hold circuit 5b are the first analog subtractor 6a.
And the level difference between the dark reference signal and the white reference signal (first level difference), that is, the signal corresponding to the maximum amplitude of the amplifier 2 is output from the first analog subtractor 6a. On the other hand, the maximum allowable input voltage Vrefh of the AD converter 3
And the minimum allowable input voltage Vrefl are subtracted by the second analog subtractor 6b, and the level difference between the maximum allowable input voltage Vrefh and the minimum allowable input voltage Vrefl (second level difference), that is, the input voltage of the AD converter 3 A signal corresponding to the range is output from the second analog subtractor 6b. The maximum allowable input voltage Vrefh and the minimum allowable input voltage V
The refl may be stored in the signal processing circuit, or may be input from outside whenever necessary.

The output signal from the first analog subtractor 6a (first level difference) and the output signal from the second analog subtractor 6b (second level difference) are input to the first comparator 7a. Then, the comparison result is input to the amplification degree adjusting circuit 4. The amplification degree adjusting circuit 4 adjusts the amplification degree of the amplifier 2 so that the first level difference becomes equal to the second level difference. Specifically, if the maximum amplitude of the amplifier 2 is larger than the input voltage range of the AD converter 3, the set value of the amplification degree of the amplifier 2 is lowered, and if the maximum amplitude is larger, the set value of the amplification degree is raised. In this way, a series of operations starting from the acquisition of the dark reference signal and the white reference signal are repeated under the newly set amplification degree. In this way, the adjustment of the amplification degree is continued until the first level difference and the second level difference become equal. Thus, the amplification degree of the amplifier 2 is determined when the first level difference becomes equal to the second level difference. In the case of the method of controlling the amplification degree of the amplifier 2 with a digital value, the amplification degree adjusting circuit 4 may have a simple circuit configuration such as an up-down counter.

Next, the offset adjustment of the amplifier 2 is performed under the determined amplification degree. In the present embodiment, the dark reference voltage input from the sensor 1 and amplified by the amplifier 2 and the minimum allowable input voltage Vrefl of the AD converter 3 are input to the second comparator 7b, and the comparison result is offset adjusted. Input to the circuit 8. The offset adjusting circuit 8 adjusts the offset of the amplifier 2 so that the dark reference voltage and the minimum allowable input voltage Vrefl are equal.

In this embodiment, as a result of the above-mentioned amplification degree adjustment, the maximum amplitude of the amplifier 2 and the input voltage range of the AD converter 3 match, so the dark reference voltage and the AD converter 3 are matched.
Instead of the minimum allowable input voltage Vrefl of, the white reference signal and the maximum allowable voltage Vrefh of the AD converter 3 may be used to perform the offset adjustment. A circuit such as a DA converter can be used as the offset adjustment circuit 8.

Next, a second embodiment of the signal processing circuit of the present invention will be described. FIG. 3 is a circuit diagram showing a second embodiment of the signal processing circuit of the present invention. As shown in FIG. 3, the present embodiment is similar to the signal processing circuit of the first embodiment shown in FIG. 1, and therefore only the portions different from the first embodiment will be described below. explain.

In this embodiment, the third sample-hold circuit 5c and the fourth sample-hold circuit 5c are provided between the photoelectric conversion sensor 1 and the amplifier 2.
The sample and hold circuit 5d and the multiplexer 9 are inserted. The third sample and hold circuit 5c holds the minimum level signal of the analog input signal, and the fourth sample and hold circuit 5d holds the maximum level signal of the analog input signal. Multiplexer 9
Are the third and fourth sample and hold circuits 5c,
One of the output signal of 5d and the analog input signal bypassing the third and fourth sample hold circuits 5c and 5d is selected and input to the amplifier 2.

By configuring the signal processing circuit as described above, when processing the minimum level signal of the analog input signal, that is, the image signal from the photoelectric conversion sensor, the dark reference signal is used as the third sample hold. The signal of the highest level among the analog input signals, which is held in the circuit 5c,
That is, when processing the image signal from the photoelectric conversion sensor, the white reference signal is held in the fourth sample hold circuit 5d, and when the dark reference signal is sampled in the first sample hold circuit 5a, the multiplexer 9 is used. Of the white reference signal to the second sample and hold circuit 5c.
When sampling to b, the input position of the multiplexer 9 is switched to the side of the fourth sample hold circuit 5d. At the time of actual signal processing, the input position of the multiplexer 9 is set to the sample hold circuits 5c and 5c.
Switch to a position that bypasses d. By doing so, it is not necessary to light-shield the photoelectric conversion sensor or read the reference white plate many times when adjusting the amplification degree of the amplifier 2, and the operability can be improved.

In each of the above embodiments, the first sample hold circuit 5a and the second sample hold circuit 5b are used.
Although the example in which the two sample and hold circuits are provided has been described, the functions of the two sample and hold circuits 5a and 5b can be shared by one sample and hold circuit. That is, the minimum level signal and the maximum level signal may be alternately held in one sample hold circuit. However, when the two sample hold circuits are provided as in each of the above-described embodiments, the error of the sample hold circuit itself can be canceled, so that the accuracy of the signal processing circuit can be further improved, which is preferable.

Similarly, two sample and hold circuits 5c and 5d in the second embodiment are provided.
As for the above, one sample and hold circuit can be used for both of them, but for the same reason as described above, 2
It is preferable to provide two sample and hold circuits.

[0024]

As described above, according to the signal processing circuit of the present invention, first, the amplification degree of the amplifier is adjusted so that the maximum amplitude of the amplifier matches the input voltage range of the AD converter. After determining the amplification degree, under that amplification degree,
Since the offset of the amplifier is adjusted so that the minimum input voltage matches the minimum allowable input voltage of the AD converter or the maximum input voltage matches the maximum allowable input voltage of the AD converter, the maximum amplitude of the amplifier is adjusted. And the input voltage range of the AD converter match, and high-precision signal processing can be performed by maximizing the resolution of the AD converter.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a signal processing circuit of the present invention.

FIG. 2 is a circuit diagram of an amplifier used in the present embodiment, which is capable of freely adjusting an amplification degree and an offset.

FIG. 3 is a circuit diagram showing a second embodiment of the signal processing circuit of the present invention.

FIG. 4 is a block diagram showing an example of a conventional signal processing circuit.

FIG. 5 is a block diagram showing another example of a conventional signal processing circuit.

[Explanation of symbols]

 1 photoelectric conversion sensor 2 amplifier 3 AD converter 4 amplification degree adjustment circuit 5a, 5b, 5c, 5d sample hold circuit 6a, 6b analog subtractor 7a, 7b comparator 8 offset adjustment circuit 9 multiplexer 10 output terminal 11 operational amplifier 12 fixed resistance Device 13 Variable resistor 14 Input terminal 15 Control signal input terminal 16 Output terminal

Claims (2)

[Claims] 1. A signal processing circuit comprising an amplifier that amplifies and outputs an analog signal and that can be adjusted in amplification degree and offset, and an AD converter that inputs an output signal of the amplifier and converts it into a digital signal. In, the first output signal from the amplifier when the minimum level signal of the analog input signal is input to the amplifier and the maximum level signal of the analog input signal are input to the amplifier. A maximum amplitude measuring circuit for determining a first level difference between the second output signal from the amplifier and the second output signal from the amplifier; and a maximum allowable input voltage of the AD converter and a minimum allowable input voltage of the AD converter. An input voltage range measuring circuit for obtaining a second level difference between the two, an amplification degree adjusting circuit for adjusting the amplification degree of the amplifier so that the first level difference becomes equal to the second level difference, and One of the output signals of the first output signal and the second output signal, and one of the minimum allowable input voltage and the maximum allowable input voltage, which is one of the allowable inputs corresponding to the one output signal. A signal processing comprising: a comparator for comparing a voltage; and an offset adjusting circuit for adjusting an offset of the amplifier so that the level of the one output signal and the one allowable input voltage become equal to each other. circuit. 2. A sample and hold circuit for holding at least one of a minimum level signal and a maximum level signal of an analog input signal, and an output signal of the sample and hold circuit, in the preceding stage of the amplifier. 2. The signal processing circuit according to claim 1, further comprising: a multiplexer for selecting one of the analog input signals bypassing the sample hold circuit.