JPH09307010A - Method of fabricating semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of fabricating a semiconductor storage in which a source line is formed in a self aligned manner. SOLUTION: In this fabricating method, a floating gate 204, a control gate 202, and a selection gate 216 are sequentially formed on a channel via a tunnel oxide film 205 and a part of the selection gate 216 is formed on the channel via a gate insulating film 217. The method includes a step in which a first side wall film 250 is formed on a side wall of the layered product of the floating gate 204 and the control gate 202, and a source line 213 is formed by implanting impurities into a region which will become the source line 213 in a self aligned manner by using the first side wall film 250 as a mask. After that, a second side wall film 251 having the film width narrower than that of the first side wall film 250 is formed and the gate insulating film 217 is further formed, thereby forming the selection gate 216.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device having a floating gate and capable of electrically writing and erasing data.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor device capable of electrically writing and erasing, "0" and "1" are recorded depending on whether or not electrons are injected into a floating gate. There has been proposed an EEPROM and a flash EEPROM (collective erasing type non-volatile semiconductor device) which can occupy less memory cell area per bit than the EEPROM. Flash EEPROM above
Various types are known, and one of them is a BMI type flash EEPROM (U.
S. P5,280,446)).

In a BMI type flash EEPROM, a source region 12 and a drain region 13 are formed in a semiconductor substrate 11, as shown in the vertical sectional view of FIG.
A channel region 14 is formed between 2 and 13, and a floating gate 16 and a control gate 17 having a length less than the channel length in the cross section of FIG. 4 are formed on the channel region 14 via a gate insulating film 15. Further, a selection gate 18 is formed from the control gate 17 to the regions 12, 13 and 14 via an insulating film.

Flash EEPROM having such a structure
With the selection gate 18, there is no problem even if the memory cell is in the over-erased state, and by applying an appropriate voltage to the floating gate 16, the control gate 17, and the selection gate 18, the channel hot Since hot carriers can be generated on the source side more efficiently than electron injection, it is advantageous for a single power supply and a low voltage. Further, as shown in the plan view of FIG. 5, since the memory cells can be selected in a matrix by the control gate 17 and the selection gate 18, they are arranged in a NOR contactless system, and the source lines of the adjacent memory cells are arranged. Further, the drain lines can be shared, and the memory array area can be reduced. Thus, B
The MI type flash memory EEPROM is considered to be promising for lower voltage and higher integration.

FIG. 6 is a sectional view showing each step of manufacturing the BMI type flash memory (in FIG. 5, taken along the line AA).
FIG. FIG. 3A shows a tunnel oxide film 105 and a floating gate 10 on a p-type semiconductor substrate 106 after forming a well and a field oxide film for element isolation.
4 and a part of the inter-poly insulating film (ONO laminated film) 103, and further, etching for processing the floating gate 104 into a stack gate shape in the bit line direction (BB direction in the plan view of FIG. 5). The remaining interpoly insulating film 103 is formed, and then the control gate 10 is formed.
2. A silicon oxide film 101 is formed by the CVD method, and a resist film 100 for etching each film in the word line direction (CC direction in the plan view of FIG. 5).
The patterning is performed.

Next, as shown in FIG. 1B, the silicon oxide film 10 is formed using the resist film 100 as a mask.
1, the control gate 102, the interpoly insulating film 103, and the floating gate 104 are etched into a stack gate shape.

Then, as shown in FIG. 1C, the resist film 10 is formed by the photolithography technique so that the portion which becomes the common source line of the adjacent memory cells is opened.
8 is patterned. After that, N-type impurities (for example, As) 107 are implanted. At this time, the common drain line 109 is implanted by self-alignment, and the common source line 110 is implanted with its position regulated by the resist film 108.

After that, as shown in FIG.
A silicon oxide film 113, a silicon nitride film 112, and a silicon oxide film 111 are deposited by the D method.

Next, as shown in FIG. 1E, the select gate 1 is etched back by dry etching.
15 (see FIG. 9G) is etched back to the silicon nitride film 112 so that the silicon oxide film 113 in the region where the gate insulating film 114 is formed remains, and the silicon oxide film 113, the silicon nitride film 112 and the silicon Nitride film 11
A laminated side wall film 116 composed of 1 and 1 is formed.

Next, as shown in FIG. 3F, one of the silicon oxide film 113 and the tunnel oxide film 105 for forming the gate oxide film 114 and one of the common source line 110 and the common drain line 109. The partial region is removed by wet etching.

Next, as shown in FIG. 1G, after forming a gate oxide film 114 by a thermal oxidation method, a select gate 115 is formed.
To form After that, a peripheral gate transistor and a wiring are formed by using a known technique.

[0012]

However, in the above-described conventional manufacturing method, as shown in FIG. 6C, the common source line 110 (source region 12 in FIG. 4) is formed by the resist by photolithography technique. Since the film 108 is patterned, the uniformity of the channel length of the selection gate 115 (selection gate 18 in FIG. 4) in the BMI type flash EEPROM depends on the alignment accuracy in the photolithography technique.

The variation in the channel length may cause an increase in the leak current of the entire memory array or may cause the deterioration of the memory characteristic due to the variation in the threshold value of the select transistor. For this reason, it is necessary to provide some alignment margin in the photolithography process, and the BMI type flash EEPR is provided.
It has a drawback that the OM cannot be miniaturized.

In view of the above circumstances, it is an object of the present invention to provide a method of manufacturing a semiconductor memory device in which source lines are formed in a self-aligned manner.

[0015]

In a semiconductor memory device of the present invention, a floating gate, a control gate, and a select gate are sequentially stacked on a channel via an insulating film, and a part of the select gate is In a method of manufacturing a semiconductor memory device formed so as to face a channel, a first sidewall film is formed on a sidewall portion of a stack of a floating gate and a control gate, and the first sidewall film is used as a mask to perform self-deposition. A step of forming impurities by injecting impurities into a region to be a source line to form a source line, and then forming a second sidewall film having a film width narrower than that of the first sidewall film to form the select gate. It is characterized by including.

According to the above structure, the formation position of the source line is determined by the film width of the first side wall film formed on the side wall portion of the stacked body of the floating gate and the control gate. That is, the formation position of the source line is not determined by the accuracy of mask alignment by the photolithography technique, but is determined in conformity with the formation position of the stacked body of the floating gate and the control gate. The channel length of the transistor formed by the select gate is a value obtained by subtracting the film width of the second sidewall film from the film width of the first sidewall film. Since the film width of the first side wall film is formed to be substantially uniform in the side wall portion of the stacked body in each memory cell, the channel length of the select gate transistor in each memory cell can be made uniform. .

The steps of the method for manufacturing the semiconductor memory device will be described below in detail.

That is, according to the method of manufacturing a semiconductor memory device of the present invention, a floating gate, a control gate, and a select gate are sequentially stacked on the channel with an insulating film interposed therebetween, and a part of the select gate is formed in the channel. In a method of manufacturing a semiconductor memory device formed to face above, a first silicon oxide film or a single-layer or laminated insulating film is formed after forming a material for the floating gate, an interpoly insulating film, and a material for a control gate. A first step of forming a conductive thin film, and forming the above-mentioned materials, the interpoly insulating film, and the first silicon oxide film or a single-layer or laminated insulating thin film in parallel with the bit line and forming the memory cell portion into a stack gate shape. Second step of etching so that a mask is formed in a region including a region to be a source line, and then impurities are added to a region to be a drain line. In the third step of implanting, and after removing the mask, a second silicon oxide film and a first silicon nitride film are formed, and the first silicon nitride film is etched back. A fourth step of leaving the second silicon oxide film in a region to be a line and forming a first laminated sidewall film composed of the second silicon oxide film and the first silicon nitride film; A fifth step of implanting impurities in a region which should be a source line in a self-aligned manner by using the laminated sidewall film as a mask;
A sixth step of removing the first silicon nitride film, a second silicon nitride film and a third silicon oxide film are formed on the second silicon oxide film, and both films are etched back. A second silicon oxide film, a second silicon nitride film, and a third silicon oxide film are formed by leaving at least the second silicon oxide film in the region where the select gate insulating film is to be formed during the etch back. A seventh step of forming a stacked sidewall film, an eighth step of removing at least the second silicon oxide film located in a region where a select gate insulating film is to be formed, and a select gate insulating film forming. And a ninth step of forming a select gate.

The thickness of the second silicon oxide film formed in the fourth step is preferably 5 nm to 40 nm, and the thickness of the first silicon nitride film is preferably 400 nm to 600 nm.

Alternatively, a semiconductor memory device in which a floating gate, a control gate, and a select gate are sequentially stacked on the channel with an insulating film interposed therebetween, and a part of the select gate is formed so as to face the channel. A first step of forming a material for the floating gate, an interpoly insulating film, and a material for the control gate, and then forming a first silicon oxide film or a single-layer or laminated insulating thin film. A second step of etching each material, the interpoly insulating film, and the first silicon oxide film or a single-layer or laminated insulating thin film in parallel with the bit line so that the memory cell portion has a stack gate shape; After forming a mask in a region including a region to be a source line, a third step of implanting impurities in a region to be a drain line and removing the mask. After that, a second silicon oxide film, a first silicon nitride film, and a third silicon oxide film are formed, the third silicon oxide film is etched back, and at least a source line should be formed during this etching back. A first laminated sidewall film composed of the second silicon oxide film, the first silicon nitride film, and the third silicon oxide film is formed, leaving the second silicon oxide film and the first silicon nitride film in the region. A fourth step of forming, a fifth step of implanting impurities in a region to be a source line in a self-aligned manner by using the first laminated sidewall film as a mask, and a third step of removing the third silicon oxide film. 6), a fourth silicon oxide film is formed on the first silicon nitride film, both films are etched back, and at the time of this etching back, at least a region where a select gate insulating film is to be formed is formed. A second step of forming a second stacked sidewall film composed of the second silicon oxide film, the first silicon nitride film and the fourth silicon oxide film while leaving the second silicon oxide film, and at least the selective gate insulation. The method comprises an eighth step of removing the second silicon oxide film located in a region where a film is to be formed, and a ninth step of forming a select gate insulating film and forming a select gate. And

The thickness of the second silicon oxide film formed in the fourth step is 5 nm to 20 nm, the thickness of the first silicon nitride film is 5 nm to 20 nm, and the third silicon oxide film is formed. Film thickness is 400nm to 600nm
It is desirable that

Alternatively, a semiconductor memory in which a floating gate, a control gate, and a selection gate are laminated in this order on a channel with an insulating film interposed therebetween, and a part of the selection gate is formed so as to face the channel. A method of manufacturing a device, comprising forming a material for the floating gate, an interpoly insulating film, and a material for the control gate, and then forming a first silicon oxide film or a single-layer or laminated insulating thin film.
And the step of etching each material, the interpoly insulating film, and the first silicon oxide film or the single-layer or laminated insulating thin film in parallel with the bit line so that the memory cell portion has a stack gate shape. And a third step of forming a mask in a region including a region to be a source line and implanting an impurity into a region to be a drain line, and a second silicon oxide film after removing the mask. And a first silicon nitride film is formed, the first silicon nitride film is etched back, and at the time of this etching back, at least a second region of the region where the select gate insulating film is formed is formed.
The second silicon oxide film and the first silicon oxide film
A fourth step of forming a first laminated sidewall film made of a silicon nitride film of the above, a second silicon nitride film and a third silicon oxide film are formed on the first silicon nitride film, and a third step of The silicon oxide film is etched back, and at the time of this etching back, at least the region of the second silicon oxide film and the second silicon nitride film to be the source line is left, and the second silicon oxide film and the first silicon film are left. A fifth step of forming a second laminated sidewall film composed of a nitride film, a second silicon nitride film, and a third silicon oxide film, and a source line in a self-aligned manner using the second laminated sidewall film as a mask. A sixth step of implanting an impurity into a region to be formed, a seventh step of removing portions of the second silicon nitride film and the third silicon oxide film, and a region where at least a select gate insulating film is to be formed The second An eighth step of removing the con oxide film, to form a selection gate insulating film, and wherein the ninth step of forming a select gate, in that it consists of.

The thickness of the second silicon oxide film formed in the fourth step is 5 nm to 20 nm, and the thickness of the first silicon nitride film is 30 nm to 100 nm. The thickness of the third silicon oxide film formed is preferably 400 nm to 600 nm.

Alternatively, a semiconductor memory device in which a floating gate, a control gate, and a selection gate are sequentially stacked on the channel via an insulating film, and a part of the selection gate is formed to face the channel. A first step of forming a material for the floating gate, an interpoly insulating film, and a material for the control gate, and then forming a first silicon oxide film or a single-layer or laminated insulating thin film. A second step of etching each material, the interpoly insulating film, and the first silicon oxide film or a single-layer or laminated insulating thin film in parallel with the bit line so that the memory cell portion has a stack gate shape; After forming a mask in a region including a region to be a source line, a third step of implanting impurities in a region to be a drain line and removing the mask. After that, a second silicon oxide film and a polysilicon film or an amorphous silicon film are formed, the polysilicon film or the amorphous silicon film is etched back, and at the time of this etching back, at least the region to be the source line is covered with the second silicon oxide film. The fourth step of forming a first laminated sidewall film composed of a second silicon oxide film and a polysilicon film or an amorphous silicon film while leaving the silicon oxide film of FIG. A fifth step of implanting impurities into a region which should be a source line in a consistent manner, and a sixth step of removing the polysilicon film or the amorphous silicon film,
A silicon nitride film and a third silicon oxide film are formed on the second silicon oxide film, and both of these films are etched back. At the time of this etching back, at least a second region of the region where the select gate insulating film is to be formed is formed. A seventh step of forming a second stacked sidewall film composed of the second silicon oxide film, the silicon nitride film and the third silicon oxide film while leaving the silicon oxide film, and at least the select gate insulating film is formed. It is characterized by comprising an eighth step of removing the second silicon oxide film located in the power region and a ninth step of forming a select gate insulating film and forming a select gate.

The thickness of the second silicon oxide film formed in the fourth step is 5 nm to 40 nm, and the thickness of the polysilicon film or the amorphous silicon film is 5 nm.
To 20 nm is desirable.

Further, by controlling the thickness of the first silicon oxide film or the single-layer or laminated insulating thin film formed in the first step, the side wall width of the first laminated side wall film is optimized. May be.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing each step of the method of manufacturing a semiconductor memory device of this embodiment (in FIG. 5, A in FIG.
-Corresponding to a sectional view taken along the arrow A).

First, as shown in FIG. 3A, a field oxide film for separating wells and elements is formed on a p-type semiconductor substrate 206, and a tunnel oxide film 205 is formed with a thickness of 7 nm to 1 nm.
The thickness of the polysilicon film to be the floating gate 204 is 100 nm to 150 nm, and the bottom oxide film 21 of the inter-poly insulating film (ONO laminated film) 203 is 0 nm thick.
8 is formed to a thickness of 5 nm to 15 nm, and a silicon nitride film 219 is formed to a thickness of 5 nm to 15 nm by the CVD method. Then, etching for processing the silicon nitride film 219, the bottom oxide film 218, and the floating gate 204 into a stack gate shape is performed in the word line direction (BB direction in the plan view of FIG. 5), and the remaining interpoly insulating film 203 is formed. The top oxide film 220 is 5 nm to 15 n
Then, a polysilicon film to be the control gate 202 is formed to a thickness of 100 nm to 150 nm.
The first silicon oxide film 201 is formed to 200 n by the CVD method.
Each is formed to a thickness of m to 350 nm. Next, the resist film 200 for patterning each film in the bit line direction (CC direction in the plan view of FIG. 5) is patterned.

Next, as shown in FIG. 3B, the silicon oxide film 20 is formed by using the resist film 200 as a mask.
1, the control gate 202, the interpoly insulating film 203, and the floating gate 204 are etched into a stack gate shape.

Next, as shown in FIG. 3C, only the region where the common drain line 209 of the adjacent memory cells is to be formed is opened, and the common source line 213 (FIG. 1) is formed.
The resist 208 is patterned by the photolithography technique so that the region where the (see (e)) is to be formed is masked. Then, As (arsenic) 207 is implanted as an n-type impurity into the region where the common drain 209 is to be formed under the conditions of 50 kev and 5e15 cm ⁻² , and the common drain line 209 is formed.

Next, as shown in FIG. 3D, the second silicon oxide film 211 is formed to a thickness of 5 nm to 10 n by the CVD method.
Similarly, the first silicon nitride film 210 is deposited to a thickness of 600 nm (W2) by the CVD method at a thickness (W1) of m.

Next, as shown in FIG. 3E, the silicon nitride film 210 is etched back by dry etching under the condition that the silicon oxide film 211 in the region where the common source line 213 should be formed remains. Oxide film 211
And a silicon nitride film 210 are formed to form a first laminated sidewall film (sidewall) 250. Next, As (arsenic) is used as the n-type impurity 212 for 100 kev and 5e.
Under the condition of 15 cm ⁻² , a common source line 213 is formed by self-aligning implantation into the region opened by the etching back of the silicon nitride film 210 in the previous step.

Next, as shown in FIG. 6F, the silicon nitride film 210 is wet-etched by hot phosphoric acid.
Is removed so that the entire film is covered only by the silicon oxide film 211.

Next, as shown in FIG. 3G, a second silicon nitride film 214 is formed to a thickness of 20 nm to 40 nm.
A third silicon oxide film 215 is deposited to a thickness of 20 nm to 40 nm, and the gate insulating film 217 of the selection gate 216 (see FIG. 1H) is dry-etched.
Etching back to the silicon nitride film 214 is performed under the condition that the silicon oxide film 211 in the region (see FIG. 1H) is left, and the silicon oxide film 211, the silicon nitride film 214, and the silicon oxide film 215 are removed. A second laminated sidewall film (sidewall) 251 made of is formed.

Next, as shown in FIG. 3H, the silicon oxide film 21 on the region where the gate oxide film 217 under the select gate 216 and the common source line 213 are to be formed.
1 and the tunnel oxide film 205 and a part of the silicon oxide film 211 on the common drain 209 are removed by wet etching with an aqueous solution containing hydrofluoric acid. Then, after forming the gate oxide film 217 to a thickness of 10 nm to 20 nm, the select gate 216 is formed. Thereafter, peripheral gate transistors and wirings are formed by a known technique.

As described above, according to this method of manufacturing a semiconductor memory device, the formation position of the source line 213 is the first stack formed on the side wall of the stack of the floating gate 204 and the control gate 202. Film width of the sidewall film 250 (W
sw1). That is, the source line 213
The formation position of is not determined by the accuracy of mask alignment by the photolithography technique, but is determined in conformity with the formation position of the stacked body of the floating gate 204 and the control gate 202. The channel length (Lsg) of the transistor formed by the select gate 216 is equal to the first stacked sidewall film (Wsw).
From the film width of 1) to the film width (Wsw) of the second stacked sidewall film 251.
2) is subtracted. The film width (Wsw1) of the first side wall film 250 and the film width (Ws) of the second laminated side wall film 251.
Since w2) is formed with a substantially uniform width on the side wall of the stacked body in each memory cell, the channel length (L) of the select gate transistor in each memory cell is
This makes it possible to make sg) uniform.

Here, assuming a sub-half generation memory cell, the channel length (L
sg) is 350 nm, and the film width (Wsw2) of the second stacked sidewall film 251 is expected to be 30 nm to 100 nm.
In addition, in FIG. 1E, the implantation range of the n-type impurity implanted into the position to be the common source line 213 is 50 nm
In the following case, the sub-half generation tunnel oxide film 205
Is about 7 nm to 10 nm, the film thickness (W1) of the silicon oxide film 211 is about 40 nm at most. On the other hand, the silicon oxide film 211 when the silicon nitride film 210 is etched back in FIGS.
It is considered that the silicon oxide film 211 needs to have a film thickness of 5 nm or more in consideration of the amount of film reduction of the film thickness, and the film width (Wsw1) of the first stacked sidewall film 250 including the silicon oxide film 211 and the silicon nitride film 210 is The film width occupied by the silicon nitride film 210 is about 350 nm to 400 nm. Therefore,
Silicon nitride film 2 considering the amount of film loss during etch back
It can be said that the film thickness (W2) of 10 is preferably 400 nm to 600 nm.

A polysilicon film or an amorphous silicon film may be used instead of the above silicon nitride film 210. Further, instead of the first silicon oxide film 201 formed in the first step, a single-layer or laminated insulating thin film may be formed. Further, by controlling the thickness of the first silicon oxide film 201 formed in the first step, or the single-layer or laminated insulating thin film, the sidewall width of the first laminated sidewall film 250 is optimized. May be.

(Embodiment 2) Next, another embodiment will be described with reference to FIG.

FIG. 2 is a sectional view showing each step of the method for manufacturing the semiconductor memory device of this embodiment (in FIG. 5, A in FIG.
-Corresponding to a sectional view taken along the arrow A).

The steps performed before FIG. 2A are the same steps as those in FIGS. 1A to 1C in the first embodiment. That is, FIG. 2A is the same as FIG.
Although it is a diagram corresponding to the stage of (d), the difference from this FIG. 1D is that there are three of the second silicon oxide film 301, the first silicon nitride film 302, and the third silicon oxide film 303. This is the point where the film is deposited. Here, the film thickness (W3) of the second silicon oxide film 301 is 10 nm to 30 nm.
The thickness (W4) of the first silicon nitride film 302 is set to 10 nm to 30 nm, and the third silicon oxide film 3 is formed.
The film thickness (W5) of No. 03 is 600 nm.

Next, as shown in FIG. 2B, silicon is formed under the condition that the silicon nitride film 302 and the silicon oxide film 301 in the region where the common source line 305 (see FIG. 2C) is formed remain. The oxide film 303 is etched back by dry etching to form a first laminated sidewall film 350 including three layers of the silicon oxide film 301, the silicon nitride film 302, and the silicon oxide film 303.

Next, as shown in FIG. 6C, As (arsenic) is used as the n-type impurity 304 at 100 kev and 5e.
Silicon oxide film 3 in the previous process under the condition of 15 cm ^-2
A common source line 305 is formed by self-aligning implantation into the region opened by etch back of 03.

Next, as shown in FIG. 3D, the silicon oxide film 303 is removed by wet etching with an aqueous solution containing hydrofluoric acid. Then, the fourth silicon oxide film 30
6 is deposited to a thickness of 20 nm to 40 nm. Then, the silicon oxide film 306 and the silicon nitride film 302 are etched back by dry etching so that the silicon oxide film 301 in the region where the select gate insulating film should be formed remains, and the silicon oxide film 301 and the silicon nitride film 302 are removed. A second laminated sidewall film 351 including the silicon oxide film 306 is formed.

Next, as shown in FIG. 7E, the region where the gate oxide film 308 is formed under the select gate 307, the common source line 306, a part of the common drain line, the silicon oxide film 301, and the tunnel oxide film. 300 is removed by wet etching with an aqueous solution containing hydrofluoric acid, and the film thickness is 1
A gate oxide film 308 having a thickness of 0 nm to 20 nm is formed.
After forming the selection gate 307, peripheral gate transistors and wirings are formed by a known technique.

According to the method of manufacturing the semiconductor memory device, the channel length (Lsg) of the select gate transistor in each memory cell can be made uniform as in the first embodiment.

Here, assuming a sub-half generation memory cell, the channel length (L
sg) is expected to be 350 nm, and the film width (Wsw2) of the second laminated sidewall film 351 is expected to be 30 nm to 100 nm.
The film thickness of the silicon nitride film 302 needs to be 5 nm or more in consideration of the amount of reduction of the silicon nitride film 302 when the silicon oxide film 303 is etched back in FIG. 2B. It is considered that the film thickness of the silicon oxide film 301 needs to be 5 nm or more in consideration of the amount of decrease in the silicon oxide film 301 when the silicon nitride film 302 is etched back. Therefore, when the implantation range of the n-type impurity implanted into the position to be the source line 306 in FIG. 2C is 50 nm or less, the sub-half generation tunnel oxide film 205 has a thickness of about 7 nm to 10 nm. The film thickness (W3) of the film 301 is 5 nm to 20 nm
The film thickness (W4) of the silicon nitride film 302 is about 5 nm to 20 nm. The optimum value of each film thickness may be determined from the leak current between the control gate and the select gate. Therefore, as shown in FIG. 2B, the film width of the silicon oxide film 303 in the film forming the first stacked sidewall film 350 is about 350 nm to 450 nm. Therefore, the film thickness (W5) of the silicon oxide film 303 is 400 nm to 600 nm in consideration of the amount of film loss at the time of etch back.
It is desirable to set the degree.

(Third Embodiment) Next, another embodiment will be described with reference to FIG.

FIG. 3 is a sectional view showing each step of the method of manufacturing the semiconductor memory device of this embodiment (in FIG. 5, A in FIG.
-Corresponding to a sectional view taken along the arrow A).

The steps performed before FIG. 3A are the same steps as those in FIGS. 1A to 1C in the first embodiment. That is, FIG. 3A is the same as FIG.
Although it is a diagram corresponding to the stage of (d), the difference from this FIG. 1D is that the second silicon oxide film 401 to be the second laminated sidewall film 451 (see FIG. 3B) is The point is that the first silicon nitride film 402 is formed in advance. The thickness (W6) of the silicon oxide film 401 is 20 nm,
The film thickness (W7) of the silicon nitride film 402 is set to 80 nm.

Next, as shown in FIG. 6B, the silicon nitride film 402 is etched back by dry etching under the condition that the silicon oxide film 401 in the region where the source line is formed remains. A laminated sidewall film 451 is formed, and a second silicon nitride film 403 is formed to a film thickness of 10
nm, and the third silicon oxide film 404 is deposited thereon with a film thickness (W8) of 500 nm.

Next, as shown in FIG. 6C, the silicon oxide film 40 is formed under the condition that the silicon oxide film 401 and the silicon nitride film 403 in the region where the source line is formed remain.
4 is etched back by dry etching to form a first laminated sidewall film 450 composed of four films of a silicon oxide film 401, a silicon nitride film 402, a silicon nitride film 403 and a silicon oxide film 404. Then, As (arsenic) is used as the n-type impurity 405 at 100 kev, 5e15.
cm ⁻² , the silicon oxide film 404 in the previous process
By self-aligned injection into the area opened by the etch back of
A common source line 406 is formed.

Next, as shown in FIG. 3D, the silicon oxide film 404 is removed by wet etching with an aqueous solution containing hydrofluoric acid, and further, the silicon nitride film 403 is removed by dry etching. The second laminated sidewall film 451 is exposed.

Next, as shown in FIG. 7E, the silicon oxide film 401 and the tunnel oxide film 400 which are a part of the gate oxide film 408 under the select gate 407, the common source line and the common drain line are formed. Is removed by wet etching with an aqueous solution containing hydrofluoric acid to give a film thickness of 10
After forming the gate oxide film 408 of 20 nm to 20 nm,
The select gate 407 is formed. After that, the peripheral gate transistor and the wiring are formed by a known technique.

Here, the second laminated sidewall film 451 in this embodiment is the same as the second silicon oxide film 401 and the first silicon oxide film 401.
The silicon nitride film 402 is formed of two films.
Assuming a sub-half generation memory cell, the channel length (Lsg) of the select gate transistor is 350 nm,
The film width (Wsw2) of the second stacked sidewall film 451 is 30 nm.
Expected to be 100 nm. The film thickness (W6) of the silicon oxide film 401 is 5 nm to 20 nm in consideration of the film reduction amount when the silicon nitride film 402 is etched back, and the film thickness (W7) of the silicon nitride film 402 is the film when the same film is etched back. Considering the weight reduction, the thickness is about 30 nm to 100 nm. On the other hand, the film thickness of the silicon nitride film 403 may be set to 5 nm to 10 nm in consideration of the film reduction amount of the silicon oxide film 404 in FIG. Therefore, when the implantation range of the n-type impurities implanted into the source line in FIG. 3C is 50 nm or less, the tunnel oxide film 400 of the sub-half generation is about 7 nm to 10 nm, and therefore the film thickness of the silicon oxide film 401 Is 5 nm to 20n
m, the thickness of the silicon nitride film 402 is 5 nm to 10 nm.
If it is about nm, injection into the source line becomes possible. In addition, the silicon oxide film 401 and the silicon nitride film 4
02, the silicon nitride film 403, and the silicon oxide film 404, the film width of the first stacked sidewall film 450 (Wsw1) is about 350 nm to 500 nm. Therefore, the film thickness of the silicon oxide film 404 (W
8) is preferably about 400 nm to 600 nm in consideration of the amount of film loss when the film is etched back.

[0057]

As described above, according to the present invention,
The channel length of the select gate transistor in each memory cell can be made uniform.

[Brief description of drawings]

1A to 1H are cross-sectional views showing respective steps of a method for manufacturing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2A to FIG. 2E are cross-sectional views showing respective steps of a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention.

3A to 3E are cross-sectional views showing respective steps of a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view showing one memory cell portion in a BMI type flash EEPROM.

FIG. 5 is a plan view of a BMI type flash EEPROM.

6A to 6G are cross-sectional views showing each step of a method for manufacturing a conventional semiconductor memory device (BMI type flash EEPROM).

[Explanation of symbols]

 201 silicon oxide film 202 control gate 203 interpoly insulating film 204 floating gate 205 tunnel oxide film 206 p-type semiconductor substrate 210 silicon nitride film 211 silicon oxide film 216 select gate 217 gate insulating film 250 first stacked sidewall film 251 second Stacked sidewall film 350 First stacked sidewall film 351 Second stacked sidewall film 450 First stacked sidewall film 451 Second stacked sidewall film

Claims (10)

[Claims] 1. A semiconductor memory device in which a floating gate, a control gate, and a select gate are sequentially stacked on a channel with an insulating film interposed therebetween, and a part of the select gate is formed so as to face the channel. In the manufacturing method of the above method, a first side wall film is formed on a side wall portion of a stacked body of a floating gate and a control gate, and the first side wall film is used as a mask to add impurities to a region to be a source line in a self-aligned manner. After the implantation to form the source line, a step of forming a second side wall film having a film width narrower than that of the first side wall film to form the select gate is included. Manufacturing method. 2. A semiconductor memory device in which a floating gate, a control gate, and a select gate are sequentially stacked on a channel with an insulating film interposed therebetween, and a part of the select gate is formed so as to face the channel. A first step of forming a material for the floating gate, an interpoly insulating film, and a material for the control gate, and then forming a first silicon oxide film or a single-layer or laminated insulating thin film. A second step of etching each material, the interpoly insulating film, and the first silicon oxide film or a single-layer or laminated insulating thin film in parallel with the bit line so that the memory cell portion has a stack gate shape; A third step of implanting an impurity into a region to be a drain line after forming a mask in a region including a region to be a source line, and removing the mask After that, a second silicon oxide film and a first silicon nitride film are formed, the first silicon nitride film is etched back, and at the time of this etching back, at least the region of the second silicon oxide to be a source line is etched. A fourth step of forming a first laminated sidewall film composed of a second silicon oxide film and a first silicon nitride film while leaving the film, and the source in a self-aligned manner using the first laminated sidewall film as a mask. A fifth step of implanting impurities into a region to be a line, a sixth step of removing the first silicon nitride film, a second silicon nitride film and a third silicon film on the second silicon oxide film. An oxide film is formed, both films are etched back, and at the time of this etching back, at least the second silicon oxide film in the region where the select gate insulating film is to be formed is left, and the second silicon oxide film is formed. A seventh step of forming a second laminated sidewall film composed of the oxide film, the second silicon nitride film and the third silicon oxide film, and at least in the region where the select gate insulating film is to be formed. An eighth step of removing the second silicon oxide film, and a ninth step of forming a select gate insulating film and forming a select gate
A method of manufacturing a semiconductor memory device, comprising: 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein the thickness of the second silicon oxide film formed in the fourth step is 5 nm to 40 nm, and the thickness of the first silicon nitride film is Is 400 nm to 600 nm, a method of manufacturing a semiconductor memory device. 4. A semiconductor memory device in which a floating gate, a control gate, and a select gate are sequentially stacked on a channel with an insulating film interposed therebetween, and a part of the select gate is formed so as to face the channel. A first step of forming a material for the floating gate, an interpoly insulating film, and a material for the control gate, and then forming a first silicon oxide film or a single-layer or laminated insulating thin film. A second step of etching each material, the interpoly insulating film, and the first silicon oxide film or a single-layer or laminated insulating thin film in parallel with the bit line so that the memory cell portion has a stack gate shape; A third step of implanting an impurity into a region to be a drain line after forming a mask in a region including a region to be a source line, and removing the mask After a second silicon oxide film first
Forming a silicon nitride film and a third silicon oxide film,
The third silicon oxide film is etched back, and at the time of this etching back, at least the region of the second silicon oxide film and the first silicon nitride film to be the source line is left, and the second silicon oxide film and the second silicon oxide film are removed. A fourth step of forming a first laminated sidewall film composed of a first silicon nitride film and a third silicon oxide film, and a source line in a self-aligned manner using the first laminated sidewall film as a mask A fifth step of implanting impurities into the region, a sixth step of removing the third silicon oxide film, a fourth silicon oxide film formed on the first silicon nitride film, and etching of both films. Backing is performed, and at the time of this etch back, at least the second silicon oxide film in the region where the select gate insulating film is to be formed is left, and the second silicon oxide film, the first silicon nitride film, and the fourth silicon film are removed. A seventh step of forming a second laminated sidewall film made of an oxide film, and an eighth step of removing at least the second silicon oxide film located in a region where the select gate insulating film is to be formed. Forming a select gate insulating film and forming a select gate
A method of manufacturing a semiconductor memory device, comprising: 5. The method of manufacturing a semiconductor memory device according to claim 4, wherein the thickness of the second silicon oxide film formed in the fourth step is 5 nm to 20 nm, and the thickness of the first silicon nitride film is Is 5 nm to 20 nm, and the thickness of the third silicon oxide film is 400 nm to 600 nm. 6. A semiconductor memory in which a floating gate, a control gate, and a select gate are laminated in this order on a channel with an insulating film interposed therebetween, and a part of the select gate is formed so as to face the channel. A first step of forming a material for the floating gate, an interpoly insulating film, and a material for the control gate, and then forming a first silicon oxide film or a single-layer or laminated insulating thin film in the method for manufacturing the device; A second step of etching the materials, the interpoly insulating film, and the first silicon oxide film or the single-layer or laminated insulating thin film in parallel with the bit line so that the memory cell portion has a stack gate shape. Forming a mask in a region including a region to be a source line and then implanting an impurity into a region to be a drain line; After the removal, a second silicon oxide film and a first silicon nitride film are formed, the first silicon nitride film is etched back, and at the time of this etching back, at least a second region of the region where the select gate insulating film is formed is formed. Forming a first laminated sidewall film composed of the second silicon oxide film and the first silicon nitride film, leaving the silicon oxide film of
And the step of forming a second silicon nitride film and a third silicon nitride film on the first silicon nitride film.
A silicon oxide film is formed, the third silicon oxide film is etched back, and at the time of this etching back, at least the second silicon oxide film and the second silicon nitride film in a region to be a source line are left. A fifth step of forming a second laminated sidewall film composed of the second silicon oxide film, the first silicon nitride film, the second silicon nitride film and the third silicon oxide film; and the second laminated sidewall A sixth step of implanting impurities into a region to be a source line in a self-aligned manner using the film as a mask, and a seventh step of removing portions of the second silicon nitride film and the third silicon oxide film, An eighth step of removing at least the second silicon oxide film in the region where the select gate insulating film is to be formed, and a ninth step of forming a select gate insulating film and forming a select gate.
A method of manufacturing a semiconductor memory device, comprising: 7. The method of manufacturing a semiconductor memory device according to claim 6, wherein the thickness of the second silicon oxide film formed in the fourth step is 5 nm to 20 nm, and the thickness of the first silicon nitride film is Is 30 nm to 100 nm, and the thickness of the third silicon oxide film formed in the fifth step is 400 n
A method for manufacturing a semiconductor memory device, characterized in that the thickness is from m to 600 nm. 8. A semiconductor memory device in which a floating gate, a control gate, and a selection gate are sequentially stacked on a channel via an insulating film, and a part of the selection gate is formed so as to face the channel. A first step of forming a material for the floating gate, an interpoly insulating film, and a material for the control gate, and then forming a first silicon oxide film or a single-layer or laminated insulating thin film. A second step of etching each material, the interpoly insulating film, and the first silicon oxide film or a single-layer or laminated insulating thin film in parallel with the bit line so that the memory cell portion has a stack gate shape; A third step of implanting an impurity into a region to be a drain line after forming a mask in a region including a region to be a source line, and removing the mask After that, a second silicon oxide film and a polysilicon film or an amorphous silicon film are formed, the polysilicon film or the amorphous silicon film is etched back, and at the time of this etching back, at least the region to be the source line is covered with the second silicon oxide film. The fourth step of forming a first laminated sidewall film made of a second silicon oxide film and a polysilicon film or an amorphous silicon film while leaving the silicon oxide film of A fifth step of injecting impurities into a region which should be a source line in a consistent manner, a sixth step of removing the polysilicon film or the amorphous silicon film, a silicon nitride film and a third step on the second silicon oxide film. Silicon oxide film is formed, and both films are etched back. In addition, the second silicon oxide film in the region where the select gate insulating film is to be formed is left, and the second stacked sidewall film including the second silicon oxide film, the silicon nitride film, and the third silicon oxide film is formed. A seventh step, an eighth step of removing at least the second silicon oxide film located in a region where a select gate insulating film is to be formed, and a select gate insulating film is formed to form a select gate. 9th
A method of manufacturing a semiconductor memory device, comprising: 9. The method of manufacturing a semiconductor memory device according to claim 8, wherein the second silicon oxide film formed in the fourth step has a film thickness of 5 nm to 40 nm, and is a polysilicon film or an amorphous silicon film. Thickness is 5nm to 20n
m is a method for manufacturing a semiconductor memory device. 10. The sidewall width of the first laminated sidewall film is optimized by controlling the thickness of the first silicon oxide film or the single-layer or laminated insulating thin film formed in the first step. 11. The method for manufacturing a semiconductor memory device according to claim 1, wherein the method is applied.