JPH09305139A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve stepless gradation expression according to a video signal inputted in an active matrix method. SOLUTION: With respect to a FED(Field Emission Display) display device and an organic EL display device, a driving means is provided in each pixel P11..., and in this driving means, a video signal supplied to each frame is held by capacitors C11-Cjk. The drive duty factor of each pixel becomes 1 by DC- driving each FEC array with the held video signal. Further, in the driving means, each pixel block is provided with a FET element, and a drain current obtained according to the video signal voltage impressed on the gate of each FET element is supplied to each cathode electrode P of FEC array as a driving current. Thus, a stepless gradation expression is achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an image having active matrix type display pixels, and more particularly to an FED using a field emission type cathode.
It is suitable for application to a display device and an organic electroluminescence (hereinafter referred to as organic EL) display device.

[0002]

2. Description of the Related Art The applied electric field on the surface of a metal or semiconductor is reduced to 10
^At about ⁹ [V / m], electrons pass through the barrier and emit electrons in a vacuum even at room temperature due to the tunnel effect.
This is called field emission, and a cathode that emits electrons based on such a principle is called a field emission cathode (Fi
eld Emission Cathode). In recent years, it has become possible to create a surface emission type field emission cathode using an array of micron size field emission cathodes by making full use of semiconductor processing technology, and an image display apparatus using such a field emission cathode (FED display devices) are being researched and developed.

Further, as another display device, an organic EL display device using an organic compound in a light emitting layer is also studied based on a phenomenon called electroluminescence which emits light when an electric field is applied to a certain kind of phosphor. Development is underway.

[0004]

By the way, one of the development subjects of these display devices is to realize good gradation expression in order to improve the display quality. In order to control the light emission luminance according to the input video signal and realize good gradation expression, for example, there is a method in which a signal subjected to pulse width modulation (PWM) based on the value of the input video signal is used as a drive signal. . In this case, since the light emission time of each pixel is controlled according to the value of the input video signal, gradation expression is performed.

In this case, in general, pulse width modulation is performed by A / D converting the input video signal and detecting the coincidence between the digital data and the count value of the counter. Due to the limitation of the frequency of the clock for the counter and the A / D conversion, the limit of the A / D conversion is about 6 bits, that is, about 64 gradations. It was very difficult to achieve. That is, P
The WM method has a practical limit in gradation expression, and there is a problem in that dramatic improvement in display quality cannot be expected.

As another method, the drive voltage, that is, F
A pulse amplitude modulation (PAM) method has also been considered in which gradation is expressed by modulating a gate-cathode voltage in an ED display device or an electrode voltage in an organic EL display device. However, due to variations in the anode current rising point voltage on the anode current characteristics of the FED display device and the organic EL display device (variations between pixel pixels), temperature characteristics of the drive circuit, power loss, etc. There was a problem that good display quality could not be obtained because the control was not possible.

The present invention has been made to solve the above problems.
It is an object of the present invention to provide an active matrix display device which realizes stepless gradation expression according to an input video signal and dramatically improves the quality of a display image.

[0008]

In order to achieve the above object, the display device of the present invention is an FED display section in which display pixels are formed in a matrix, wherein the display pixels include an electron emission section and a display section. And the electron emission part is composed of at least one or more field emission cathodes,
The display unit includes an anode that collects electrons emitted from the electron emission unit and a phosphor that is deposited on the anode, and the electron emission unit of each display pixel is sequentially scanned at predetermined intervals. Holding means for holding the video signal applied to the electron emission portion of each display pixel until the next cycle,
The electron emitting section is provided with a driving unit including a FET element for supplying a constant DC current corresponding to the video signal held by the holding unit to the field emission cathode.

Further, in another display device of the present invention, in the organic electroluminescence display portion in which the display pixels are formed in a matrix, the display pixels are sequentially scanned at a predetermined cycle and video is displayed on each display pixel. A signal is given, and the driving means provided for each display pixel responds to the holding means for holding the video signal given to each display pixel until the next cycle, and the video signal held by the holding means. The FET element is configured to supply a constant DC current to the display pixel.

In the display means, the holding means may have a capacitor composed of a ground wiring layer and a ferroelectric film formed thereon, and a video signal applied to each FET element may be provided. In contrast, the F
A video signal correction circuit for providing an inverse characteristic of the gate-source voltage-drain current characteristic of the ET element is provided, or the video signal correction circuit is provided for the video signal applied to each FET element of the FED display unit. Characteristic correction for non-linear characteristics is also performed.

According to the present invention as described above, since each display pixel can be driven by a constant current corresponding to a video signal, stepless gradation expression according to the video signal can be realized and the display can be performed. The quality of the image can be dramatically improved. In addition, the driving means for driving each display pixel is provided in each display pixel, and the holding means for holding the video signal given in each cycle is provided in each driving means.
The number of output terminals of the display means can be reduced. Further, since each display pixel is driven by direct current with a duty of 1, the same luminance can be obtained by a driving voltage of a fraction of the dynamic method, and the duty is 1, so that the wiring of the display means floats. Power loss due to charge / discharge of the capacity can be almost eliminated.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An outline of a display device according to a first embodiment of the present invention will be described below with reference to FIG. In FIG. 1, the display units 10 are arranged in a matrix.
It is composed of xn pixels P11 to Pmn. An analog video signal Sv is amplified by the video amp 2 to these pixels P11 to Pmn, and further V
The characteristic of the video signal is corrected by the / I correction circuit 3 and is supplied. In this case, the pixels P11 to Pmn are sequentially time-divided by the scanning control circuit 4, and the video signal Sv is intermittently supplied to the individual pixels P11 to Pmn. The scanning control circuit 4 has a synchronization signal Syn.
c is supplied, and the scanning control circuit 4 outputs the synchronization signal Sync.
The scanning control is performed according to the timing.

A driving means is provided for each of the pixels P11 to Pmn, and the display section 10 is of a so-called active matrix type. Each pixel P11 to Pm
Although the driving means provided in n will be described later, holding means for holding the video signal intermittently supplied until the next video signal is supplied in the next frame cycle, and the video signal held by the holding means. F driven by constant current according to the level of
It is composed of ET elements. Then, the FET device supplies a constant current for driving each of the pixels P11 to Pmn. Each of the pixels P11 to Pmn emits light in response to the supplied constant current, which allows stepless gradation control according to the video signal. The power supply circuit 5 supplies an anode power supply for driving the display unit 10 and a drive power supply for the driving means.

The present invention enables a stepless gradation expression in the display device of the active matrix type as described above, and the FED display device as the first embodiment thereof is provided. This will be described with reference to FIGS. 2 to 6. First, as a field emission cathode (FEC) used in an FED display device, FIG. 5 shows a field emission cathode (FEC) called a Spindt type formed by a semiconductor processing technique.

As shown in FIG. 5, in the FEC, a cathode electrode C made of a metal such as aluminum is formed by vapor deposition on a substrate K such as glass, and the cathode electrode C is made of a metal such as molybdenum. A cone-shaped emitter E is formed. A silicon dioxide (SiO ₂ ) film is formed on a portion of the cathode electrode C where the emitter E is not formed, and a gate GT is further formed on the silicon dioxide (SiO ₂ ) film, which is a round shape provided on the gate GT and the silicon dioxide film. The cone-shaped emitter E is located in the opening. That is, the tip of the cone-shaped emitter E faces the opening provided in the gate GT.

The pitch between the cone-shaped emitters E can be made to be 10 microns or less, and tens of thousands to hundreds of thousands of emitters E can be provided on one substrate K. Further, since the distance between the gate GT and the tip of the cone of the emitter E can be made submicron, a gate-emitter voltage V _GE of only several tens of volts is applied between the gate GT and the emitter E (cathode electrode C). By applying the voltage, electrons can be emitted from the emitter E. The field-emitted electrons are collected by the anode A to which the positive voltage _VA applied to the gate GT is applied.

FIG. 6 shows the characteristics of the cathode current I _c and the gate-cathode voltage V _{GC of} such an FEC. This figure 6
As shown in, when the gate-cathode voltage V _GC gradually rises, the cathode current I _c starts to flow. The voltage V _{GC at} which this current I _c begins to flow is _defined as the threshold voltage V _TH
At this time, the electric field between the gate and the cathode is about 10 ⁹
Since it is about [V / m], electrons start to be emitted from the emitter E. As a result, the cathode current I _c begins to flow to the cathode electrode C. In general, a voltage of about V _OP shown in the figure, which is considerably higher than the threshold voltage V _TH , is applied between the gate and the cathode, and at this time, the cathode current I _op flows to the cathode electrode C.

In this case, since the emission current obtained from one of the cone-shaped emitters E is a small current of about 1 microamperes, a desired magnitude of emission current can be obtained by arraying a large number of emitters E. It is called FEC. In this case, the anode A collects the emitted electrons, and when the anode A is provided with a phosphor, the anode A from which the field emission from the emitter is collected is collected.
It is possible to emit light from the phosphor portion. By utilizing such a principle, an image display device using FEC, that is, an FED display device has been realized.

FIG. 2 shows an example of a partial detailed view of the display portion 10 of the FED display device using such a principle. This partially detailed view shows the display unit 1 surrounded by the one-dot chain line shown in FIG.
Only four pixels P11, P12, P21 and P22 of 0 are shown in an enlarged manner. Display unit 10
Is a portion where display is performed according to the principle described in FIG. 5, and an array of FECs including an emitter E and a gate GT is formed in each of pixels P11 to Pmn of one unit in a j × k block. In this case, the display area is formed by n × m pixels as shown in FIG. Pixel P1
1 to Pnm have the same configuration, and the pixel will be described with the pixel P11 as a representative.

Pixel 11 is a block FEC11, ...
FEC22 ... F of j × k block of FECjk
An EC array is provided, and drive means for independently driving each block is provided. The driving means is composed of two field effect transistors (FETs), a signal holding capacitor, and a resistance for compressing the FET characteristic variation. Specifically, the block FEC1
1, the FET TR-111 operates as an analog switch and opens when the video signal is applied to the pixel P11, and applies the input video signal to the capacitor C11 and the gate of the FET TR-11. The FET TR-111 is controlled to be turned on only during the period when the video signal is applied to the pixel P11, and the period of turning on is set to, for example, every frame.

The video signal thus captured in the pixel 11 is held by the capacitor C11 until the next video signal is applied in the next frame. Further, the holding voltage of the capacitor C11 is applied to the gate of the FET TR-11, so that a constant current according to this gate voltage flows in the drain of the FET TR-11. This drain current is supplied to the block FEC11 as a cathode current. In addition, FET
Since the drain current of TR-11 is determined by the gate voltage of the block FEC11, not by the rising characteristics of the block FEC11, even if the rising characteristics of the block FEC11 shown in FIG. You can run it. For this reason, it is possible to prevent variations in luminance due to variations in rising characteristics.

By the way, the video signal taken into the pixel P11 is supplied to the capacitor C1 provided in each block.
1 to Cjk are accumulated and held respectively. And
As described above, the gate voltage is supplied to the FETs TR-11 to TR-jk. As a result, each block FEC1
1 to FECjk are driven by a direct current constant current according to the level of the video signal, so the duty is 1
(100%). As a result, when the same luminance is obtained, the anode voltage and the gate voltage can be reduced to a fraction, and the breakdown voltage can be lowered, so that the display device can be easily designed. be able to.

Next, a drive control method for driving the pixels P11 to Pmn will be described. From the scanning control circuit 4 shown in FIG. 1, a video clock signal Vck, a video synchronization signal Vsy, a line synchronization signal Lsy, and a line clock signal Lck are given to the display unit 10. Further, the gate power supply Vg supplied from the power supply circuit 5 is constantly applied to the gates of all the pixels P11 to Pmn. In the horizontal direction of the display unit 10, shift registers SR-H1 to SR-Hn provided for each pixel are connected in series.
The video synchronization signal Vsy is input to the shift registers SR-H1 to SR-Hn, and the video synchronization signal Vsy is shifted by the video clock signal Vck. Further, in the vertical direction of the display unit 10, shift registers SR-V1 to SR-Vm provided for each pixel are connected in series, and the shift registers SR-V1 to S are provided.
The line synchronization signal Lsy is input to R-Vm, and the line synchronization signal Lsy is input by the line clock signal Lck.
sy has been shifted.

For example, when the output of the shift register SR-V1 supplies an active level signal to one of the switches S-1-1 to S-1-n of the pixels P11 to P1n on one horizontal line, SR-
When the output of H1 becomes the active level, two signals of the active level are supplied only to the switch S-1-1. Therefore, only the switch S-1-1 is turned on and the FETs TR-111 to FET11-111 in the pixel P11. TR-jk1 is turned on. This turned on the FET TR-111.
To the video signal V to the pixel 11 via TR-jk1.
s will be taken in. At the next timing, the video synchronization signal Vsy is shifted by the video clock Vck, the output of the shift register SR-H2 becomes active level, and only the switch S-1-2 is turned on.
FETs TR-111 to TR-jk in the pixel P12
1 turns on. Therefore, these turned on F
The pixel 12 receives the video signal Vs via the ET.

Similarly, as the video synchronizing signal Vsy is shifted by the shift registers SR-H1 to SR-Hn, the video signal Vs is sequentially taken into the pixels P13 to P1n in the horizontal direction. Next, when a video signal is taken into each pixel of one horizontal line, the line synchronizing signal Lsy is shifted by the line synchronizing signal, and the output of the shift register SR-V2 becomes active level.
This time, the pixels P21 to P2n in the second line sequentially take in the video signal Vs in the same manner as described above.
By continuously performing such an operation, the pixels Pm1 to Pmn in the final line are sequentially output to the video signal Vs.
Take in. As a result, one frame of the video signal is supplied to the display unit 10, and each of the pixels P11 to
In Pmn, a cathode current corresponding to the held video signal is supplied to each FEC block, and electrons are emitted according to the image signal of the input video signal Vs.

The source resistors R11 to Rjk inserted in the sources of the FETs TR-11 to TR-jk are F.
It acts to suppress variations in the characteristics of ET TR-11 to TR-jk. That is, when the drain current is smaller than a predetermined value, the voltage drop of the source resistance is small, and
The ET is operated in the direction of increasing the drain current, and when the drain current is larger than a predetermined value, the voltage drop of the source resistance becomes large, and the FET is operated in the direction of decreasing the drain current. In this way, the pixel P11
.About.Pmn performs a field emission operation according to the video signal Vs, which is collected on the side of the anode electrode A (not shown in FIG. 1) and collides with the phosphor, thereby performing a light emitting operation. That is, one frame of light constituting an image is emitted and one image is displayed.

In the video signal holding capacitors C11 to Cjk provided in each block of each pixel, the video signal needs to be updated every frame, and the video signal needs to be held during that period. In the case of shortage, a capacitor formed by forming a ferroelectric film on the ground wiring layer may be added to increase the capacitance. The held output voltage from the capacitors C11 to Cjk is FET TR-1 which is a field effect transistor.
1 to TRjk are applied to the FET TR-
Since 11 to TRjk are the MOS type which is the insulated gate type, the leakage current is small and the capacitors C11 to C11 having a small capacity.
Cjk makes it possible to hold the video signal level for one frame.

The characteristics of the drain-source voltage V _DS and the drain current I _D of the FET element are generally shown in FIG.
The constant current characteristic as shown in is known. In this example, the cathode current is steplessly modulated according to the video signal as described above by utilizing the constant current characteristic of the FET. For example, the cathode currents for the pixels P11 to Pmn are almost independent of the characteristics of each pixel.
A current determined by the gate voltage of the S-type FETs TR11 to TRjk flows. In this case, the characteristics of the gate-source voltage V _GS and the drain current I _D of the MOS type FET element are generally non-linear as shown in FIG. 4, but with the characteristics for the video signal Sv which is the gate voltage. Gives a reverse characteristic so that a cathode current linearly modulated steplessly according to the voltage value of the video signal Sv input to the input terminal 1 can be obtained. The characteristic processing of the video signal Sv for this purpose is performed by the V / I correction circuit 3.

Further, blocks FEC11 to FECjk
The characteristics of the gate-cathode voltage V _GC and the cathode current I _c of each pixel are as shown in FIG. 6 as described above, but the maximum brightness is set to V _OP and I _OP . As the gain of the video amplifier 2, a MOS type FET TR-
The drain-source voltage V _{DS of} 11 to TR-jk shown in FIG. 3 is adjusted to be before the bending point, that is, a voltage of 1 to 3V. That is, the constant current characteristic region of the FET element is used. The non-linear characteristic of the gate-cathode voltage V _GC and the cathode current I _c shown in FIG. 6 may be corrected by the V / I correction circuit 3.

In the V / I correction circuit 3, the video signal Sv is subjected to, for example, logarithmic compression processing, and F shown in FIG.
Gate-source voltage V _GS and drain current I of ET element
A characteristic reverse to the characteristic of _D is given, and the video signal Sv processed as described above is supplied to the MOS type FET TR-1.
1 to TR-jk are applied. Then, the current flowing through the cathode electrodes C1 to Cn of each pixel has a linear characteristic with respect to the voltage value of the video signal Sv input to the input terminal, that is, is linearly modulated in accordance with the video signal Sv. The cathode current can be obtained.

The brightness of the display section 10 is proportional to the anode power. Since the anode voltage is usually constant, the brightness is proportional to the anode current, and the anode current is almost the same as the cathode current. That is, if the cathode current changes, the brightness changes accordingly. Therefore, in the present invention, the stepless gradation expression according to the video signal Sv is generated by the cathode current steplessly modulated according to the video signal Sv. Will be realized. In this case, as a matter of course, there is no limitation to multi-step gradation as in the conventional PWM modulation, and there is no influence of variation in characteristics of FIG. 6, so that the quality of the display image can be dramatically improved. .

By the way, when the characteristic correction is insufficient only by the processing of the V / I correction circuit 3, the video signal Sv
Alternatively, a correction circuit system for performing A / D conversion, correction calculation, and D / A conversion may be provided to perform correction by digital calculation. In such a case, each FET TR-1
It is also possible to perform characteristic correction corresponding to each pixel 1 to TR-jk. In addition, each FET T is corrected by digital calculation correction.
When performing characteristic correction for each of R-11 to TR-jk,
The above-mentioned source resistances 11 to jk for correcting characteristic variations
Becomes unnecessary.

Further, in order to correct the characteristics of the video signal Sv, the characteristics of each of the pixels P11 to Pmn may be stored in the memory in advance as table data, and the correction may be executed based on the characteristics. When the display device is to be full-colored, R, G, and B phosphors are provided in one pixel, and the block made up of the FEC array is divided into three corresponding to R, G, and B, and each color is divided into three blocks. The video signal is captured and held in each divided block. In this case, if the gate electrode is also divided corresponding to the divided blocks, the color balance can be adjusted by adjusting the gate voltage of each gate electrode.

Next, an organic EL display device as a second embodiment of the display device of the present invention will be described with reference to FIGS. 7 to 9. The outline of the display device is the same as that of the display device shown in FIG. And the four pixels P11, P21, P22 of the display unit 10 shown in FIG. 1 in the case of an organic EL display device.
The detailed configuration of is shown in FIG. Also in the organic EL display device, as shown in FIG. 1, the display unit 10 is composed of m × n pixels P11 to Pmn arranged in a matrix. The operation of this display device is such that the display element is FE.
The description is omitted because it is as described above except that the organic EL display element is changed from C, but the display unit 10 is an active matrix type, and each pixel P11 to Pmn emits light according to a constant current supplied. By doing so, stepless gradation control according to the video signal can be performed. The power supply circuit 5 supplies the display unit 10 with a driving anode power supply and the like.

The present invention is an organic EL display device which is a second embodiment of the present invention, which is capable of stepless gradation expression in a display device of active matrix type as described above. Will be described with reference to FIGS. Organic E used in this organic EL display device
The structure of the L light emitting element is shown in FIG. The organic EL light emitting device is
Thin film transparent ITO formed on the glass substrate 101
The electrode 102, the hole transport layer 103 formed so as to cover the ITO electrode 102, and the hole transport layer 103.
A light emitting layer 104 formed in a thin film on the top, and a light emitting layer 104
It is composed of the upper electrode 105 formed above.

In the organic EL light emitting device having such a structure, the upper electrode 105 serves as a so-called cathode electrode and the ITO electrode 102 serves as an anode electrode. When a negative DC voltage is applied to the upper electrode 105 and a positive DC voltage is applied to the ITO electrode 102, the holes injected from the ITO electrode 102 are transported by the hole transport layer 103 and injected into the light emitting layer 104. On the other hand, electrons are injected from the upper electrode 105 into the light emitting layer 104, and the injected electrons and holes injected from the hole transport layer 103 are recombined in the light emitting layer 104. By this recombination,
The light emitting layer 104 emits light, and this light emission can be observed through the translucent hole transport layer 103, the ITO electrode 102, and the glass substrate 101.

In this case, the upper electrode 105 and the ITO electrode 1
If the voltage of the DC power supply applied to 02 is 10 V or less,
It is possible to obtain light emission of 00 [cd / cm ² ] or more.
The hole transport layer 103 is generally formed of triphenyldiamine (TPD) as a material, and the light emitting layer 10
4 is generally formed of an aluminum quinolinol complex (Alq ₃ ). Further, instead of the organic EL medium including the hole transport layer 103 and the light emitting layer 104, a light emitting layer having a single layer structure including a light emitting polymer can be used.

The characteristics of the anode current I _a of the organic EL display element and the anode-cathode voltage V _AC are shown in FIG. As shown in FIG. 6, when the anode-cathode voltage V _AC gradually rises, the anode current I _a starts to flow. The voltage V _{AC at} which this current I _a starts to flow is called the threshold voltage V _th . Generally, a voltage of about V _OP, which is much higher than the threshold voltage V _th , is applied between the anode and the cathode, and at this time, the anode current I _op flows through the ITO electrode 102 which is the anode.

An example of a partial detailed view of the display portion 10 of the organic EL display device using such a principle is shown in FIG.
This partial detailed view shows a pixel P of the display unit 10 shown in FIG.
Only four pixels of 11, P12, P21 and P22 are enlarged and shown. The display unit 10 is a portion where display is performed according to the principle described with reference to FIG.
5, light emitting layer 104, hole transport layer 103, and ITO
Pixels P11 to Pmn of one unit are formed by j organic EL elements including the electrodes 102. In this case, the display area is formed by n × m pixels as shown in FIG. Pixels P11 to Pnm are all configured the same,
The pixel will be described with the pixel P11 as a representative.

The pixel 11 is an organic EL element O-EL1.
It is provided with j organic EL elements of O-ELj, and a driving means for independently driving each organic EL element is provided. The driving means is composed of two field effect transistors (FETs), a signal holding capacitor, and a resistor for compressing the FET characteristic fluctuation compression. Specifically, in the organic EL element O-EL1, the FET TR-1
1 operates as an analog switch, and the pixel P
When the video signal is applied to 11, the input video signal is applied to the capacitor C1 and the gate of the FET TR-1. The FET TR-11 is controlled so as to turn on only during a period when a video signal is applied to the pixel P11, and the period of turning on is set to, for example, every frame.

The video signal thus captured in the pixel 11 is held by the capacitor C1 until the next video signal is applied in the next frame. Further, the holding voltage of the capacitor C1 is applied to the gate of the FET TR-1, so that a constant current according to the gate voltage flows in the drain of the FET TR-1. This drain current is supplied to the organic EL element O-EL1 as a cathode current. In addition, FET
Since the drain current of TR-1 is determined by the gate voltage of the organic EL element O-EL1 and not by the rising characteristic of the organic EL element O-EL1, even if the rising characteristic of the organic EL element O-EL1 shown in FIG. 9 varies. The cathode current that absorbs the variation can flow. For this reason, it is possible to prevent variations in luminance due to variations in rising characteristics.

By the way, the video signal taken into the pixel P11 is accumulated and held in the capacitors C1 to Cj provided for each organic EL element. Then, as described above, the gate voltage is supplied to the FETs TR-1 to TR-j. Thereby, each of the organic EL elements -EL1 to O-
ELj is driven by a constant DC current according to the level of the video signal, so its duty is 1 (100
%). As a result, when the same luminance is obtained as compared with the case of dynamic driving, the anode voltage can be reduced to a fraction, and the breakdown voltage can be lowered, which facilitates the design.

Next, a drive control method for driving the pixels P11 to Pmn will be described. Here, from the scanning control circuit 4 shown in FIG. 1, the video clock signal Vck, the video synchronization signal Vsy, the line synchronization signal Lsy, and the line clock signal Lck are given to the display unit 10. Also,
The anode power Va supplied from the power supply circuit 5 is constantly applied to the ITO electrodes (anode electrodes) of all the pixels P11 to Pmn. In the horizontal direction of the display unit 10, shift registers SR-H1 to
The SR-Hn are connected in cascade, the video synchronization signal Vsy is input to the shift registers SR-H1 to SR-Hn, and the video synchronization signal Vsy is shifted by the video clock signal Vck. The display unit 1
In the vertical direction of 0, shift registers SR-V1 to SR-Vm provided for each pixel are connected in series.
The line synchronization signal Lsy is input to the shift registers SR-V1 to SR-Vm, and the line synchronization signal Lsy is shifted by the line clock signal Lck.

For example, when the output of the shift register SR-V1 supplies an active level signal to one of the switches S-1-1 to S-1-n of the pixels P11 to P1n on one horizontal line, SR-
When the output of H1 becomes the active level, since two active level signals are supplied only to the switch S-1-1, only the switch S-1-1 is turned on and the FET11 to FETj1 in the pixel P11 are turned on. It turns on.
That is, at this time, FET11 to FETj turned on
The video signal Vs is captured by the pixel 11 via 1. Video clock Vc at the next timing
The video synchronization signal Vsy is shifted by k, and the output of the shift register SR-H2 becomes active level,
Only the switch S-1-2 is turned on, and the pixel P12
FET11 to FETj1 in the inside are turned on. That is,
At this time, the video signal Vs is taken into the pixel 12 through the FET11 to FETj1 which are turned on.

The synchronizing signals Vsy of the shift registers SR-H1 to SR-Hn are sequentially shifted, and accordingly, the video signals Vs are sequentially fetched to the pixels P13 to P1n in the horizontal direction. Next, when a video signal is taken into each pixel on one horizontal line, the line synchronizing signal Lsy is shifted by the line synchronizing signal, the output of the shift register SR-V2 becomes active level, and this time, the pixels P21 to P21 on the second line. P2n
However, the video signal Vs is sequentially fetched in the same manner as described above. By continuously performing such an operation, the pixels Pm1 to Pmn on the final line sequentially capture the video signal Vs. As a result, one frame of the video signal is supplied to the display unit 10, and the cathode current corresponding to the video signal held in each of the pixels P11 to Pmn is supplied to each organic EL display element to be input. Light is emitted according to the image signal of the video signal Vs.

The source resistors R1 to Rj inserted in the sources of the FETs TR-1 to TR-j are the FETs T1.
This serves to suppress the variation in the characteristics of R-1 to TR-j. That is, when the drain current is smaller than a predetermined value, the voltage drop of the source resistance is small, and the FET is operated in the direction of increasing the drain current. When the drain current is larger than the predetermined value, the voltage drop of the source resistance is large and the FET is drained. The current is decreasing. In this way, the pixels P11 to Pmn perform the light emitting operation according to the video signal Vs. That is, one frame of light constituting an image is emitted and one image is displayed.

In the video signal holding capacitors C1 to Cj provided in each block of each pixel, the video signal is updated every frame, and it is necessary to hold the video signal during this period. If there is a shortage, a capacitor formed by forming a ferroelectric film on the ground wiring layer may be added to increase the capacitance.
The holding output voltage from the capacitors C1 to Cj is applied to the gates of the FETs TR-1 to TRj which are field effect transistors, but since the FETs TR-1 to TRj are MOS type insulated gate type, The leakage current is small, and the small-capacity capacitors C1 to Cj can hold the video signal level for one frame.

The characteristics of the drain-source voltage V _DS and the drain current I _D of the FET element are generally shown in FIG.
The constant current characteristic as shown in (4) is known, and in this embodiment as well, the constant current characteristic of such an FET is used to continuously modulate the cathode current according to the video signal as described above. ing. For example, the pixels P11 to Pm
As the cathode current for n, a current determined by the gate voltage of the MOS FETs TR1 to TRj flows regardless of the characteristics of each pixel. In this case, M
The characteristics of the gate-source voltage V _GS and the drain current I _D of the OS-type FET element are generally non-linear as shown in FIG. 4, but are opposite to these characteristics with respect to the video signal Sv serving as the gate voltage. By providing such a characteristic, a cathode current that is linearly modulated steplessly according to the voltage value of the video signal Sv input to the input terminal can be obtained. The characteristic processing of the video signal Sv for this purpose is performed by the V / I correction circuit 3.

Furthermore, organic EL elements O-EL1 to OE
Anode-cathode voltage V of each pixel composed of Lj
The characteristics of _AC and the anode current I _a are as shown in FIG. 9 as described above, but the maximum brightness is set to V _OP and I _OP . That is, the gain of the video amplifier 2 is the MOS type FE.
The drain-source voltage V _{DS of} T TR-1 to TR-j shown in FIG. 3 is adjusted to be before the bending point, that is, a voltage of 1 to 3V. That is, the constant current characteristic region of the FET element is used. In addition, the nonlinear characteristic of the anode-cathode voltage V _AC and the anode current I _a shown in FIG.
The correction may be performed by the I correction circuit 3.

In the V / I correction circuit 3, the video signal Sv is subjected to, for example, logarithmic compression processing, and F shown in FIG.
Gate-source voltage V _GS and drain current I of ET element
A characteristic reverse to the characteristic of _D is given, and the video signal Sv processed as described above is supplied to the MOS type FET TR-1.
~ TR-j is applied to the gate. Then
The current flowing through the upper electrode 105 (cathode electrode) of each pixel has a linear characteristic with respect to the voltage value of the video signal Sv input to the input terminal, that is, is linearly modulated in accordance with the video signal Sv. The cathode current can be obtained.

The brightness of the display section 10 is proportional to the anode power. Since the anode voltage is usually constant, the brightness is proportional to the anode current, and the anode current is almost the same as the cathode current. That is, if the cathode current changes, the brightness changes accordingly. In other words, in this example, the cathode current that is steplessly modulated according to the video signal Sv causes stepless gradation expression according to the video signal Sv. Will be realized. In this case, as a matter of course, there is no limitation to multi-step gradation as in the conventional PWM modulation, and there is no influence of variation in characteristics of FIG. 6, so that the quality of the display image can be dramatically improved. .

By the way, when the characteristic correction is not sufficient only by the processing of the V / I correction circuit 3, the video signal Sv
Alternatively, a correction circuit system for performing A / D conversion, correction calculation, and D / A conversion may be provided to perform correction by digital calculation. In such a case, each FET TR-1
It is also possible to perform characteristic correction corresponding to each TR-j and each pixel. In addition, each FET TR-
When the characteristic correction is performed for each of 1 to TR-j, the above source resistors 1 to j for correcting the characteristic variation are unnecessary.

Further, in order to correct the characteristics of the video signal Sv, the characteristics of each of the pixels P11 to Pmn may be stored in the memory as table data in advance, and the correction may be executed based on the characteristics. When the display device is to be full-colored, R, G, and B filters are provided within one pixel, and the organic EL display element group is divided into three parts corresponding to R, G, and B, and video of each color is displayed. The signal is captured and held in each divided block. In this case, if the anode electrode is also divided corresponding to the divided blocks, the color balance can be adjusted by adjusting the anode voltage of each anode electrode.

[0054]

As described above, in the FED display device and the organic electroluminescence display device of the present invention, each display pixel can be driven by a constant current corresponding to the video signal, and therefore, the display pixel corresponding to the video signal is not displayed. It is possible to realize gradation expression in stages, and it is possible to dramatically improve the quality of a display image. Further, the driving means for driving each display pixel is provided for each display pixel, and the holding means for holding the video signal given in each cycle is provided in each driving means. The number of output terminals can be reduced.
Further, since each display pixel is driven by direct current with a duty of 1, the same luminance can be obtained by a driving voltage of a fraction of the dynamic method, and the duty is 1, so that the wiring of the display means floats. Power loss due to charge / discharge of the capacity can be almost eliminated.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a display device of the present invention.

FIG. 2 is a diagram showing in detail a part of a display unit of the FED display device according to the first embodiment of the present invention.

3 is an explanatory view of a V _DS -I _D characteristic of the FET.

4 is an explanatory view of the V _GS -I _D characteristic of the FET.

FIG. 5 is an explanatory diagram of a structure of FEC.

FIG. 6 is an explanatory diagram of V _GC -I _C characteristics of FEC.

FIG. 7 is a diagram showing details of a part of a display portion of an organic EL display device according to a second embodiment of the present invention.

FIG. 8 is an explanatory diagram of a structure of an organic EL display unit.

9 is an explanatory view of a V _AC -Ia characteristics of the organic EL display unit.

[Explanation of symbols]

2 Video Amplifier 3 V / I Correction Circuit 4 Scanning Control Circuit 5 Power Supply Circuit 10 Display P11 to Pmn Pixels FEC11 to FECjk Field Emission Cathodes TR-11 to TR-jk, TR-111 to TR-jk
1, TR-1 to TR-j, TR-11 to TR-j1 Field effect transistors O-EL1 to O-ELj Organic EL display element

Claims (8)

[Claims] 1. An FED display unit in which display pixels are formed in a matrix, each display pixel includes an electron emission unit and a display unit, and the electron emission unit is at least one field emission cathode. The display unit includes an anode that collects electrons emitted from the electron emission unit, and a phosphor that is deposited on the anode. A video signal is intermittently applied to the electron emitting portion, holding means for holding the video signal applied to the electron emitting portion of each display pixel until the next cycle, and a video signal held by the holding means. The display device is characterized in that the electron-emitting portion is provided with a driving means including an FET element for supplying a constant DC current corresponding to the above to the field emission cathode. 2. The display device according to claim 1, wherein the holding means has a capacitor composed of a ground wiring layer and a ferroelectric film formed thereon. 3. A video signal correction circuit for providing a video signal applied to each FET element with an inverse characteristic of a gate-source voltage-drain current characteristic of the FET element is provided. The display device according to claim 1. 4. The video signal correction circuit is provided for each of the FEs.
4. The display device according to claim 3, wherein the video signal applied to the T element is also subjected to characteristic correction for the non-linear characteristic of the field emission cathode. 5. In an organic electroluminescence display part in which display pixels are formed in a matrix, the display pixels are sequentially scanned at predetermined intervals and a video signal is given to each display pixel. The driving means provided for each pixel is a holding means for holding the video signal given to each display pixel until the next cycle, and a constant direct current corresponding to the video signal held by the holding means for the display pixel. A display device comprising an FET element for supplying to the. 6. The display device according to claim 5, wherein the holding means has a capacitor composed of a ground wiring layer and a ferroelectric film formed thereon. 7. A video signal correction circuit for providing a video signal applied to each FET element with an inverse characteristic of a gate-source voltage-drain current characteristic of the FET element is provided. The display device according to claim 5. 8. The video signal correction circuit is provided for each of the FEs.
8. The display device according to claim 7, wherein the video signal applied to the T element is also subjected to characteristic correction for the non-linear characteristic of each display pixel of the organic electroluminescence display section.