JPH09297707A - Driving method for storage device, and same device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the driving method which properly drives a storage device with different access specifications. SOLUTION: This storage device driving method properly drives the storage devices with different address input specifications and supplies addresses, based upon 1st address input specifications to the storage device to write 1st pattern data (S1, S2). Then an address based upon 2nd address input specifications is supplied to the storage device to write the 2nd pattern data (S3, S4). Then the address based upon the 1st address input specifications is supplied to the storage device to read in the corresponding data (S5, S6). When the read-in data are equal to the 1st pattern data, the storage device is set to the driving circuit constitution, which follows the 1st address input specifications (S7, S8, and S10).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a storage device and a device thereof, and more particularly to a method of driving a storage device driving an expansion memory and a device thereof.

[0002]

2. Description of the Related Art As a memory for expanding an apparatus such as a computer or a printer, an S. O. DIMM is widely used. This is an S.V. O. S.D. in the DIMM socket. O. This is because by setting the DIMM, general users can easily add memory.

S. O. Various types of DIMMs having different memory capacities, configurations, and access speeds are commercially available. O. The presence-side terminals (PD0 to PD6) provided in the DIMM are sensed by the device side, so that the device is recognized and used properly. In the presence detect terminal (hereinafter abbreviated as PD terminal), PD0 to 3 indicate the capacity and configuration, and PD4 to 6 indicate the access speed.

On the other hand, since the capacity configuration and the access speed are the same, even though the PD terminal specifications are the same,
S.I. O. There is a DIMM. For example, Toshiba's 4 MB S. O. With DIMM,
THL321050ATS-6 and THL321070
It is ATS-6, and its block diagram and pin arrangement are shown in FIG.
A, FIG. 1B, and FIGS. 2A and 2B. As is clear from these figures, the difference between the two is implemented.
The types of AM are different.

In FIG. 1A and FIG. 1B, the multiplexed address input is 10 (A0 to A9) for both row address input and column address input, whereas in FIG. 12 address inputs (A
0 to A7, A8R to A11R) and column address input 8
It is a book (A0-A7). In general, the former is called a 1K refresh type and the latter is called a 4K refresh type, which will be described below.

[0006]

As described above, S.S. O. Despite the presence of DIMMs, conventional devices have only one type of interface, and the S. O. Even if a DIMM is attached, since the presence detect terminal settings are the same, there is a drawback that the device cannot discriminate and correct access cannot be performed.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a method of driving a storage device and a device for appropriately driving storage devices having different access specifications.

[0008]

In order to achieve the above object, a method of driving a storage device of the present invention and the device thereof have the following configurations. That is, a method of driving a storage device that appropriately drives storage devices having different address input specifications,
A first write step of supplying an address according to a first address input specification to a storage device to write first pattern data, and an address according to a second address input specification to the storage device to provide a second pattern. A second writing step of writing data, a reading step of supplying an address complying with the first address input specification to a storage device to read corresponding data, and a data read in the reading step and the first pattern data If they are equal, a drive circuit configuration step of setting the drive circuit configuration according to the first address input specification is provided.

Another aspect of the present invention is a drive device for a storage device that appropriately drives a storage device having a different address input specification, wherein an address according to the first address input specification is supplied to the storage device, and a first device is provided. First writing means for writing the pattern data, and an address according to the second address input specification for supplying the memory device with the second writing means for writing the second pattern data and the address according to the first address input specification. If the reading means that supplies the data to the storage device and reads the corresponding data is equal to the data read by the reading means and the first pattern data,
Drive circuit configuration means for setting the drive circuit configuration according to the first address input specification.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION In the present embodiment, both 1K refresh type and 4K refresh type S.S.
O. Provide an accessible interface configuration for the DIMM. [First Embodiment] FIG. 3 shows an S.V. O. It is a block diagram explaining the structure of a DIMM interface circuit.

In FIG. 3, reference numeral 1 is an address input latch, 2 is a control logic circuit, and 4 to 6 are multiplexers. Signals 11 to 17 are output signals of the CPU and its peripheral circuits (not shown). Further, the signals 20 to 26 are S. O. This is a signal output to the DIMM. The configuration will be described in detail below. still,
The signal whose last character of the signal name in each circuit diagram is "*" is
Indicates negative logic.

Address signals A2 to A21 (11) output from the CPU are latched in the address latch (1) by the address strobe signal of the signal ADS * (12). LA2 which is the output signal of the address latch 1
~ LA21 becomes an input of the multiplexers 3, 4, 5, and 6. The signal CS * (13) is a signal obtained by decoding the upper bits of the address signal of the CPU. O. DIM
This indicates access to M and is input to the control logic circuit (2).

The signal W / R * (14) indicates write or read which is the type of access by the CPU. Further, the signals BE0 * to BE3 * (15) are S.S. O. It is a byte enable signal indicating which byte of the DIMM data bus 32 bits (4 bytes) is to be accessed.

The signal CLK (17) is a clock signal which gives the operation timing to the control logic circuit (2). The signal REFREQ (16) is the output of the refresh counter, and when this signal becomes true, the control logic circuit (2) outputs the S.S. O. A known refresh operation is performed on the DIMM.

The description of the refresh operation will be omitted. Control logic circuit (2) according to the input signal
Outputs the following signal. Signals RAS0 *, RAS2 *
(24) is a row address strobe signal, and signals CAS0 * to / CAS3 * (25) are column address strobe signals. In addition, the signal WE * (26) is
This is a write enable signal.

A row address strobe signal RA is issued in response to the byte enable signals BE0 * to BE3 * (15).
S0 *, RAS2 * (24) and column address strobe signals CAS0 * to CAS3 * are output. Signal 2
7 is a row address / column address switching signal R / C *
And becomes the select input of the multiplexers 3 and 4.

Signals 18 and 19 are control signals and serve as select inputs of the multiplexers 6 and 5, respectively. The multiplexers (3 to 6) output the A input when the select input is the logic “L”, and output the B input when the select input is the logic “H”. Each output of address latch 1 is connected to the input of a multiplexer (3-6). In addition, LA20 is the S. O. It is the address signal MA10 of the DIMM.

The output of the multiplexer (5) is connected to the B input of the multiplexer (3) and the output of the multiplexer (3) is the S.M. O. DIMM address signal M
It becomes A8, 9. The B input of the multiplexer (6) is V
It is pulled up to cc and is fixed to logic "H". The output becomes the address signal MA11.

Further, the output of the multiplexer (4) becomes the address signals MA0-7. FIG. 4 is a timing chart showing the operation of this embodiment. The operation will be described with reference to FIG. First, at timing T1, a CPU (not shown) outputs an address signal, an address strobe signal ADS *, a write / read signal W / R *, and byte enable signals BE0 * to BE3 *.

At the timing T2, the address strobe signal ADS * becomes false. As a result, the address signal is latched in the address latch (1) and MA0 to 1
The row address is output to 1. Next, timing T3
Then, the row address strobes RAS0 *, RAS2 *
Then, at timing T4, the row address / column address switching signal R / C * becomes logic "L", and the column address is output to the address signals MA0-9.

A write enable signal WE * is also output. Next, at timing T5, the column strobe signals CAS0 * to CAS3 * are output. At timing T6, the row address strobe signal RAS0
*, RAS2 *, column address strobe signal CAS
0 * to CAS3 *, the write enable signal WE * is set to false, and the row / column address switching signal R / C * is set.
Is a logic "H".

From the above, S. O. The access (write) to the DIMM ends. Also in the case of reading, access is performed in the same cycle as described above except that the write enable signal WE * is not true. FIG. 5 shows the address signals A2 to A21 and S.S. O. D
It is a figure showing correspondence of address signals MA0-MA11 outputted to IMM.

As can be seen from FIG. 5, the lower address signals MA0 to 7 are commonly output as row addresses A12 to 19 and column addresses A2 to 9. Also,
MA10 always outputs A20. On the other hand, MA8,
9 changes by changing the control signal A, and MA 11 changes by changing the control signal B. That is, when the control signal A is set to the logic "L", the MAs 8 and 9 output A20 and 21 as row addresses and the column addresses A10 and 11, respectively.

On the other hand, when the logic "H" is set, low,
A10 and 11 are output together with the column address. Also,
When the control signal B is logic "L", A21 is output to MA11, and when it is logic "H", logic "H" is always output. As described above, when the control signal A is set to the logic "L", the address suitable for the 1K refresh type is output, and when the control signal A is set to the logic "H", the address suitable for the 4K refresh type is output. In addition, the control signal B is set to logic "
By setting to H ", MA11 is fixed to logic" H ".

The 1K refresh type S.M. O. D
The input pins corresponding to MAs 10 and 11 of the IMM are N.M. Since it is C (no connection), it is clear that it is not affected even if the above signals are input. FIG. 6 shows the mounted S. O. 7 is a flowchart showing a procedure for determining the type of DIMM.

First, in step S1, the control signal A
And B to logic "L". Next, in step S2, data "55555555H" is stored in the address "0H".
To write. The address shown here is S. O. DIMM
Is the mapped relative address. "H" is 1
Means hexadecimal. FIG. 7 shows the S. O. DI
After executing the processing of step S2 according to the type of MM, the S.M. O. It is a figure which shows the data on DIMM. 7A shows the case where the 1K refresh type is mounted, and FIG. 7B shows the case where the 4K refresh type is mounted.

By executing step S2, both are set to "0H".
That is, "55H" is written to the address "~ 3H." Next, in step S3, the control signal A is set to logic "L" and the control signal B is set to logic "H".
Then, the data "AAAAAAAAH" different from that in step S2 is written in the address "0H".

If the S. O. If DIMM is 1K refresh type, valid MA0-9
Since both the row and column addresses are logical "L", "AAH" is written in the "0H-3H" numbers as shown in FIG. On the other hand, if it is a 4K refresh type, in MA0-11 which is effective as a row address,
MA11 is a logical "H", others are a logical "L", and MA0 to MA7 are all logical "L" as column addresses.
As shown in FIG. 8B, the address "200000H-2
The data "AAH" is written in the address "00003H".

As is clear from FIG. 8, the S. O. The data on the memory map varies depending on the type of DIMM. next,
In step S5, the control signals A and B are set to logic "L" as in step S1. In step S6, the address "0H" is read.

In step S7, it is determined whether the read data is the data "AAAAAAAAH" written in step S4. The read data is "AAAAAAAAA.
If it is H ", the process proceeds to step S9. In step S9, the mounted SO DIMM is determined to be the 1K refresh type, and the control signals A and B are held at" logic "L".

On the other hand, if it is determined NO in step S7, the process proceeds to step S8, and the data read in step S6 is the data "555" written in step S1.
55555H "is determined. If so, it is determined that the attached SO DIMM is the 4K refresh type, and the process proceeds to step S10. In step S10, the control signal A is set to logic" H ". The control signal B is set to "" to logic "L".

If it is determined NO in step S8, the S. O. Since it is determined that the access to the DIMM cannot be executed correctly, the process proceeds to the error processing routine. By the above processing, the output of the address suitable for each type is set.

The present invention may be applied to either a system composed of a plurality of devices or an apparatus composed of a single device. As described above, according to the present invention,
Although the settings of the presence detect terminals are the same, S.S. O. DIM
By determining the type of M as well, it is possible to output an address signal adapted to each type.

[0034]

As described above, according to the present invention, it is possible to properly drive storage devices having different access specifications.

[Brief description of drawings]

FIG. 1A is a 1K refresh type S.I. O. DIMM
FIG. 3 is a diagram illustrating the configuration of FIG.

FIG. 1B is a 1K refresh type S.I. O. DIMM
FIG. 6 is a diagram for explaining the terminal assignment of the signal of FIG.

2A is a 4K refresh type S.I. O. DIMM
FIG. 3 is a diagram illustrating the configuration of FIG.

FIG. 2B is a 4K refresh type S.I. O. DIMM
FIG. 6 is a diagram for explaining the terminal assignment of the signal of FIG.

FIG. 3 is a diagram illustrating an S.S. O. It is a block diagram explaining the structure of a DIMM interface circuit.

FIG. 4 is a diagram illustrating an S.S. O. 6 is a timing chart illustrating the operation of the DIMM interface circuit.

FIG. 5 is a diagram illustrating an S.S. O. It is a figure explaining the address output of a DIMM interface circuit.

FIG. 6 is a diagram illustrating an S.S. O. 7 is a flowchart illustrating an operation of the DIMM interface circuit.

FIG. 7 is a diagram illustrating an S.S. O. It is a memory map figure explaining operation | movement of a DIMM interface circuit.

FIG. 8 is a diagram illustrating an S.S. O. It is a memory map figure explaining operation | movement of a DIMM interface circuit.

[Explanation of symbols]

 1 Address Latch 2 Control Circuit 3-6 Multiplexer

Claims (10)

[Claims] 1. A method of driving a storage device, which appropriately drives storage devices having different address input specifications, wherein an address according to a first address input specification is supplied to the storage device to write first pattern data. A first writing step, an address complying with a second address input specification are supplied to the storage device, a second writing step for writing second pattern data, and an address complying with the first address input specification are supplied to the storage device. A read step of reading corresponding data, and a drive circuit configuration step of setting a drive circuit configuration according to the first address input specification if the data read in the read step and the first pattern data are equal to each other. A method for driving a storage device, comprising: 2. If the data read in the reading step and the second pattern data are equal, a driving circuit configuration step of setting a driving circuit configuration according to the second address input specification is further provided. The method of driving a storage device according to claim 1. 3. The first address has a row address and a column address, and the second address has a row address and a column address different from the first address specification. 2. A method for driving a storage device according to item 1. 4. The method of driving a storage device according to claim 1, wherein the storage device is a dynamic memory. 5. The method of driving a storage device according to claim 1, further comprising an access step of accessing the storage device by using the drive circuit configured in the drive circuit configuration step. 6. A drive device of a storage device for properly driving storage devices having different address input specifications, wherein an address according to a first address input specification is supplied to the storage device to write first pattern data. A first writing unit, an address according to a second address input specification are supplied to the storage device, a second writing unit for writing second pattern data, and an address according to the first address input specification are supplied to the storage device. Read means for reading the corresponding data, and drive circuit configuration means for setting the drive circuit configuration according to the first address input specification if the data read by the read means and the first pattern data are equal. A drive device for a storage device, comprising: 7. If the data read by the reading means is equal to the second pattern data, a drive circuit configuration means for setting a drive circuit configuration according to the second address input specification is further provided. The drive device for a storage device according to claim 6. 8. The first address has a row address and a column address, and the second address has a row address and a column address different from the first address specification. 6. The drive device for the storage device according to item 6. 9. The drive device for a storage device according to claim 6, wherein the storage device is a dynamic memory. 10. The drive device for a storage device according to claim 6, further comprising access means for accessing the storage device by using the drive circuit configured by the drive circuit configuration means.