JPH09293371A - Memory for ic card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a memory in which both a write operation and a read operation are executed in parallel so as to enhance an execution speed by a method wherein, when a read request comes during the write operation, an interrupt processing operation which reads out data which is written into a memory cell at an address whose read operation is requested is executed. SOLUTION: During the execution of a write operation, a read request is input to a control circuit 5 from the outside. Then, when a data bus 4 is performing operations other than a latch operation, the bus 4 becomes an empty state, and the output of an address latch circuit 9 is stopped. At the same time, address data which is contained in the read request is latched, and data which is written into addresses at a memory cell array 10 on the basis of the address data is read out. That is to say, the execution of the write operation is interrupted once during a read operation, and the execution of the write operation is resumed after the finish of the read operation. In this manner, when the read request comes during the execution of the write operation, the circuit 5 performs an interrupt processing operation which reads out the data written into the address during the read request of the array 10. As a result, both the write operation and the read operation can be executed in parallel, and the execution speed of a memory can be enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card memory used for ski lift tickets and the like.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a conventional IC card memory. In the figure, 1 is a shift register circuit for converting serial data input from the outside of the IC card memory into parallel data. Reference numeral 3 is a reception buffer and a transmission buffer for temporarily storing parallel data. Reference numeral 4 is a data bus, and 5 is a control circuit for managing memory address decoding, writing, and reading operations.

Reference numeral 6 is a data latch circuit for inputting write data of parallel data via the data bus 4.
Reference numeral 7 is a write buffer, and 8 is a column latch circuit.
Reference numeral 9 is an address latch circuit for inputting address data of parallel data via the data bus 4, 10 is a memory cell array for storing write data at an address based on the address data, 11 is a sense amplifier circuit, 1
2 is an output buffer.

Next, the operation will be described. In FIG. 7, serial data input from the outside of the IC card memory has address data input first, and then write data input. The serial data is converted into parallel data by the shift register circuit 1, temporarily stored in the reception buffer 2, and output to the data bus 4. The inside of the memory is managed by the control circuit 5, and first,
The address data of the parallel data is latched by the address latch circuit 9. Write data of the parallel data passes through the data latch circuit 6 and the write buffer 7 and is latched by the column latch circuit 8. This column latch circuit 8 has 1 page (16 bytes)
The write data is sequentially stored in the column latch circuit 8.

When the control circuit 5 detects a write request via the data bus 4, the data stored in the address of the memory cell array 10 corresponding to the address data latched by the address latch circuit 9 is erased. ,
The write data stored in the column latch circuit 8 is written in the memory cell array 10. FIG. 8 is an operation state diagram when a write request is made, and the operations are performed in the order shown. In addition,
The control circuit 5 measures the time from the latch of the write data to the latch of the next write data and the time from the latch of the write data to the input of the write request, and when the predetermined timeout time is exceeded, It is judged to be abnormal and the operation up to that point is invalidated and the processing ends. In addition, the sense amplifier circuit 11 and the output buffer 1
2 is for reading the data stored in the corresponding address of the memory cell array 10 when a read request is detected via the data bus 4 in a time zone in which no write request is detected, and for reading the data bus 4 and the transmission buffer. 3 to the shift register circuit 1.

[0006]

Since the conventional IC card memory is constructed as described above, when a write request is made, the write data is latched, erased and written in the order without interruption. Therefore, when the read operation cannot be executed during the write operation and both the write and read requests are made, the read operation is performed after the write operation is completed, so the data is immediately read. There was a problem that data could not be read even when it was necessary. Further, since the reception buffer 2 and the transmission buffer 3 are required, there is a problem that the configuration is complicated and causes a size increase. Further, there is a problem that it is not possible to confirm whether or not the write data is accurately written in the memory cell array 10.

The present invention has been made to solve the above problems, and when both writing and reading are requested, both are executed in parallel to increase the execution speed and reduce the size. It is an object of the present invention to provide a memory for an IC card that enables writing and confirm writing.

[0008]

According to a first aspect of the present invention, in a memory for an IC card, when a read request is issued during writing, writing is performed at an address of a memory cell array based on address data included in the read request. It is provided with a control circuit for performing an interrupt process for reading the stored data.

An IC card memory according to a second aspect of the present invention is inputted via a data input bus and a shift register circuit for converting into parallel data in a time zone between a stop bit and a start bit of serial data. And a control circuit for outputting the data written in the address of the memory cell array based on the address data included in the read request to the shift register circuit via the read data output bus in response to the read request.

According to a third aspect of the present invention, an IC card memory is written in an address of a memory cell array based on write data latched by a column latch circuit and address data latched by an address latch circuit in response to a write request. It is provided with a control circuit for comparing the data with the data and notifying when there is a mismatch.

According to a fourth aspect of the present invention, there is provided an IC card memory, wherein key data based on a key address input via a data input bus among key data written in advance in a memory cell array and the data input bus via the key data. The input key data is compared, and if they match, the write data is written in response to the write request, or the data written in the address included in the read request is read in response to the read request. It is equipped with a circuit.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1. 1 is a block diagram of a first embodiment of the present invention.
FIG. 1 is a block diagram showing a C card memory, in which 1 is a shift register circuit for converting serial data input from the outside of the IC card memory into parallel data, 21 is a data input bus, and 22 is a data output bus. Yes, it is divided into data input and output compared to the conventional.

Reference numeral 6 is a data latch circuit for inputting write data of parallel data via the data input bus 21, reference numeral 7 is a write buffer, and reference numeral 8 is a column latch circuit. Reference numeral 9 is an address latch circuit for inputting address data of parallel data via the data input bus 21, 10 is a memory cell array for storing write data at an address based on the address data, 11 is a sense amplifier circuit, and 12 is an output buffer. Is. Reference numeral 23 is a control circuit that manages the address decoding, writing, and reading operations of the memory.
The write data latched in the column latch circuit 8 is compared with the data written in the address of the memory cell array 10 based on the address data latched in the address latch circuit 9 in response to the write request, and if they do not match, the data output bus The error data is output to the shift register circuit 1 via 22.

Next, the operation will be described. In FIG. 1, serial data input from the outside of the IC card memory is first input with address data and then with write data. The serial data is converted into parallel data by the shift register circuit 1 and output to the data input bus 21. The inside of the memory is managed by the control circuit 23, and first, the address data of the parallel data is latched by the address latch circuit 9. Further, write data of the parallel data passes through the data latch circuit 6 and the write buffer 7,
It is latched by the column latch circuit 8. The column latch circuit 8 is a latch circuit having a capacity of 1 page (16 bytes), and write data is sequentially written in the column latch circuit 8
Is stored.

Here, the control circuit 23 controls the data input bus 2
When a write request is detected via 1, the data stored in the address of the memory cell array 10 corresponding to the address data latched in the address latch circuit 9 is erased, and the write data stored in the column latch circuit 8 is erased. Write to the memory cell array 10. The control circuit 23 measures the time from the latch of the write data to the latch of the next write data and the time from the latch of the write data to the input of the write request, and exceeds the predetermined timeout time. Then, the operation is judged to be abnormal, the operation up to that point is invalidated, and the processing ends.

The control circuit 23 also reads the write data latched in the column latch circuit 8 and, at the same time, writes in the memory cell array 10 at an address based on the address data latched in the address latch circuit 9 in response to the write request. The data inside is read out, both data are compared, and if they do not match, it is determined that the data has not been written correctly, and error data is output to the shift register circuit 1 via the data output bus 22.

Further, FIG. 2 is a timing chart when the serial data is input from the outside. As shown in FIG.
Stop bit (SP) and start bit (ST) of T
If data is written in or read out by the shift register circuit 1 between and, the receiving buffer 2 and the transmitting buffer 3 can be made unnecessary as shown in FIG. The latch circuit 6 or the column latch circuit 8 can be used. As a result, the reception buffer 2 and the transmission buffer 3 can be eliminated, and the chip size can be reduced.

As described above, according to the first embodiment, the write data latched by the column latch circuit 8 is compared with the data in the memory cell array 10 based on the address data latched by the address latch circuit 9. Since the error data is output in the case of a mismatch, it is possible to detect whether or not the data is accurately written in the memory cell array 10. Since the data bus 4 is divided into the data input bus 21 and the data output bus 22 and the shift register circuit 1 writes or reads data between the stop bit and the start bit of the UART, The reception buffer 2 and the transmission buffer 3 can be eliminated and the chip size can be reduced.

Embodiment 2. In the second embodiment, in the control circuit 5 shown in FIG. 7, when there is a read request during writing, the output of the address latch circuit 9 is stopped and the address data included in the read request is changed. It has a function of performing an interrupt process of latching and reading the data written in the address of the memory cell array 10 based on the address data.

Next, the operation will be described. In FIG. 7, it is assumed that a read request is externally input to the control circuit 5 during the writing operation. At this time, when the data bus 4 is not used (in the empty state), the output of the address latch circuit 9 is stopped, the address data included in the read request is latched, and the memory cell array based on the address data is latched. The data written at the address of 10 is read. FIG. 3 is an operation state diagram of a memory with and without a data read request during writing according to the second embodiment of the present invention.
When there is a read request, the data bus 4 is in an empty state when it is performing an operation other than latching, so that
Read as shown in FIG. 5D, and the write execution is suspended while the data is being read. Then, the write execution is restarted after the data reading is completed.

As described above, according to the second embodiment, when a read request is issued during writing, the control circuit 5 determines the address of the memory cell array 10 based on the address data included in the read request. Since the interrupt processing for reading the written data is performed, both the writing and the reading can be executed in parallel, and the execution speed can be increased even when both are requested.

Embodiment 3 FIG. In the third embodiment, in the control circuit 23 shown in FIG. 1, among the key data written in the memory cell array 10 in advance, the key data based on the key address input via the data input bus 21 and the data input bus thereof. The key data input via 21 is compared, and if they match, the write data is written in the memory cell array 10 in response to the write request, or the memory cell array 1 in response to the read request.
It has a function of reading the data written at the address of 0.

FIG. 4 is a memory map diagram of a memory cell array 10 according to the third embodiment of the present invention, where columns are page addresses and rows are column addresses, each page being 16 bytes. Page addresses 1 to 3 are areas for writing keys, and six 8-byte keys can be set. A page that can be accessed for each key is set, and this setting is determined by the access map for writing and reading. The key address is set as shown in the lower part of FIG. 4, and when a key is input from the outside of the memory, the key corresponding to the key address is read from the memory and the control circuit 23 determines the key corresponding to the key address. Compare. The access map is set before shipping by designation at the time of ordering, and the access map cannot be changed after shipping. Also, one or more keys can be set, and the remaining key area can be used as a normal data area in units of 16 bytes. Further, the IC of page address 0 has an initial value of FF16. At this time, all pages can be freely accessed regardless of whether the key collation matches or does not match.

Next, the operation will be described. In FIGS. 1 and 4, the contents of the IC are FF16 at the time of shipment, so that the contents of the memory cell array can be freely rewritten. In this state, C1, C2, Bl, B2, K
Write the key to l and K2. Next, data other than FF16 is written in the IC. After that, data cannot be written or read unless the key is verified. FIG. 5 is a data format diagram input to the IC card memory when writing and reading are requested, and FIG. 6 is a data format diagram output from the IC card memory.

The control circuit 23 first reads a command and a key address from the data shown in FIG. After this, read the key. For example, when the key address of the data shown in FIG. 5 is 0010, the key set in the area K1 corresponding to the key address and the key of the data shown in FIG. To be done. Next, the page address to be accessed in the memory cell array 10 is read and stored in the address latch circuit 9. Further, the latched page address is read by the control circuit 23, and it is determined whether or not the page address corresponds to the key. When the key and page address match, the memory cell array 10 can be accessed. If they do not match, the write request becomes invalid and the control circuit 23 outputs an error code to the outside. At this time, the data latched in the column latch circuit 8 becomes invalid. Although the case of the write request has been described in the third embodiment, the case of the read request is also performed by the same matching method.

As described above, according to the third embodiment, of the key data written in the memory cell array 10 in advance, the key data based on the key address input via the data input bus 21 and the data input bus thereof. The key data input via 21 is compared by the control circuit 23, and if they match, the write data is written in the memory cell array 10 according to the write request, or
Since the data written in the address of the memory cell array 10 is read in response to the read request,
Various data formats as shown in FIG. 5 are possible, and more precise confidentiality can be maintained. Further, when the key is collated, the data can be directly input to the control circuit 23 through the data input bus 21, so that there is no need to latch the key, and the collating operation can be speeded up.

[0027]

As described above, according to the first aspect of the present invention, when a read request is issued during writing,
The control circuit is configured to perform interrupt processing to read the data written in the memory cell array of the address included in the read request, so even if both write and read requests are made, both are executed in parallel. Therefore, there is an effect that the execution speed can be increased.

According to the second aspect of the invention, the shift register circuit converts the serial data into parallel data in the time zone between the stop bit and the start bit,
In response to a read request input via the data input bus by the control circuit, the data written in the memory cell array at the address included in the read request is output to the shift register circuit via the read data output bus. Therefore, the reception buffer and the transmission buffer can be eliminated, and the chip size can be reduced.

According to the third aspect of the invention, the write data latched by the column latch circuit by the control circuit is compared with the data written in the memory cell array at the address latched by the address latch circuit in response to the write request. However, since the notification is made when there is a mismatch, there is an effect that it can be detected whether or not the data is accurately written in the memory cell array.

According to the present invention, the key data based on the key address inputted through the data input bus among the key data previously written in the memory cell array and the data inputted through the data input bus. The control circuit compares the key data with each other, and if they match each other, the write data is written, or the data written at the address of the memory cell array is read, so that more precise security can be maintained. Also, when collating the key data, it is possible to input directly to the control circuit via the data input bus, so there is no need to latch the key data,
This has the effect of speeding up the matching operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an IC card memory according to a first embodiment of the present invention.

FIG. 2 is a timing chart when receiving data from the outside of the IC card memory according to the first embodiment of the present invention.

FIG. 3 is an operation state diagram at the time of a read request of the IC card memory according to the second embodiment of the present invention.

FIG. 4 is a memory map diagram of a memory cell array of an IC card memory according to a third embodiment of the present invention.

FIG. 5 is an IC for requesting writing and reading of the memory for an IC card according to the third embodiment of the present invention.
It is a data format figure input into the memory for cards.

FIG. 6 is an IC for requesting writing and reading of an IC card memory according to a third embodiment of the present invention.
It is a data format figure output from the memory for cards.

FIG. 7 is a block diagram showing a conventional IC card memory.

FIG. 8 is an operation state diagram when a write request is made in a conventional IC card memory.

[Explanation of symbols]

1 shift register circuit, 5, 23 control circuit, 8 column latch circuit, 9 address latch circuit, 10 memory cell array, 21 data input bus, 22 data output bus.

Claims (4)

[Claims] 1. A shift register circuit for converting serial data including a write request or a read request into parallel data, a column latch circuit for latching write data of the parallel data, and address data of the parallel data. The address latch circuit to be latched and the write data latched in the column latch circuit is written to an address of the memory cell array based on the address data latched in the address latch circuit in response to the write request, and the write data is written during execution of the write. A memory for an IC card, comprising a control circuit that performs an interrupt process for reading data written at an address of a memory cell array based on address data included in the read request when a read request is made. 2. A shift register circuit for inputting serial data including a write request or a read request and converting the serial data into parallel data in a time zone between a stop bit and a start bit of the serial data, and among the parallel data. A column latch circuit for inputting and latching write data via a data input bus, an address latch circuit for inputting and latching address data of its parallel data via a data input bus, and an input via the data input bus The write data latched by the column latch circuit is written to the address of the memory cell array based on the address data latched by the address latch circuit according to the write request, and the read request input through the data input bus is also performed. According to its read request And a control circuit for outputting the data written in the address of the memory cell array based on the address data contained in the above to the shift register circuit through the read data output bus. 3. A shift register circuit for converting serial data including a write request into parallel data, a column latch circuit for latching write data of the parallel data, and an address for latching address data of the parallel data. The latch circuit compares the write data latched by the column latch circuit with the data written at the address of the memory cell array based on the address data latched by the address latch circuit in response to the write request, and if they do not match. A memory for an IC card having a control circuit for informing the user. 4. A shift register circuit for converting serial data including a key address and key data in a write request or a read request into parallel data, and write data of the parallel data is input and latched via a data input bus. A column latch circuit, an address latch circuit for inputting and latching address data of its parallel data via a data input bus, and key data preliminarily written in the memory cell array input via the data input bus. The key data based on the key address is compared with the key data input via the data input bus, and if they match, the address latch circuit is supplied to the address latch circuit in response to a write request input via the data input bus. Memory cell array based on latched address data The write data latched in the column latch circuit is written to the address b or the address of the memory cell array based on the address data included in the read request is input in response to the read request input via the data input bus. A memory for an IC card, comprising: a control circuit that outputs written data to the shift register circuit via a read data output bus.