JPH09289302A - Amplifying solid-state imaging device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize the potential of a sensor, the depth of overflow barrier, substrate voltage required for reset or electronic shutter and so on, by independently forming an impurity region for the formation of the sensor in all the source, drain and gate regions in an amplifying solid-state imaging device containing pixel MOS transistors. SOLUTION: An amplifying solid-state imaging device is constituted as follows: An overflow barrier region 41 of second conductivity type and semiconductor regions 43, 44 of first conductivity type are formed on a semiconductor substrate 41 of the first conductivity type in this order. An amplifying pixel MOS transistor 26D comprising a source region 24, a drain region 25 and a gate region of the second conductivity type, is formed on the semiconductor regions 43, 44 of the first conductivity type. An impurity region 47 of the second conductivity type, the impurity concentration of which is lower than that of the drain region 25 of the semiconductor region 43 of the first conductivity type, is formed under the drain region 25. An overflow control region 46 of the first conductivity type is formed under the source region 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid state image pickup device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in response to a demand for higher resolution of a solid-state imaging device, an amplification type solid-state imaging device which has no smear and can realize fine pixels has been developed in place of a CCD solid-state imaging device. This amplification type solid-state imaging device includes a MOS type transistor for amplifying an optical signal for each pixel,
A signal is read out by using the electric charge accumulated in the pixel by photoelectric conversion as the current modulation of the transistor.

[0003]

17 to 20 show the previously proposed amplification type solid-state imaging device. This amplification type solid-state imaging device 1 has a second conductivity type, that is, an n type semiconductor region, that is, an overflow barrier region 3 and a p type semiconductor well region 4 on a silicon semiconductor substrate 2 of a first conductivity type, for example, p type.
Is formed on the p-type semiconductor well region 4 and SiO ₂ is formed.
Etc., a ring-shaped gate electrode 6 capable of transmitting light is formed through the gate insulating film 5, and the gate electrode 6 is formed in the p-type semiconductor well region 4 corresponding to the central hole and outer periphery of the ring-shaped gate electrode 6. The n-type source region 7 and the drain region 8 are formed by self-alignment as a mask,
Here, one pixel is a MOS transistor (hereinafter referred to as pixel M
An OS transistor) 9 is formed. The ring-shaped gate electrode 6 is made of a thin or transparent material so as to absorb light as little as possible. In this example, thin-film polycrystalline silicon is used. In FIG. 18, 10 is an interlayer insulating layer.

This pixel MOS transistor 9 is shown in FIG.
, The source regions 7 of the pixel MOS transistors 9 corresponding to each column are arranged in a matrix.
Are connected to a common signal line 11 made of, for example, a first layer Al formed along the vertical direction, and are formed at a position corresponding to each row of the pixel MOS transistors 9 so as to be orthogonal to the signal line 11, for example, a second layer Al. The vertical selection line 12 is formed along the horizontal direction.

[0005] Two horizontally adjacent pixels M
A wiring layer made of, for example, polycrystal silicon, that is, a U-shaped contact buffer layer 13 is formed so as to extend over the ring-shaped gate electrodes 6 of the OS transistors 9 and the corresponding vertical selection lines 12, respectively. Both ends of the buffer layer 13 are electrically connected to two pixel MOS transistors, that is, their gate electrodes 6 and 6, respectively, and an intermediate portion is electrically connected to the vertical selection line 12.

Reference numeral 15 is a contact portion between the contact buffer layer 13 and the vertical selection line 12, and 16 is a contact portion between the source region 7 and the signal line 11. Further, the drain power supply line 18 made of, for example, the first layer Al, which is connected to the drain region 8, is formed between the pixel MOS transistors 9 that do not straddle the contact buffer layer 13. 17 is the drain region 8
And a drain power supply line 18 are in contact with each other.

The pixel MOS transistor 9 shown in FIG.
As shown in FIG. 8, the light transmitted through the ring-shaped gate electrode 6 generates electrons and holes, of which the holes h serve as signal charges and are the p-type semiconductor well region 4 below the ring-shaped gate electrode 6.
Is accumulated in When a high voltage is applied to the ring-shaped gate electrode 6 through the vertical selection line 12 and the pixel MOS transistor 9 is turned on, a drain current (so-called channel current) flows in the surface channel, and the drain current Id changes due to the signal charge h. Therefore, the drain current Id is output through the signal line 11 and the amount of change is used as a signal output.

By the way, in the amplification type solid-state image pickup device 1 shown as the above-mentioned comparative example, as shown in FIGS. 19 and 20 showing the part of the pixel MOS transistor 9, the p-type semiconductor well region 4 is n-type. This is a structure in which only the source region 7 and the drain region 8 are formed. Therefore, as shown in the simulation of the potential in the charge accumulation state of the pixel MOS transistor of FIG. 21, the potential barrier of the drain portion as the channel stop, that is, the height of the potential barrier between adjacent pixels is other than the surface of the drain region. Then it was difficult to secure enough.
Further, the potential barrier of the overflow barrier region 3 in the substrate direction is about the diffusion potential of the p-type well region 4, which is insufficient as a potential barrier for the substrate. For this reason, blooming to adjacent pixels, overflow to the substrate, and charge injection from the substrate are likely to occur, and the amount of signal charge accumulated in the so-called sensor portion under the gate electrode tends to be small.

In this pixel MOS transistor,
As shown in the potential simulation in FIG. 22 (simulation of potential in the substrate depth direction passing through the sensor unit for accumulating charges (holes) h), the depth Y _OFB1 from the surface to the overflow barrier OFB when light enters. The electric charge h generated by the photoelectric conversion is accumulated in the portion of the valley of the potential serving as the sensor unit.

However, in the case of the pixel MOS transistor having the structure of FIG. 20, as shown in the potential diagram of FIG.
The potential of the n-type overflow barrier region 3 affects the potential gradient from the overflow barrier OFB toward the sensor unit side, and the depth Y _OBF1 from the surface to the overflow barrier OFB becomes substantially shallow.
This means that the charges due to the light (so-called light having a long wavelength) incident deeply from the overflow barrier OFB are not accumulated in the sensor unit. In addition, if the potential gradient is gentle, it is difficult for the electric charges generated in that portion to accumulate in the sensor portion. Therefore, the area that works effectively as the sensor portion is narrowed, which makes it difficult to obtain sensitivity to light having a long wavelength.

Light having a short wavelength is photoelectrically converted in a shallow region, but light having a long wavelength is photoelectrically converted after being incident deeper. Therefore, in order to obtain sensitivity to light having a long wavelength, it is preferable that Make a valley of the potential (sensor part) to a deep position, and overflow barrier O from the surface.
It is necessary to increase the depth to FB.

On the other hand, in the case of the pixel MOS transistor having the structure shown in FIG. 20, there is also a problem that the substrate voltage applied at the time of resetting the signal charges becomes too large.

In view of the above points, the present invention provides an amplification type solid-state image pickup device which can improve the overall sensitivity and obtain a spectral balance.

Further, according to the present invention, blooming to adjacent pixels can be suppressed, the amount of signal charges, output voltage, dynamic range, etc. can be increased, and the pixel potential in various operating states can be optimized. A solid-state imaging device and a method for manufacturing the same are provided.

[0015]

According to another aspect of the present invention, there is provided an amplification type solid-state image pickup device at a position deeper than a gate part in a first conductivity type semiconductor region where a source region, a drain region and a gate part of a pixel transistor are formed. Therefore, the overflow control region of the first conductivity type is formed over the entire area of the pixel.

In this amplification type solid-state image pickup device, in the first conductivity type semiconductor region in which the source region, the drain region and the gate part of the pixel transistor are formed, the overflow of the first conductivity type is spread over the entire pixel at a position deeper than the gate part. By having the control region, the depth from the surface to the overflow barrier is substantially increased, and the potential gradient from the overflow barrier to the sensor unit side becomes steep, so that the region effectively acting as the sensor unit is widened. Therefore, the sensitivity to light having a long wavelength is improved, and the overall sensitivity is improved and the spectral balance is obtained. Further, the substrate voltage can be reduced when the signal charges are reset.

The amplification type solid-state imaging device according to the present invention has the same conductivity type as the drain region below the drain region, that is, the first conductivity type semiconductor region in which the source region, the drain region and the gate portion of the pixel transistor are formed. A two-conductivity-type impurity region is formed, and a first region is formed at least under the gate portion.
A conductive overflow control region is formed.

In this amplification type solid-state imaging device, an impurity region of the same conductivity type as the drain region, that is, a second conductivity type is formed under the drain region of the amplification type pixel transistor, so that this impurity region serves as a so-called channel stop region. This prevents the signal charges accumulated under the gate portion from leaking to the adjacent pixel, and avoids blooming. The amount of signal charge, output voltage, and dynamic range also increase. Further, by forming the first conductivity type overflow control region in at least the signal under the gate portion, overall sensitivity improvement and spectral balance can be obtained, and the low range of the substrate voltage at the time of resetting the signal charge can be achieved.

The amplification type solid-state imaging device according to the present invention has the same conductivity type as the drain region below the drain region in the first conductivity type semiconductor region in which the source region, the drain region and the gate portion of the pixel transistor are formed. Is formed, and an overflow control region having a conductivity type opposite to that of the source region is formed below the source region.

In this amplification type solid-state imaging device, the source region is formed by forming an impurity region of the same conductivity type as the drain region below the drain region of the pixel transistor and forming an overflow control region below the source region. Impurity regions for forming a sensor can be independently formed in all regions of the drain, the gate, and the potential of the sensor, the depth of the overflow barrier, the substrate voltage required for resetting, and the like can be optimized.

According to the method of manufacturing an amplification type solid-state imaging device of the present invention, after the second conductivity type overflow barrier region, the first conductivity type semiconductor region and the gate insulating film are sequentially formed on the first conductivity type semiconductor substrate. By ion implantation, a first conductivity type overflow control region and a second conductivity type impurity region are selectively formed at a position corresponding to a source region and a drain region, respectively, in the first conductivity type semiconductor region. Then, a source region and a drain region are formed in the first conductivity type semiconductor region using the ring-shaped gate electrode formed on the gate insulating film as a mask to form an amplification type pixel transistor.

According to this manufacturing method, the impurity regions for forming the sensor can be independently formed in all regions of the source, the drain and the gate, and the potential of the sensor, the depth of the overflow barrier, and the substrate required for resetting. It is possible to manufacture an amplification type solid-state imaging device in which the voltage and the like are optimized.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION In an amplification type solid-state imaging device according to the present invention, a second conductivity type overflow barrier region and a first conductivity type semiconductor region are sequentially formed on a first conductivity type semiconductor substrate. An amplification-type pixel transistor including a second-conductivity-type source region, a second-conductivity-type drain region, and a gate is formed in the first-conductivity-type semiconductor region. The first conductivity type overflow control region is formed in the structure.

The amplification type solid-state image pickup device according to the present invention is the first
A second conductivity type overflow barrier region and a first conductivity type semiconductor region are sequentially formed on a conductivity type semiconductor substrate, and a second conductivity type source region, a second conductivity type drain region, and a second conductivity type drain region are formed in the first conductivity type semiconductor region. An amplification type pixel transistor including a gate portion is formed, a second conductivity type impurity region having an impurity concentration lower than that of the drain region is formed at a position below the drain region of the first conductivity type semiconductor region, and a second conductivity type impurity region is formed at least below the gate portion. The overflow control region of one conductivity type is formed.

The amplification type solid-state imaging device according to the present invention is the first
A second conductivity type overflow barrier region and a first conductivity type semiconductor region are sequentially formed on a conductivity type semiconductor substrate, and a second conductivity type source region, a second conductivity type drain region, and a second conductivity type drain region are formed in the first conductivity type semiconductor region. An amplification type pixel transistor including a gate portion is formed, a second conductivity type impurity region having an impurity concentration lower than that of the drain region is formed below the drain region of the first conductivity type semiconductor region, and a second conductivity type impurity region is formed below the source region. The overflow control region of one conductivity type is formed.

According to the present invention, in the amplification type solid-state imaging device, the second conductivity type impurity region is formed so as to correspond to a part or the whole of the drain region or to partially overlap the gate part, and the first conductivity type The overflow control region of the mold is formed so as to correspond to a part or the whole of the source region or to partially overlap the gate portion.

In the method for manufacturing an amplification type solid-state image pickup device according to the present invention, the second conductivity type overflow barrier region and the first conductivity type semiconductor region are sequentially formed on the first conductivity type semiconductor substrate, and the first conductivity type semiconductor substrate is formed. A step of forming a gate insulating film on the semiconductor region, and a step of forming a first conductivity type overflow control region at a position corresponding to a portion below the source region in the first conductivity type semiconductor region by ion implantation and a position corresponding to a portion below the drain region. A step of selectively forming impurity regions of the second conductivity type, a ring-shaped gate electrode is formed on the gate insulating film, and the second conductivity type is formed on the surface of the first conductivity type semiconductor region using the gate electrode as a mask. And forming a source region and a drain region to form an amplification type pixel transistor.

According to the present invention, in the method for manufacturing an amplification type solid-state image pickup device, the first conductivity type overflow control region is formed so as to correspond to a part or the whole of the source region or to partially overlap the gate part. The second conductivity type impurity region corresponds to part or all of the drain region,
Alternatively, it is formed so as to partially overlap with the gate portion.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic configuration example common to the embodiments of the amplification type solid-state image pickup device according to the present invention.

As shown in FIG. 1, the amplification type solid-state imaging device 21 according to the present example has a ring-shaped gate electrode 2 capable of transmitting light through the gate insulating film on the semiconductor region, as described above.
3 is formed, and the source region 24 and the drain region 25 are formed by self-alignment in the portion corresponding to the center hole and the outer periphery of the gate electrode 23, thereby forming a pixel MOS transistor 26 which becomes one pixel.

A plurality of pixel MOS transistors 26 are arranged in a matrix, and the pixel MO transistors corresponding to each column are formed.
The source region 24 of the S-transistor 26 is formed along the vertical direction, for example, a common signal line 27 made of the first layer Al.
Is connected to the pixel MO so that it is orthogonal to the signal line 27.
A vertical selection line 28 made of, for example, the second layer Al is formed along the horizontal direction at a position corresponding to each row of the S transistors 26.

Then, two pixels M adjacent in the horizontal direction
Each ring-shaped gate electrode 2 of the OS transistor 26
3 and the vertical selection line 28, a U-shaped wiring layer, that is, a contact buffer layer 29 is formed, and the contact buffer layer 29 is connected to the two pixel MOS transistors 26 and the vertical selection line 28, respectively. It

Further, between the pixel MOS transistors 26 that do not straddle the contact buffer layer 29, a drain power supply line 30 connected to the drain region 25, for example, of the first layer Al is formed. Reference numeral 31 is a drain contact portion between the drain power supply line 30 and the drain region 25, 32 is a source contact portion between the source region 24 and the signal line 27, and 34 is a contact portion between the contact buffer layer 29 and the vertical selection line 29.

The present invention is particularly characterized by the configuration of the pixel MOS transistor 26 in the amplification type solid-state image pickup device 21.

2 and 3 show a first embodiment of an amplification type solid-state image pickup device according to the present invention, particularly a pixel MOS transistor thereof. However, FIG. 2 is a pixel MO in which the signal line, vertical selection line, contact buffer layer, and drain power supply line of FIG. 1 are omitted.
FIG. 3 is a plan view showing only the S transistor, and FIG. 3 is a sectional view taken along line BB of FIG. 2, that is, a sectional view of the pixel MOS transistor.

As shown in FIGS. 2 and 3, in this embodiment, a second conductivity type or n type semiconductor layer, that is, the overflow barrier regions 42 and p are formed on the first conductivity type, for example, p type silicon semiconductor substrate 41. The type semiconductor well region 43 is formed. Further, a so-called sensor well region 44, which is a p-type charge storage well region forming a channel, is formed, and a ring capable of transmitting light on the p-type sensor well region 44 through a gate insulating film 45 made of SiO ₂ or the like. Shaped gate electrode 23 is formed. This ring-shaped gate electrode 2
3 on the semiconductor surface corresponding to the central hole and the outer periphery, in this example, the semiconductor surface reaching from the sensor well region 44 to the p-type semiconductor well region 43 by the ion implantation method by self-alignment so as to sandwich the gate electrode 23, respectively. A source region 24 and a drain region 25 are formed.

In this example, a p-type semiconductor region for adjusting the potential or the like, a so-called overflow control region 46, is further formed at a position deeper than the gate portion, that is, the sensor well region 44, over the entire region of the pixel to form one pixel. A pixel MOS transistor 26A is formed.

For the ring-shaped gate electrode 23, a thin or transparent material is selected so as not to absorb light as much as possible, and polycrystalline silicon, tungsten polycide, tungsten silicide or the like can be used. In this example, a thin film of polycrystalline silicon having a good light-transmitting property is used.

The mutual correlation of the impurity concentrations of the p-type silicon semiconductor substrate 41, the p-type semiconductor well region 43, the p-type sensor well region 44, and the p-type overflow control region 45 is highest in the sensor well region 44, and then p. The type silicon semiconductor substrate 41, the p type overflow control region 46, and the p type semiconductor well region 43 become lower in this order. That is, the p-type semiconductor well region 43 is the lowest.

In this pixel MOS transistor 26A,
Signal charges (holes) h are accumulated in the sensor well region 44, and the channel current is modulated accordingly. According to the amplification type solid-state imaging device 21 including the pixel MOS transistor 26A of this example, the p-type overflow control region 46 is formed at a position deeper than the sensor well region 44 over the entire pixel, and thus the p-type overflow control region 46 of FIG. As shown in the potential simulation (simulation of the potential in the substrate depth direction passing through the sensor unit that accumulates charges (holes) h), the depth Y _OFB2 from the surface to the overflow barrier OFB becomes substantially large (that is, Y
_OFB2 > Y _OFB1 ). Further, the potential gradient a on the sensor unit side from the overflow barrier OFB also becomes steep.

As a result, the area that works effectively as the sensor portion becomes wider than in the case of the comparative example shown in FIGS. 20 and 22. Therefore, the sensitivity to light having a long wavelength is improved, and the overall sensitivity and spectral balance can be improved.

FIG. 4 (corresponding to the BB cross section of FIG. 2) is
Amplification-type solid-state imaging device according to the present invention, particularly pixel MOS
A second embodiment of the transistor will be shown. In the present example, in addition to the configuration of FIG. 3 described above, a deeper position corresponding to the drain region 25, that is, to reach the p-type semiconductor well region 43 from the overflow control region 46,
Impurity region 47 of the same conductivity type as drain region 25, that is, n-type
Pixel MOS transistor 26B which forms one pixel by forming
Is configured. Impurity region 47 acts as a channel stop region for signal charge h (see FIG. 18) accumulated in sensor well region 44 below gate electrode 23.

The impurity region 47 may be formed so as to extend from the drain region 25 to the overflow barrier region 42, or may not extend to both regions 25 and 42, provided that the drain region 25 extends to the overflow barrier region. The impurity region 47 is further arranged so that the p-type semiconductor well region 43 exists between the drain region 25 and the overflow barrier region 42, that is, between the impurity region 47 and the overflow barrier region 42 while preventing a potential dip from being formed over 42. And drain region 2
It may be formed so that the p-type semiconductor well region 43 exists between the five. FIG. 4 shows an example in which an impurity region 47 is formed between the drain region 25 and the overflow barrier region 42.

In the signal charge accumulation state by controlling the impurity concentration of the n-type impurity region 47, the potential thereof is set to be shallower than the potential of the overflow barrier region 42 and deeper than the potential of the drain region 25.

The impurity concentration of the n-type impurity region 47 is set to such a concentration that a potential side dip is not formed when the signal charge h is discharged to the substrate 41 by the reset operation or the electronic shutter operation, for example. Therefore, the n-type impurity concentration is set lower than the impurity concentration of the drain region 25 and higher than the impurity concentration of the overflow barrier region 42. Since the other configurations in FIG. 4 are the same as those in FIG. 3, the corresponding portions will be denoted by the same reference symbols and redundant description will be omitted.

According to the amplification type solid-state image pickup device 21 having the pixel MOS transistor 26B of this example, the drain region 2 is provided while having the overflow control region 46.
5, the n-type impurity region 47 having the same conductivity type as the drain region is formed in the region between the drain region 25 and the overflow barrier region 42, and the n-type impurity region 47 is accumulated in the sensor well region 44. It acts as a channel stop region for the generated signal charge h. Therefore, the potential barrier formed by the n-type impurity region 47 prevents the signal charge h accumulated in the adjacent pixel MOS transistor from leaking out, and so-called blooming can be suppressed. Also,
The signal charge also increases, and the output voltage and the dynamic range can be increased.

At the same time, since the overflow control region 46 is provided in regions other than the n-type impurity region 47, the depth Y _OFB2 from the surface to the overflow barrier OFB is increased as compared with the comparative example, and the overall sensitivity is increased. Is improved and a spectral balance is obtained.

FIG. 5 (corresponding to the BB cross section of FIG. 2) is
Amplification-type solid-state imaging device according to the present invention, particularly pixel MOS
The 3rd Example of a transistor is shown. In this example,
In addition to the configuration of FIG.
Simultaneously with the formation of the impurity region 47 of the type, the same n-type impurity region 48 is formed immediately below the source region 24 to form a pixel MOS transistor 26C which becomes one pixel. Since other configurations are the same as those in FIG. 4, the corresponding portions are denoted by the same reference numerals and the duplicate description thereof will be omitted. The amplification type solid-state imaging device 21 including the pixel MOS transistor 26C of this example is suitable for a structure in which the width of the drain region 47 between pixels is narrow. According to the pixel MOS transistor 26C, the n-type impurity region 47 serving as a channel stop region is formed below the drain region 25, and the n-type impurity region 48 is simultaneously formed below the source region 48. Since such an overflow barrier is formed, it is possible to prevent so-called blooming, which is the leakage of signal charges to adjacent pixels. Further, in this structure, the shallow source region 24 and the drain region 25 and the deep n-type impurity regions 47 and 48 can be formed by using the same mask, so that the source region 24 and the drain region 25 are n. The alignment with the type impurity regions 47 and 48 can be performed accurately.
In addition, the same effects as those described with reference to FIG. 4 are obtained. FIG.
(Corresponding to the BB cross section of FIG. 2) shows a fourth embodiment of the amplification type solid-state image pickup device according to the present invention, in particular, its pixel MOS transistor. In this example, in the configuration of FIG. 5 described above, the n-type impurity region 48 immediately below the source region 24 is counteracted with a p-type impurity (for example, boron), and the counteracting region 50 is formed immediately below the source region 24 to form one pixel. Pixel MO
The S transistor 26D is configured. When the dose amount of the p-type impurity is smaller than the dose amount of the n-type impurity region, the strike-back region 50 becomes a low-concentration n-type impurity region by strike-back, and the dose amount of the p-type impurity is the same as the dose amount of the n-type impurity region. Alternatively, when the number is large, the return region 50 becomes a p-type impurity region. The p-type impurity implantation region 51 is
The range is wider than the n-type impurity 48. Since other configurations are the same as those in FIG. 5, corresponding parts are denoted by the same reference numerals and redundant description will be omitted.

In the amplification type solid-state image pickup device 21 having the pixel MOS transistor 26D of this example, the source region 2
By implanting the n-type impurity region 48 immediately below 4 with a p-type impurity to form a return region 50, the concentration and potential of the region immediately below the source region 24 can be set independently of the n-type impurity region 47 immediately below the drain region.

By the way, n is formed under the drain region 25 described above.
The second embodiment in which the type impurity region 47 is formed, the third embodiment in which the n-type impurity regions 47 and 48 are formed under the drain region 25 and the source region 24, respectively, and the lower part of the source region 24 is repelled by p-type impurities. In the fourth embodiment in which the region 50 is formed, the overflow control region 46 having the same polarity as that of the sensor well region 44 is present at a position deeper than the sensor well region 44 in all regions of the pixel by ion implantation. Source,
Since it is not possible to independently set all the impurity concentrations of the drain and gate regions, the pixel potential is insufficiently optimized, or it is necessary to form the pixel potential at a position as deep as possible. There is a problem that a certain overflow barrier OFB becomes shallow as compared with the case where the pixel potential is optimized, or the substrate voltage required for the reset operation or the electronic shutter operation becomes too large.

FIGS. 7 and 8 show an amplification type solid-state image pickup device according to the present invention, in particular, its pixel MOS, in which the above problems are improved.
A further preferred fifth embodiment of the transistor is shown. However,
7 is a plan view of only the pixel MOS transistor with the signal line, vertical selection line, contact buffer layer, and drain power supply line in FIG. 1 omitted, and FIG. 8 shows a cross section taken along line CC of FIG.

In this example, as shown in FIGS. 7 and 8, a semiconductor layer of the second conductivity type, that is, an n type, is formed on the silicon semiconductor substrate 41 of the first conductivity type, for example, p type, as in the above-described embodiments. That is, the overflow barrier region 42 and the p-type semiconductor well region 43 are formed. Further, a p-type charge storage well region that constitutes a channel, that is, a so-called sensor well region 44 is formed, and a ring-shaped that allows light to pass through the p-type sensor well region 44 through a gate insulating film 45 made of SiO ₂ or the like. The gate electrode 23 is formed. An ion implantation method by self-alignment is performed on the semiconductor surface corresponding to the center hole and the outer periphery of the ring-shaped gate electrode 23, in this example, so that the gate electrode 23 is sandwiched between the semiconductor surface reaching the p-type semiconductor well region from the sensor well region. Then, an n-type source region 24 and a drain region 25 are formed respectively.

In this example, an n-type impurity region 47 is further formed in the p-type semiconductor well region 43 below the drain region 25 (that is, at a position deeper than the drain region 25) and the source region is formed. P-type semiconductor well region 4 under 24 (that is, deeper than the source region)
3, a p-type overflow control region 46 is formed, and a pixel MOS transistor 2 which becomes one pixel is formed therein.
6E is formed.

The impurity region 47 functions as a channel stop region for the signal charge h (see FIG. 18) accumulated in the sensor well region 44 below the gate electrode 23, as described above.

The n-type impurity region 47 has the same structure as described above.
It may be formed so as to extend from the drain region 25 to the overflow barrier region 42, or both regions 25 may be formed.
And 42, but not while forming a potential dip from the drain region 25 to the overflow barrier region 42.
5 and the overflow barrier region 42, that is, so that the p-type semiconductor well region 43 exists between the impurity region 47 and the overflow barrier region 42, and between the n-type impurity region 47 and the drain region 25. You may make it so that 43 may exist. FIG. 8 shows the drain region 25 and the overflow barrier region 42.
This is an example in which an n-type impurity region 47 is formed in the middle of. n
In the signal charge accumulation state by controlling the impurity concentration of the type impurity region 47, its potential is shallower than the potential of the overflow barrier region 42, and the drain region 25.
It is set to be deeper than the potential of.

The impurity concentration of the n-type impurity region 47 is set so that no potential dip is formed when the signal charge h is discharged to the substrate 41 by the reset operation or the electronic shutter operation, for example. Therefore, the n-type impurity concentration is set lower than the impurity concentration of the drain region 25 and higher than the impurity concentration of the overflow barrier region 42.

The n-type impurity region 47 can preferably be formed so as to partially overlap the drain region 25 and the gate portion as shown in FIGS. 7 and 8, but otherwise as shown in FIG. In addition, it may be formed only under the entire region of the drain region 25, or may be formed corresponding to a part of the drain region 25 as shown in FIG.

The impurity concentration of the p-type overflow control region 46 corresponding to the source region 24 is set to a value between the sensor well region 44 and the overflow barrier region 42 similarly to the above-mentioned overflow control region.

The mutual relation of the impurity concentrations of the p-type silicon semiconductor substrate 41, the p-type semiconductor well region 43, the p-type overflow control region 46, and the p-type sensor well region 44 is the highest in the sensor well region 44 as described above. , P-type silicon semiconductor substrate 41, p-type overflow control region 62, p-type semiconductor well region 4
It becomes low in order of 3. That is, the p-type semiconductor well region 4
3 is the lowest.

P-type overflow control area 4
6, it is preferable that the source region 24 is formed so as to partially overlap the gate portion as shown in FIGS. 7 and 8, but in addition, as shown in FIG. It may be formed so as to correspond to only part of the source region 24, or may be formed so as to correspond to a part of the source region 24 as shown in FIG.

Next, an example of a method of manufacturing the amplification type solid-state image pickup device including the pixel MOS transistor 26E will be described with reference to FIGS.

In this example, as shown in FIG. 13A, p
After sequentially forming an n-type overbarrier region, a p-type semiconductor well region 43, and a p-type sensor well region 44 on the type silicon substrate 41, a gate insulating film 45 of, for example, SiO ₂ is formed on the surface of the p-type sensor well region 44. For example, it is deposited by the CVD method.

Next, as shown in FIG. 13B, on the gate insulating film 45, at a position corresponding to a drain region to be formed later, in this example, it is wider than the drain region, that is, it extends over the drain region and a part of the gate portion. A first photoresist mask 69 having an opening 68 having a width is formed, and an n-type impurity 70 is ion-implanted through this photoresist mask 69, and inside the p-type semiconductor well region 43 at a position deeper than the sensor well region 44. Then, an n-type impurity region 47 to be a channel stop region is formed. At this time, ion implantation is adjusted so that a potential dip cannot be formed between the overflow barrier region 42 and a drain region formed thereafter. The optimum energy for ion implantation of the n-type impurity region 47, the dose amount, the presence / absence of overlap (overlap), the line width, etc. are determined by the size and shape of the pixel MOS transistor, the width of the drain region, and the surface of the overflow barrier region. It is set according to the depth.

Next, as shown in FIG. 13C, after removing the first photoresist mask 69, the gate insulating film 45 is removed.
At the position corresponding to the source region to be formed later,
In this example, a second photoresist mask 73 having an opening 72 wider than the source region, that is, extending over the source region and a part of the gate portion is formed, and a p-type impurity (for example, through the second photoresist mask 73) is formed. 74)
Are ion-implanted to form a p-type overflow control region 46 in the p-type semiconductor well region 43 at a position deeper than the sensor well region 44. At this time, ion implantation is adjusted so that a potential dip cannot be formed between the overflow barrier region 42 and the source region formed thereafter.

P-type overflow control area 46
The optimum energy for ion implantation, dose, presence / absence of overlap, line width, etc. are set by the size and shape of the pixel transistor, the width of the source region, the depth from the surface of the overflow barrier region, etc. It

Next, as shown in FIG. 14D, after removing the second photoresist mask 73, an electrode material layer to be a gate electrode, for example, a thin polycrystalline silicon layer 23A is formed on the gate insulating film 45 by, for example, the CVD method. Then, the gate electrode 23 is formed by patterning.

Next, as shown in FIG. 14E, the gate electrode 23 is used as an ion implantation mask, or the photoresist mask when the gate electrode is patterned and the gate electrode 23 are used as an ion implantation mask, and an n-type is used. An impurity 75 is ion-implanted to form an n-type source region 24 and a drain region 25 on the surface reaching the p-type semiconductor well region 43 from the sensor well region 44 by self-alignment. The contact, wiring, passivation, etc. are the same as those of a normal MOS transistor.

In this way, the n-type impurity region 47 is formed under the drain region 25 so as to partially overlap the gate portion, and the p-type overflow control is performed under the source region so as to partially overlap the gate portion. The target pixel MOS transistor 26E in which the region 46 is formed is obtained.

According to the amplification type solid-state image pickup device 21 having the pixel MOS transistor 26E of this example, the n-type impurity region 47 is formed under the drain region 25 and the p-type overflow control is formed under the source region 24 of the pixel MOS transistor 26E. By forming the regions 46 independently and without overlapping, it is possible to optimize the blooming suppression, the potential in each region of the pixel, the position of the overflow barrier, the substrate voltage required for the reset or the electronic shutter, and the like.

That is, since the impurity concentrations in the source, drain, and gate regions can be optimized independently of each other, as shown in the potential simulation of FIG. 16, a region other than the surface of the drain region 25, that is, the drain region 25 A potential barrier is also formed in this region, and the signal charge h accumulated in the sensor well region 44 below the gate electrode 23 does not flow to the adjacent pixel MOS transistor due to this potential barrier, and blooming is prevented from occurring. In addition, the amount of signal charge in the sensor section is increased, so that the output voltage and the dynamic range can be increased.

Further, the pixel potential can be optimized in various operating states. By optimizing the pixel potential, the position of the overflow barrier OFB becomes deep, and the red sensitivity can be improved. Further, the substrate voltage V _Sub value at the time of resetting or electronic shutter can be kept within a practical range, thereby reducing power consumption.
Furthermore, simplification of narrowing down pixel formation conditions can be achieved.

In the above example, the n-channel type has been described as the pixel MOS transistor, but the same applies to the p-channel type.

[0074]

According to the amplification type solid-state imaging device of the present invention, the first conductivity type overflow control region is formed in the entire pixel at a position deeper than the gate portion in the first conductivity type semiconductor region forming the amplification type pixel transistor. Because it is formed
The depth from the surface to the overflow barrier is substantially increased, the overall sensitivity can be improved, and a spectral balance can be obtained. Further, the substrate voltage at the time of resetting or the electronic shutter can be reduced.

Further, when a second-conductivity-type impurity region having a lower impurity concentration than the drain region is formed under the second-conductivity-type drain region and at least a first-conductivity-type overflow control region is formed under the gate portion, In addition to the above effects, it is possible to suppress the occurrence of blooming, increase the signal charge amount, and increase the output voltage, the dynamic range, and the like.

Further, according to the amplification type solid-state imaging device of the present invention, the second impurity type impurity having a lower impurity concentration than the drain region is located below the second conductivity type drain region of the amplification type pixel transistor.
By forming the conductivity type impurity region and forming the first conductivity type overflow control region below the source region, the impurity concentration of each of the source, drain and gate regions can be set independently. It is possible to set the potential of each region independently.

For this reason, blooming can be suppressed. In addition, the amount of signal charge, output voltage, and dynamic range can be increased. It is possible to optimize the pixel potential in various operating states.

The position of the overflow barrier can be made deeper from the surface, and the red sensitivity can be improved. That is, it is possible to improve the overall sensitivity and obtain a spectral balance. The substrate voltage value at the time of resetting or at the time of electronic shutter can be kept within a practical range, and power consumption can be reduced. Furthermore, simplification of narrowing down pixel formation conditions can be achieved.

According to the method for manufacturing an amplification type solid-state image pickup device according to the present invention, it is possible to easily and accurately manufacture the amplification type solid-state image pickup device which can obtain the above effects.

[Brief description of drawings]

FIG. 1 is a plan view showing a basic configuration example of an amplification type solid-state imaging device according to the present invention.

FIG. 2 is a plan view of an example showing only pixel MOS transistors.

FIG. 3 is a cross-sectional view corresponding to a BB cross section of FIG. 2 showing a first embodiment of a pixel MOS transistor according to the present invention.

FIG. 4 is a cross-sectional view showing a second embodiment of the pixel MOS transistor according to the present invention and corresponding to the BB cross section of FIG. 2.

FIG. 5 is a cross-sectional view showing a third embodiment of the pixel MOS transistor according to the present invention and corresponding to the BB cross section of FIG. 2.

FIG. 6 is a cross-sectional view showing a fourth embodiment of a pixel MOS transistor according to the present invention, the cross-sectional view corresponding to the BB cross section of FIG. 2;

FIG. 7 is a plan view of another example showing only the pixel MOS transistor according to the present invention.

8 is a cross-sectional view taken along line CC of FIG. 7 showing a fifth embodiment of the pixel MOS transistor according to the present invention.

FIG. 9 is a plan view showing still another example of only the pixel MOS transistor according to the present invention.

FIG. 10 is a plan view showing still another example of only the pixel MOS transistor according to the present invention.

FIG. 11 is a plan view showing still another example of only the pixel MOS transistor according to the present invention.

FIG. 12 is a plan view showing still another example of only the pixel MOS transistor according to the present invention.

13A is a manufacturing process diagram illustrating an example of a method of manufacturing an amplification type solid-state imaging device according to the present invention. FIG. B is a manufacturing process diagram illustrating an example of a method of manufacturing an amplification type solid-state imaging device according to the present invention. C is a manufacturing process diagram illustrating an example of a method of manufacturing an amplification type solid-state imaging device according to the present invention.

FIG. 14 is a manufacturing process diagram showing an example of a method of manufacturing the amplification type solid-state imaging device according to the present invention. E is a manufacturing process diagram illustrating an example of a method of manufacturing an amplification type solid-state imaging device according to the present invention.

FIG. 15 is a potential diagram of a pixel MOS transistor according to a second example.

FIG. 16 is a potential diagram of the pixel MOS transistor according to the fifth example.

FIG. 17 is a plan view of an amplification type solid-state imaging device according to a comparative example.

18 is a cross-sectional view taken along the line AA of FIG.

FIG. 19 is a plan view of only a pixel MOS transistor of a comparative example.

20 is a cross-sectional view taken along the line DD of FIG.

FIG. 21 is a potential diagram of a pixel MOS transistor according to a comparative example.

FIG. 22 is a potential diagram of a pixel MOS transistor according to a comparative example.

[Explanation of symbols]

21 amplification type solid-state imaging device, 23 gate electrode, 24
Source region, 25 Drain region, 26, 26A, 26
B, 26C, 26D, 26E Pixel MOS transistor, 41 p type semiconductor substrate, 42 n type overflow barrier region, 43 p type semiconductor well region, 44 p type sensor well region, 45 gate insulating film, 46 p type overflow control region, 47 , 48 n-type impurity region, 50 repelled region

Claims (6)

[Claims] 1. A second conductivity type overflow barrier region and a first conductivity type semiconductor region are sequentially formed on a first conductivity type semiconductor substrate, and a second conductivity type source region is formed in the first conductivity type semiconductor region.
An amplification type pixel transistor including a second conductivity type drain region and a gate part is formed, and a first conductivity type overflow control region is formed at a position deeper than the gate part in the first conductivity type semiconductor region and over the entire pixel. An amplification type solid-state imaging device characterized by being formed. 2. A second conductivity type overflow barrier region and a first conductivity type semiconductor region are sequentially formed on a first conductivity type semiconductor substrate, and a second conductivity type source region is formed in the first conductivity type semiconductor region.
An amplification type pixel transistor including a second conductivity type drain region and a gate portion is formed, and a second conductivity type impurity region having a lower impurity concentration than the drain region is formed at a position below the drain region in the first conductivity type semiconductor region. An amplification type solid-state imaging device, which is formed and has a first conductivity type overflow control region formed at least under the gate portion. 3. A second conductivity type overflow barrier region and a first conductivity type semiconductor region are sequentially formed on a first conductivity type semiconductor substrate, and a second conductivity type source region is formed in the first conductivity type semiconductor region.
An amplification type pixel transistor including a second conductivity type drain region and a gate portion is formed, and a second conductivity type impurity region having a lower impurity concentration than the drain region is formed at a position below the drain region in the first conductivity type semiconductor region. An amplification type solid-state imaging device, which is formed and has a first conductivity type overflow control region formed below the source region. 4. The impurity region of the second conductivity type is formed so as to correspond to part or all of the drain region or partially overlap the gate part, and the overflow control region of the first conductivity type is formed. The amplification type solid-state imaging device according to claim 3, wherein the amplification type solid-state imaging device is formed so as to correspond to part or all of the source region or to partially overlap the gate part. 5. A step of sequentially forming a second conductivity type overflow barrier region and a first conductivity type semiconductor region on a first conductivity type semiconductor substrate, and forming a gate insulating film on the first conductivity type semiconductor region. A first conductivity type overflow control region at a position below the source region in the first conductivity type semiconductor region by ion implantation, and a second conductivity type impurity region at a position corresponding to below the drain region, respectively. A step of selectively forming, and forming a ring-shaped gate electrode on the gate insulating film,
An amplification type solid-state imaging device, comprising: forming a amplification type pixel transistor by forming a second conductivity type source region and a drain region on the surface of the first conductivity type semiconductor region using the gate electrode as a mask. Manufacturing method. 6. The overflow control region of the first conductivity type corresponds to part or all of a source region,
Alternatively, the impurity region of the second conductivity type is formed so as to partially overlap with the gate portion, and the impurity region of the second conductivity type is formed so as to correspond to part or all of the drain region or partially overlap with the gate portion. The method for manufacturing an amplification type solid-state imaging device according to claim 5.