JPH09283759A - Self-aligned contact forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a withstand voltage between a gate electrode and plug interconnection by forming an etch stop film thick enough on the corners of LDD side walls. SOLUTION: A first etch stop layer 16 and SiO2 offset insulation layer 18 are formed on a gate electrode layer. Gate electrodes are formed, second etch stop layer 20 is formed on the entire surface of the substrate and etched back to expose a gate oxide film at contact-forming regions and form LDD side walls 20. An interlayer insulation film 22 is formed and etched to form connecting holes. Owing to the existence of the offset insulation film 18, a sufficiently thick etch stop film 20 can be obtained on the corners 26 of the side walls 20. Thus it is possible to realize a self-aligned contact having a high reliability of electric contact.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a method of forming a self-aligned contact of a semiconductor device, and more particularly,
The present invention relates to a method capable of forming a self-aligned contact having high withstand voltage and high reliability with respect to electrical contact between a wiring plug and its contact region.

[0002]

BACKGROUND OF THE INVENTION As seen in recent VLSI or the like, with the progress of high integration and performance of semiconductor devices have been required to further increase the wiring density, silicon oxide (SiO ₂₎ system With respect to the technique of forming a contact hole by dry-etching a material layer, technical requirements for increasing the wiring density have become more and more severe. Therefore, a self-aligned contact (hereinafter abbreviated as SAC) forming technique eliminates a design margin on a mask, which is conventionally required for alignment in a contact hole forming process, and thereby wiring is performed. It is drawing attention as a technology that can increase the density.

The development of SAC technology has been particularly active to realize semiconductor devices of the 0.25 μm rule and later generations, and as pointed out in the February 1995 issue of Nikkei Microdevices, the background is There are several reasons. The first reason is that it is technically difficult to further improve the performance of the exposure apparatus in response to the miniaturization of the design rule, and therefore it is an attempt to cope with the miniaturization of the design rule by the SAC technology. The second reason is an attempt to positively reduce the area of a chip or a cell by using the SAC technology as well as making the design rule finer.

In particular, the first reason is that even if an exposure machine developed for mass production of semiconductor devices to which the 0.25 μm rule is applied tries to cope with the trend of miniaturization of wiring layers, it is not possible due to the performance of the exposure machine. This is due to the difficulty. That is, since it is difficult to improve the positional alignment variation of the stepper so as to satisfy the 0.25 μm rule, the positional alignment variation during patterning becomes large, and it is necessary to increase the design margin of the positional alignment. As a result, there arises a problem that the wiring width becomes thick and the requirements of the design rule cannot be satisfied, or the diameter of the connection hole becomes too small so that it cannot be opened by etching. The symptom of this problem arises from the generation of the 0.3 μm rule.
It is said that it is unlikely that the problems will be avoided in the generation of ~ 0.2 μm rule.

The SAC technique is a technique that can eliminate the design margin for this alignment. There are several methods of forming the SAC, and each of them is a little more complicated than the conventional method using only exposure. The most actively studied SAC formation method is a method of using Si ₃ N ₄ as an etching stopper when etching the SiO ₂ interlayer insulating film to form a connection hole. This method has an advantage that the cost increase is relatively small because the number of exposure steps does not increase.

Besides, there are a method of using a metal layer as an etching stop layer, a method of using an insulating film other than Si ₃ N ₄ , and the like. However, although the method of using a metal material is reliable, it is generally difficult to use because a problem such as halation occurs in the exposure process. The method of using an insulating film other than Si ₃ N ₄ has a weak point that it is necessary to use a film with a poor track record as an LSI process.

By the way, in order to put the SAC technique using Si ₃ N ₄ as a stopper into practical use, it is necessary to clear the etching technique having a high degree of difficulty. Specifically, in order to stop the etching on the thin Si ₃ N ₄ layer, S
It is necessary to increase the selection ratio of SiO ₂ and Si ₃ N ₄ at the time of etching iO ₂ , and various attempts have been made for that purpose. The high selection ratio process with respect to Si ₃ N ₄ varies depending on the discharge method of the device, but is, for example, 19
As reported in Spring 1994 Proceedings of the Japan Society of Applied Physics 29p-ZF-2 (Harashima, Furuo, Akimoto, Ikawa), basically a CF-based protective film is used to reduce the etching rate of SiO _2. It is solidifying in a direction to prevent it by using high-density plasma.

[0008]

However, the problem with Si
It is difficult to establish an etching process suitable for SAC formation that can increase the ₃ N ₄ selection ratio and maintain the anisotropy of SiO ₂ etching, and the conventional method can achieve a satisfactory SA.
C could not be formed. Where SiO ₂ Li
A conventional method of forming a SAC having a Si ₃ N ₄ layer as an etching stop layer on a ghtly Doped Drain (LDD) sidewall will be briefly described. In the conventional SAC forming method, first, as shown in FIG.
An SiO ₂ layer 91, a poly-Si layer 92, and an offset SiO ₂ layer 93 are sequentially formed on the upper surface, and then gate processing and LDD implantation are performed. Then, the SiO ₂ LDD sidewall layer 94
Film is formed and etched back to form LDD sidewall 94
Are formed, and implantation for Source / Drain (S / D) formation is performed. Further, a Si ₃ N ₄ etching stop layer 95 and a SiO ₂ interlayer insulating film 96 are formed, a resist layer 97 is applied and exposed, and a contact hole 98 is formed by etching according to the pattern of the resist layer 97. Thereby, the substrate structure as shown in FIG. 9A is obtained.

By the way, according to the conventional method, the interlayer insulating film 9 is formed.
CF deposited on the Si ₃ N ₄ layer when etching 6
By using the system protective film, the etching selection ratio of SiO ₂ and Si ₃ N ₄ is improved. However, in the conventional etching process, the corner portion 9 of the LDD sidewall 94 is
The Si ₃ N ₄ etch stop layer 95 on 9 has an electrode layer 9
The CF-based protective film is less likely to be deposited than on the Si ₃ N ₄ etching layer 95 in the flat portion of 2,93. As a result, in the Si ₃ N ₄ etching stop layer 95 on the corner 99 of the LDD sidewall 94, the Si of the flat portion of the electrode layers 92 and 93 is Si.
Above the ₃ N ₄ etching stop layer 95, the selection ratio cannot be increased. Therefore, the interlayer insulating film 96 is etched, and the bottom of the contact hole is S on the Si substrate 90.
By the time it reaches the i ₃ N ₄ etch stop layer 95, the Si ₃ N ₄ layer 95 on the corner 99 is etched faster and thinner (see FIG. 9A).

Subsequently, in order to make contact with the substrate 90, the Si ₃ N ₄ etching layer 95 and the SiO ₂ layer 91 on the Si substrate 90 are etched to open connection holes,
As shown in FIG. 9B, the wiring plug 1 is formed. S
Si ₃ N ₄ etching layer 95 and SiO ₂ on i substrate 90
When etching the _two layers 91, the Si ₃
The thickness of the N ₄ etch stop layer 95 is, for thinner than the thickness of the Si ₃ N ₄ etching stop layer 95 on the Si substrate 90, when the necessary etching to make contact, offset SiO ₂ layer 93 It is etched and thinned, and the poly-Si layer 92 is likely to be exposed. As a result, the withstand voltage between the gate electrode and the wiring plug becomes insufficient, and in an extreme case, a short circuit will occur as shown in FIG. 9B. Also, S at the bottom of the contact hole
It is also difficult to perform stable etching of the i ₃ N ₄ etching stop film 95, and the amount of overetching must be increased in order to obtain a reliable contact over the entire surface of the wafer. Will be done.

As one of the measures to improve this problem, L
A SAC structure as shown in FIG. 10 in which a self-aligned contact is formed by using Si ₃ N ₄ for the DD sidewall has been proposed. This structure uses the Si ₃ N ₄ offset insulating layer 2 and the Si ₃ N ₄ LDD sidewall 3 to form the Si ₃ N ₄ etching stop film at the bottom of the contact hole, which was necessary in the SAC forming method of FIG. Eliminating the etching process and improving the breakdown voltage.

However, since the etching of the corner portion 4 of the Si ₃ N ₄ LDD side wall 3 cannot be prevented, there still remains the problem of dielectric strength failure.
As another method, there has been proposed a method of effectively increasing the distance between the corner portion and the gate electrode by increasing the thickness of the Si ₃ N ₄ offset insulating layer. However, in this method, since the Si ₃ N ₄ offset insulating layer becomes thicker, the difference in stress between the gate oxide film and the gate electrode appears remarkably.
There is a concern that damage may occur between the i substrate and the gate oxide film, and the dielectric strength between the gate electrode and the plug wiring may decrease.
As described above, it is difficult to form a self-aligned contact having a high withstand voltage by the conventional method.

In light of the above circumstances, the object of the present invention is to
It is an object of the present invention to provide a method for forming a self-aligned contact capable of ensuring a dielectric strength voltage between a gate electrode and a plug wiring.

[0014]

As a result of extensive studies on the above-mentioned problems, the present inventor has found that the following means for solving can remarkably improve the dielectric strength failure. A solution to this problem is to allow an etching stopper film having a sufficiently large film thickness to exist on the corner portion of the LDD sidewall, and after forming the etching stopper film,
This is a method of preventing the progress of the etching of the corner portion at the time of opening the contact of the interlayer insulating film by exposing the gate oxide film in the contact formation region by etching back the entire surface and remarkably improving the dielectric strength failure. In the first invention method, the first etching stop film having a large film thickness provided on the corner portion is formed by a film forming method such as a CVD method,
In the second and third invention methods, the ion implantation method is used.

In order to achieve the above object, based on the above findings, a method for forming a self-aligned contact according to the present invention (hereinafter referred to as a first invention method) is a self-aligned contact having an LDD sidewall. Forming an offset insulating layer consisting of a first etching stop layer and then a SiO ₂ layer on the gate electrode layer, forming a gate electrode, and further performing a second etching on the entire surface of the substrate. A stop layer is formed, and then the second etching stop layer is etched back to expose the gate oxide film in the contact formation region and the LDD sidewall is formed, and an interlayer insulating film is formed. And a step of forming a connection hole by etching.

A preferred embodiment of the method of the present invention is characterized in that the amount of overetching in the etchback step is set to be equal to or less than the thickness of the SiO ₂ layer forming the offset insulating layer, and the first etching is performed. The stop layer and the second etching stop layer are films containing Si ₃ N ₄ .

In the method of the present invention, the etching stopper layer and the Si forming the offset insulating layer formed on the gate electrode layer are formed.
The O ₂ layer allows a sufficiently thick etch stop layer to be present on the corners of the LDD sidewall. Furthermore, since the selectivity of the etching stopper film to the corner portion is smaller than that of the flat portion in principle, the presence of a sufficiently thick etching stopper film on the corner portion and the second etching stopper layer By etching back the entire surface to expose the gate oxide film in the contact formation region, even if overetching is performed to make sufficient contact with the Si substrate, a dielectric breakdown voltage defect between the gate electrode and the plug wiring occurs. The film thickness is secured so that it does not exist. Therefore, this can prevent a decrease in the dielectric strength of the self-aligned contact.

Another method of forming a self-aligned contact according to the present invention (hereinafter referred to as a second invention method) is mainly a method of forming a self-aligned contact having a Si ₃ N ₄ LDD sidewall. Then, a step of forming an offset insulating layer on the gate electrode, a step of implanting ions in the vicinity of the gate electrode of the offset insulating layer to form a first etching stop layer, and forming a gate electrode, Forming a second etching stop layer on the entire surface of the substrate, and then etching back the second etching stop layer to expose the gate oxide film in the contact formation region and LD
The method is characterized by including an etch-back step of forming a D side wall and a step of forming an interlayer insulating film and etching it to form a connection hole. Preferably, the amount of overetching in the etch back step is suppressed to the extent that the first etching stop layer is not exposed.

Another method of forming a self-aligned contact according to the present invention (hereinafter referred to as a third invention method) is mainly a method of forming a self-aligned contact having a SiO ₂ LDD sidewall. A step of forming an offset insulating layer on the gate electrode, and a step of implanting ions into the vicinity of the gate electrode and the surface layer of the offset insulating layer to form two first etching stop layers sandwiching the offset insulating layer. A step of forming a gate electrode and then an LDD sidewall, a step of forming a second etching stop layer on the entire surface of the substrate, and a step of etching back the first etching stop layer on the surface, and interlayer insulation. And forming a connection hole by etching.

In the second and third invention methods, the first method for forming the first etching stop layer is to form a SiO ₂ layer as an offset insulating layer and ion-implant nitrogen into the SiO ₂ layer. , A SiO ₂ layer having a predetermined thickness is made into Si _x N _y O
_It is converted to a _z- layer to function as a first etch stop layer. At that time, preferably, nitrogen is ion-implanted into the SiO ₂ layer so that the composition ratio of N and O in the Si _x N _y O _z layer is _y >> _z . The second method of forming the first etching stop layer is to form a Si ₃ N ₄ layer as an offset insulating layer,
Oxygen is ion-implanted into the Si ₃ N ₄ layer to form Si of a predetermined thickness.
_{The 3} N ₄ layer is oxidized into a Si _x N _y O _z layer to function as a first etch stop layer. At that time, preferably, Si _x
S so that the composition ratio of N and O of the N _y O _z layer is _y << _z.
Oxygen is ion-implanted into the i ₃ N ₄ film.

[0021]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The method of the present invention suppresses thinning of the corner portion of the LDD sidewall, which is a cause of breakdown voltage degradation, and
The point is the process of forming a sufficiently thick etching stop layer on the corner portion of the D sidewall. In principle, the selectivity ratio of the etching stopper film to the corner portion is smaller than that of the flat portion. Therefore, the principle of improving the withstand voltage defect is to perform an etch-back with an amount of over-etching sufficient to make sufficient contact with the Si substrate when the contact hole is opened, by forming a sufficiently thick etching stop film on the corner portion. In other words, it is necessary to secure a film thickness that does not cause a breakdown voltage defect between the gate electrode and the plug wiring.

A commercially available CVD apparatus, etching apparatus or the like can be used for the process of forming a sufficiently thick etching stopper film on the corner portion of the present invention. Further, by applying the method of the present invention, SA corresponding to the device structure can be obtained.
C, for example, a SAC having a single-layer or multi-layer LDD structure, a SAC having a multi-layer offset insulating layer structure including an antireflection film used at the time of gate processing can be formed. And SixOyNz
When the above antireflection film is used, it can also be used as an etching stop film. Further, in order to etch back the SiO ₂ layer in the LDD sidewall having a multi-layer structure, an etching stopper layer having a required thickness may be formed on the offset SiO ₂ layer. Examples 1 to 4 described below are examples of the first invention method, and examples 5 to 12 are examples of the second invention method. In the first to twelfth examples, the film thickness of each film, the film forming method, and the etching method of each film are examples for description, and the present invention is not limited thereto.

[0023]

EXAMPLE 1 This example shows an example in which the method of the present invention is applied to the formation of SAC having Si ₃ N ₄ LDD sidewalls. The offset insulating layer of this example has a SiO ₂ / Si ₃ N ₄ structure, and the etching stop layer and the LDD sidewall are formed of Si ₃ N ₄ . In this embodiment, first,
A film thickness of 10 is sequentially formed on the Si substrate 10 by a dry oxidation method.
of the SiO ₂ film 12 having a thickness of 10 nm by the low pressure CVD method.
The 0 nm poly-Si layer 14 is used as a first etching stop layer to form an offset Si ₃ N ₄ layer 16 having a film thickness of 100 nm by the low pressure CVD method, and further an offset SiO ₂ layer 18 having a film thickness of 100 nm is formed by the low pressure CVD method. Filmed Then, gate processing and LDD implantation were performed to obtain a substrate having a laminated structure shown in FIG.

Then, a 200 nm-thickness Si ₃ N ₄ film is formed on the entire surface of the substrate having the laminated structure shown in FIG.
The LDD sidewall layer 20 was formed as a second etching stop layer. Then, with using the etcher magnetron method, performed 250nm and etching back the entire surface of the pair SiO ₂ high selectivity condition the SiO ₂ layer in terms, the contact formation region 21 to expose the SiO ₂ film 12, LD
The D sidewall 20 was formed. Next, Source / Dr
Implantation for forming ain (S / D) was performed to obtain a substrate having a laminated structure shown in FIG.

Next, an interlayer insulating film 22 having a film thickness of 800 nm is formed on the substrate having the laminated structure shown in FIG. 1B, a resist layer 24 is applied and exposed, and the laminated film shown in FIG. A structure substrate was obtained. Through the above steps, in this embodiment, as shown in FIG.
As shown in (c), the presence of the offset SiO ₂ layer 18 made it possible to obtain a sufficiently thick Si ₃ N ₄ film 20 at the corner portion 26 of the LDD sidewall 20.

Next, with respect to the substrate having the laminated structure shown in FIG. 2C, a pair S is formed by using a magnetron type etcher.
Etching was performed until the Si substrate 10 was exposed under the condition of high i ₃ N ₄ selection ratio to obtain a substrate having a laminated structure having a shape shown in FIG. 2D. At this time, the Si ₃ N ₄ layer of the corner portion 26 of the LDD sidewall 20 is etched,
Since the initial film thickness is sufficiently thick, a predetermined withstand voltage can be secured.

In the present embodiment, through the above steps, the Si substrate in the contact formation region is exposed, and a connection hole having a Si ₃ N ₄ LDD sidewall with a thickness sufficient to obtain a predetermined withstand voltage is opened. did it. Therefore, it is possible to realize a self-aligned contact with high withstand voltage and high reliability of electrical contact.

Example 2 In this example, an antireflection film was formed on the gate electrode, and Si ₃
It is an example in which the present invention is applied to the formation of SAC using N ₄ for the LDD sidewall. The gate electrode of this embodiment is WS
The offset insulating layer is formed as a SiO ₂ / Si ₃ N ₄ / SixOyNz structure as the ix / Poly-Si structure, and the etching stop layer and the LDD sidewall are formed as Si ₃ N ₄ .

In this embodiment, first, on the Si substrate 30,
Sequentially, a SiO ₂ film 1 having a film thickness of 10 nm is formed by a dry oxidation method.
No. 2 was formed by a low pressure CVD method into a poly-film having a film thickness of 100 nm.
The Si layer 34 is formed into a W film having a thickness of 100 nm by the low pressure CVD method.
The Six layer 36 has a film thickness of 27 nm formed by the plasma CVD method.
Of the SixOyNz antireflection film 38, an offset Si ₃ N ₄ layer 40 having a film thickness of 100 nm by the low pressure CVD method, and an offset S having a film thickness of 100 nm by the low pressure CVD method.
Each of the iO ₂ layers 42 was deposited. Then, gate processing and LDD implantation were performed to obtain a substrate having a laminated structure shown in FIG.

Next, a 200 nm-thickness Si ₃ N film is formed on the entire surface of the substrate having the laminated structure shown in FIG.
The _four layers 44 is formed and exposed then, using the etcher magnetron method, performed 250nm and etching back the entire surface of the pair SiO ₂ high selectivity condition the SiO ₂ layer terms of SiO ₂ film 12 in the contact region 45 And let L
The DD sidewall 44 was formed. Next, Source /
Implantation for forming Drain (S / D) was performed to obtain a substrate having a laminated structure shown in FIG.

Next, an interlayer insulating film 46 having a film thickness of 800 nm is formed on the substrate having the laminated structure shown in FIG. 3B, a resist layer 48 is applied, and exposure is performed, as shown in FIG. 4C. A substrate having a laminated structure was obtained. Through the above steps, in this embodiment, as shown in FIG.
As shown in (c), the presence of the offset SiO ₂ layer 42 made it possible to obtain a sufficiently thick Si ₃ N ₄ film 44 at the corner portion 49 of the LDD sidewall 44.

Next, with respect to the substrate having the laminated structure shown in FIG. 4C, a pair S is formed by using a magnetron type etcher.
i ₃ N ₄ Etching was performed until the Si ₃ N ₄ on the Si substrate was exposed under the condition of high selection ratio to obtain a laminated structure having a shape shown in FIG. At this time, LDD sidewall 4
Although the Si ₃ N ₄ layer in the corner portion 49 of No. ₄ is etched, the initial film thickness is sufficiently thick, so that a predetermined withstand voltage can be secured.

In the present embodiment, through the above steps, the Si substrate in the contact formation region is exposed, and a connection hole having a Si ₃ N ₄ LDD sidewall with a thickness sufficient to obtain a predetermined withstand voltage is opened. did it. Therefore, it is possible to realize a self-aligned contact with high withstand voltage and high reliability of electrical contact. Further, although the WSix layer has an effect of increasing the reliability of the gate electrode, halation may occur during exposure after resist application. Therefore, in this embodiment, an antireflection film is formed on the WSix layer to suppress it.

Example 3 In this example, the method of the present invention was applied to the formation of SAC using a film having both an antireflection function and an etching stop function on the gate electrode and using Si ₃ N ₄ as the LDD sidewall. Here is an example: The gate electrode of this embodiment is Poly-Si /
As a SixOyNz structure, the offset insulating layer is SiO 2.
₂ / SixOyNy structure, and the etching stop layer and the LDD sidewall are formed of Si ₃ N ₄ .

In this embodiment, first, on the Si substrate 50,
Sequentially 10 nm thick SiO ₂ film 5 by dry oxidation method
No. 2 was formed by a low pressure CVD method into a poly-film having a film thickness of 100 nm.
The Si layer 54 has a film thickness of 100 nm formed by the plasma CVD method.
The SixOyNz antireflection film 56 of
The offset SiO ₂ layers 58 having a film thickness of 100 nm were formed by the respective methods. Then, gate processing and LDD implantation were performed to obtain a substrate having a laminated structure shown in FIG.

Then, a 200 nm-thickness Si ₃ N film is formed on the entire surface of the substrate having the laminated structure shown in FIG.
₄ forming a LDD sidewall layer 60, then, using the etcher magnetron method, the entire surface is etched back pair SiO ₂ high selectivity condition the SiO ₂ layer in terms 250n
Then, the SiO ₂ film 52 is exposed in the contact formation region 61 and the LDD sidewall 60 is formed. Then, implantation for Source / Drain (S / D) formation was performed to obtain a substrate having a laminated structure shown in FIG.

Next, an interlayer insulating film 62 having a film thickness of 800 nm is formed on the substrate having the laminated structure shown in FIG. 5B, a resist layer 64 is applied and exposed to light, as shown in FIG. 6C. A substrate having a laminated structure was obtained. Through the above steps, in this embodiment, as shown in FIG.
As shown in (c), due to the presence of the offset SiO ₂ layer 58, a sufficiently thick Si ₃ N ₄ film 60 could be obtained at the corner portion 66 of the LDD sidewall 60.

Next, with respect to the substrate having the laminated structure shown in FIG. 6C, a pair S is formed by using a magnetron type etcher.
Etching was performed until the Si substrate 50 was exposed under the condition of high i ₃ N ₄ selection ratio to obtain a laminated structure shown in FIG. 6D. At this time, the Si ₃ N ₄ layer in the corner portion 66 of the LDD sidewall 60 is etched, but since the initial film thickness is sufficiently thick, a sufficient withstand voltage can be secured.

In this embodiment, through the above steps, the Si substrate in the contact formation region is exposed, and a connection hole having a Si ₃ N ₄ LDD sidewall with a thickness sufficient to obtain a predetermined withstand voltage is opened. did it. Therefore, it is possible to realize a self-aligned contact with high withstand voltage and high reliability of electrical contact. Further, it is an advantage that one step can be reduced by the gate processing as compared with the second embodiment.

Example 4 In this example, SiO ₂ was used for the LDD sidewall,
It is an example in which the method of the present invention is applied to the formation of SAC having a Si ₃ N ₄ etching stop layer on its sidewall.
The offset insulating layer of this embodiment is made of Si ₃ N ₄ / SiO ₂ /
As the Si ₃ N ₄ structure, the LDD sidewall is made of SiO 2.
₂ / Si ₃ N ₄ structure, and S
The i ₃ N ₄ LDD sidewall is used as an etch stop layer.

In this embodiment, first, on the Si substrate 70,
The SiO ₂ film 7 having a film thickness of 10 nm is sequentially formed by the dry oxidation method.
No. 2 was formed by a low pressure CVD method into a poly-
A first offset Si ₃ N ₄ layer 76 having a film thickness of 100 nm is formed by the low pressure CVD method, and an offset SiO ₂ layer 78 having a film thickness of 100 nm and a second offset Si ₃ N layer having a film thickness of 100 nm are further formed by the low pressure CVD method. _Four layers 80 were formed respectively. Then, gate processing and LDD implantation were performed to obtain a substrate having a laminated structure shown in FIG.

Next, a 200 nm thick SiO ₂ layer for forming LDD sidewalls was formed on the entire surface of the substrate having the laminated structure shown in FIG. 7A by the low pressure CVD method. afterwards,
Using etcher magnetron method, versus SiO ₂
The total etch back under high selection conditions is 35 in terms of SiO ₂ layer.
The LDD sidewall 80 was formed by performing 0 nm. Then, implantation for Source / Drain (S / D) formation was performed. Further, a 100 nm-thickness Si ₃ N ₄ etching stop layer 8 is formed on the entire surface of the substrate by a low pressure CVD method.
2 was deposited to obtain a substrate having a laminated structure shown in FIG.

Next, with the entire surface is etched back of the substrate pair SiO ₂ highly selective conditions of the laminated structure shown in FIG. 7 (b), with the contact formation region 83 to expose the SiO ₂ film 72, FIG. 8 (c As shown in FIG. 8A, the etching stopper layer 82 of a sufficiently thick Si ₃ N ₄ film could be formed on the corner portion 88.

Next, an interlayer insulating film 84 having a film thickness of, for example, 800 nm is formed on the substrate having the laminated structure shown in FIG.
Further, a resist layer 86 is applied and exposed, and the interlayer insulating film 84 is exposed until the Si substrate 70 is exposed under the condition of a high selection ratio with respect to Si ₃ N ₄ using, for example, a magnetron type etcher.
Was etched to obtain a substrate having a laminated structure shown in FIG. At this time, the Si ₃ N ₄ etching stop layer 82 in the corner portion 88 becomes thin, but the SiO ₂ LDD sidewall is sufficiently protected, so that a predetermined withstand voltage can be secured.

In this embodiment, through the above steps, the Si substrate in the contact formation region is exposed, and a connection hole having a Si ₃ N ₄ LDD sidewall with a thickness sufficient to obtain a predetermined withstand voltage is opened. did it. Therefore, it is possible to realize a self-aligned contact with high withstand voltage and high reliability of electrical contact. In addition, as in Example 1, Si ₃ N ₄ was LDD
In the case where the sidewall is used, there is a concern that the reliability of electrical connection may be deteriorated due to hot electron injection, but in the case of the present embodiment, the injection can be suppressed, so that the reliability is improved.

Example 5 This example is an example in which the second invented method is applied to the formation of the SAC used for the Si ₃ N ₄ LDD sidewall. In this embodiment, first, a SiO ₂ film 100 having a film thickness of 10 nm is sequentially deposited on a Si substrate by a dry oxidation method under reduced pressure CVD.
The poly-Si layer 101 having a film thickness of 100 nm by
200 nm thick offset SiO by low pressure CVD method
_Two layers 102 were formed to obtain a substrate having a laminated structure shown in FIG. Next, nitrogen is implanted into the entire surface of the substrate by an ion implantation method, and as shown in FIG.
An offset Si _x O _y N _z layer 1 having a film thickness of 100 nm as a first etching stop layer in the vicinity of the layer (gate electrode) 101.
03 was formed. At this time, nitrogen is implanted so that the composition ratio of O and N of the Si _x O _y N _z layer 103 becomes y << z.
Next, as shown in FIG. 11C, the laminated structure of the substrate was processed with a gate electrode to form an LDD implantation region 104. Subsequently, a 200 nm-thickness Si ₃ N ₄ layer 105 was formed on the entire surface of the substrate by a low pressure CVD method.
Then, using a magnetron type etcher,
O ₂ layer is etched back to a thickness of 250 nm under a high selective ratio condition, and Si _{3 which} also functions as a second etching stop layer is formed.
The N ₄ LDD sidewall 105 was formed. Further, a Source / Drain (S / D) implantation layer 106 was formed by ion implantation to obtain a substrate having a laminated structure shown in FIG. 11 (d).

Next, an interlayer SiO ₂ layer 1 having a film thickness of 800 nm
07 was deposited, a resist layer 108 was applied, and patterning was performed to obtain a substrate having a laminated structure shown in FIG. Through the above steps, as shown in FIG. 12E, Si ₃ N ₄ having a sufficiently thick film is formed on the corner portion 109 of the substrate.
A film is formed. Further, using a magnetron type etcher, etching is performed under a high selection ratio condition with respect to Si ₃ N ₄ until the Si substrate is exposed to open a connection hole.
A substrate having a laminated structure as shown in 1 (f) was obtained. In this embodiment, when the connection hole is opened, the Si ₃ N ₄ layer in the corner portion 109 of the Si ₃ N ₄ LDD sidewall 105 is also etched, but since the initial film thickness is sufficiently thick, at the end of etching, S with a thickness that can ensure the specified dielectric strength
The i ₃ N ₄ layer can be left in the corner portion 109. Therefore, it is possible to realize a self-aligned contact that exposes the Si substrate and further includes the Si ₃ N ₄ LDD sidewall having a predetermined withstand voltage.

Example 6 This example is another example in which the second invention method is applied to the formation of the SAC used for the Si ₃ N ₄ LDD sidewall, and unlike Example 5, the offset Si ₃ Oxygen is injected into the N ₄ layer to form a two-layer offset structure. In this embodiment, first, a SiO ₂ film 100 having a thickness of 10 nm is sequentially formed on a Si substrate by a dry oxidation method, a poly-Si layer 101 having a thickness of 100 nm is formed by a low pressure CVD method, and a low pressure C
An offset Si ₃ N ₄ layer 110 having a film thickness of 200 nm was formed by the VD method to obtain a substrate having a laminated structure shown in FIG. Then, oxygen is implanted into the entire surface of the substrate by an ion implantation method to form a first offset Si _x O _y N _z layer 103 having a film thickness of 100 nm in the vicinity of the Poly Si layer (gate electrode) 101 as shown in FIG. Was formed as an etching stop layer. At this time, oxygen is injected so that the composition ratio of N and O of the offset Si _x O _y N _z layer 103 becomes y >> z. Subsequently, in the same manner as in Example 5, FIG.
As shown in FIG. 3, the gate electrode is processed to form the LDD implantation region 104, and the film thickness is 200 n.
forming a Si ₃ N ₄ layer 105 m, it serves as a second etch stop layer is etched back Si ₃ N ₄ LD
The D side wall 105 was formed, and the S / D implantation layer 106 was formed to obtain a substrate having a laminated structure shown in FIG. Further, as in the case of Example 5, FIG.
As shown in FIG. 4 (e), an interlayer insulating film is formed, patterned, and etched to open a connection hole.
A substrate having a laminated structure shown in (f) was obtained.

In the present embodiment, as in the case of the fifth embodiment, when the connection hole is opened, S having a thickness that can ensure a predetermined withstand voltage at the corner portion 109 of the Si ₃ N ₄ LDD sidewall 105.
Since the i ₃ N ₄ layer can be left, Si ₃ N ₄ L which exposes the Si substrate and has a predetermined withstand voltage
Self-aligned contacts with DD sidewalls can be realized.

Example 7 This example has a structure in which a gate electrode having a Poly-Si / WSix structure and an antireflection film on the gate electrode are provided, and Si ₃ N ₄ LD is used.
It is an example in which the second invention method is applied to the formation of the SAC using the D sidewall. In this embodiment, first, a SiO film having a thickness of 10 nm is sequentially formed on a Si substrate by a dry oxidation method.
₂ film 100 is formed by a low pressure CVD method to a p thickness of 100 nm.
The ly-Si layer 101 is formed to a film thickness of 10 by the low pressure CVD method.
The 0 nm WSix layer 111 is formed into a 27 nm-thick Si _x O _y N _z : H antireflection film 112 by plasma CVD.
Further, an offset SiO ₂ layer 102 having a film thickness of 200 nm was further formed by a low pressure CVD method to obtain a substrate having a laminated structure shown in FIG. Next, nitrogen is implanted into the entire surface of the substrate by an ion implantation method to form an offset Si _x O having a film thickness of 100 nm on the antireflection film 112 as shown in FIG.
_{The yNz} layer 103 was formed as a first etch stop layer. At this time, O of the offset Si _x O _y N _z layer 103
Nitrogen is injected so that the composition ratio of N and N becomes y << z. Subsequently, in the same manner as in Example 5, as shown in FIG. 15C, the gate electrode is processed to form the LDD implantation region 104, and further, Si _{3 having} a film thickness of 200 nm is formed.
An N ₄ layer 105 is formed and etched back to a thickness of 250 nm to form a Si ₃ N ₄ LDD sidewall 105.
The / D implantation layer 106 is formed, and FIG.
A substrate having a laminated structure shown in (d) was obtained. Further, in the same manner as in Example 5, as shown in FIG. 16E, an interlayer insulating film is formed, patterned, and subjected to etching to open a connection hole, and the laminated structure shown in FIG. The substrate of was obtained.

In the present embodiment, as in the case of the fifth embodiment, when the connection hole is opened, S having a thickness that can secure a predetermined withstand voltage at the corner portion 109 of the Si ₃ N ₄ LDD sidewall 105.
Since the i ₃ N ₄ layer can be left, Si ₃ N ₄ L which exposes the Si substrate and has a predetermined withstand voltage
Self-aligned contacts with DD sidewalls can be realized. Although the Poly-Si / WSix structure has the effect of enhancing the reliability of the gate electrode, halation may occur during exposure after resist application. In this embodiment, however, an antireflection film is formed on the WSix layer. By doing so, halation is suppressed.

Example 8 This example is similar to Example 7 except that Poly-Si / WS is used.
It is another example in which the second invention method is applied to the formation of the SAC using the Si ₃ N ₄ LDD side wall in the structure having the gate electrode of the ix structure and the antireflection film on the gate electrode. In this embodiment, first, a SiO ₂ film 100 having a film thickness of 10 nm is sequentially formed on a Si substrate by a dry oxidation method, a poly-Si layer 101 having a film thickness of 100 nm is formed by a low pressure CVD method, and a film thickness of 100 nm is formed by a low pressure CVD method. The WSix layer 111 of
27 nm thick Si _x O by plasma CVD method
_{The y} N _z : H antireflection film 112 is further formed by a low pressure CVD method to form an offset Si ₃ N ₄ layer 110 having a film thickness of 200 nm as a first etching stop layer, and has a laminated structure shown in FIG. A substrate was obtained. Then, oxygen is implanted into the entire surface of the substrate by an ion implantation method to form a film having a thickness of 100 n on the surface layer of the offset Si ₃ N ₄ layer 110 as shown in FIG.
m offset Si _x O _y N _z layer 103 was formed. At this time, oxygen is injected so that the composition ratio of O and N of the offset Si _x O _y N _z layer 103 becomes y >> z. continue,
In the same manner as in Example 5, as shown in FIG. 17C, the gate electrode was processed to form the LDD implantation region 104, and further the Si ₃ N ₄ layer 105 having a film thickness of 200 nm was formed. forming a Si ₃ N ₄ LDD sidewalls 105 which also functions as a second etch stop layer is etched back, S / D implantation layer 106
Was formed to obtain a substrate having a laminated structure shown in FIG. Further, as in the case of Example 5, as shown in FIG. 18E, an interlayer insulating film is formed, patterned, and etched to form connection holes, and the laminated structure shown in FIG. The substrate of was obtained.

In the present embodiment, as in the case of the fifth embodiment, when the connection hole is opened, an S having a thickness that can secure a predetermined withstand voltage at the corner portion 109 of the Si ₃ N ₄ LDD sidewall 105.
Since the i ₃ N ₄ layer can be left, Si ₃ N ₄ L which exposes the Si substrate and has a predetermined withstand voltage
Self-aligned contacts with DD sidewalls can be realized. In addition, as in Example 7, the antireflection film is formed of WSi.
By forming a film on the x layer, halation at the time of exposure for opening the connection hole can be suppressed.

Embodiment 9 This embodiment has a structure having a Si _x O _y N _z : H film having both an antireflection function and an etching stop function on a gate electrode.
It is an example in which the second invented method is applied to the formation of the SAC using the Si ₃ N ₄ LDD sidewall. In this embodiment,
First, in the same manner as in the fifth embodiment, FIG.
A substrate having the same laminated structure as that shown in FIG.
(A)). Next, silicon, nitrogen, and hydrogen are implanted into the entire surface of the substrate by an ion implantation method, and as shown in FIG. 19B, a Si _x O _y N _z film having a thickness of 100 nm is formed in the vicinity of the Poly Si layer (gate electrode) 101. : H antireflection film 112
Was formed as an antireflection film and also as a first etching stop layer. At this time, silicon and nitrogen are ion-implanted so that the composition ratios of Si, O, and N of the Si _x O _y N _z : H antireflection film 112 are x> y and x> z. Subsequently, in the same manner as in Example 5, as shown in FIG. 19C, the gate electrode is processed to form the LDD implantation region 10.
4 is formed, and a Si ₃ N ₄ layer 10 having a film thickness of 200 nm is further formed.
Si ₃ N ₄ LDD side wall 10 which also functions as a second etching stop layer by depositing 5 and etching back.
5 was formed and the S / D implantation layer 106 was formed to obtain a substrate having a laminated structure shown in FIG. Further, as in the case of Example 5, as shown in FIG. 20E, an interlayer insulating film is formed, patterned, and etched to form a connection hole, and the laminated structure shown in FIG. The substrate of was obtained.

In the present embodiment, as in the case of the fifth embodiment, when the connection hole is opened, S having a thickness that can secure a predetermined withstand voltage at the corner portion 109 of the Si ₃ N ₄ LDD sidewall 105.
Since the i ₃ N ₄ layer can be left, Si ₃ N ₄ L which exposes the Si substrate and has a predetermined withstand voltage
Self-aligned contacts with DD sidewalls can be realized. Further, in this embodiment, since the antireflection film is formed by ion implantation, the number of gate processing steps can be reduced by one step as compared with the seventh embodiment.

Example 10 In this example, as in Example 9, Si _x O _y N _z having both an antireflection function and an etching stop function on the gate electrode:
It is another example in which the second invented method is applied to the formation of SAC using a Si ₃ N ₄ LDD sidewall with a structure having an H film. In this example, unlike Example 9, silicon, oxygen, and hydrogen were implanted into the offset Si ₃ N ₄ layer to obtain 2
This is a layer offset structure. In this embodiment,
First, in the same manner as in the sixth embodiment, FIG.
A substrate having the same laminated structure as that shown in FIG.
(A)). Then, silicon, oxygen, and hydrogen are implanted into the entire surface of the substrate by an ion implantation method to deposit Si _x O having a film thickness of 100 nm in the vicinity of the Poly Si layer (gate electrode) 101.
_y N _z : H An antireflection film 112 is formed, and then an offset Si ₃ N ₄ layer 110 having a film thickness of 100 nm remaining on the surface layer is formed.
Oxygen was injected into the substrate to convert it into the offset Si _x O _y N _z layer 103 (see FIG. 21B). At this time, the composition ratio of Si, O, and N in the antireflection film Si _x O _y N _z : H112 is x> y and x> z, and further, the offset Si _x O _y N _z.
Silicon and oxygen are implanted so that the composition ratio of O and N of 103 is y >> z. Subsequently, in the same manner as in Example 5, as shown in FIG. 21C, the gate electrode is processed to form the LDD implantation region 104,
Further, a Si ₃ N ₄ layer 105 having a film thickness of 200 nm is formed,
Etch back to form a Si ₃ N ₄ LDD sidewall 105 that also functions as a second etch stop layer,
By forming the S / D implantation layer 106, as shown in FIG.
A substrate having a laminated structure shown in 1 (d) was obtained. Furthermore, Example 5
In the same manner as in FIG. 22 (e), an interlayer insulating film is formed, patterned, and etched to form connection holes, thereby obtaining a substrate having a laminated structure shown in FIG. 22 (f). .

In the present embodiment, as in the case of the fifth embodiment, when the connection hole is opened, S having a thickness that can secure a predetermined withstand voltage at the corner portion 109 of the Si ₃ N ₄ LDD sidewall 105.
Since the i ₃ N ₄ layer can be left, Si ₃ N ₄ L which exposes the Si substrate and has a predetermined withstand voltage
Self-aligned contacts with DD sidewalls can be realized. Further, in this embodiment, since the antireflection film is formed by ion implantation, the number of gate processing steps can be reduced by one step as compared with the seventh embodiment.

Embodiment 11 This embodiment is an example in which the third invention method is applied to the formation of SAC using SiO ₂ LDD sidewalls and providing Si ₃ N ₄ etching stop layer on the sidewalls. In this example, first, except that the thickness of the offset SiO ₂ layer 102 was set to 210 nm, the same laminated structure as that shown in FIG. A substrate was obtained (see FIG. 23 (a)). next,
By implanting nitrogen on the entire surface of the substrate by the ion implantation method
An offset Si _x O _y N _z layer 103 having a thickness of 90 nm is formed as a first etching stop layer in the vicinity of the Si layer (gate electrode) 101, and the remaining offset SiO ₂
Nitrogen is implanted into the surface layer of the layer 102 by an ion implantation method to form an offset Si _x O _y N _z layer 103 having a film thickness of 30 nm, and a Si _x O _y N _z layer / SiO ₂ layer is formed. / Si _x O _y N _z
An offset of a three-layer structure of layers was formed (see FIG. 23 (b)). At this time, nitrogen is implanted so that the composition ratio of O and N of the offset Si _x O _y N _z layer 103 becomes y << z.
Next, as shown in FIG. 23C, the gate electrode was processed to form the LDD implantation region 104. Subsequently, a film thickness 200 for forming the LDD sidewall is formed.
After the SiO ₂ layer 113 having a thickness of ₃ nm is formed by the low pressure CVD method, a magnetron type etcher is used to etch back the film with a thickness of 320 nm under the high selection ratio condition with respect to Si ₃ N _{4 to} obtain S.
An iO ₂ layer LDD sidewall 113 was formed. Next, the S / D implantation area 106 is formed,
Furthermore, a Si ₃ N ₄ etching stop layer 1 having a thickness of 100 nm is formed.
14 was deposited as a second etching stopper layer by a low pressure CVD method to obtain a substrate having a laminated structure as shown in FIG.

Next, under the condition of high selectivity ratio to the SiO ₂ layer, Si ₃
When etching back was performed to a thickness of 150 nm in terms of N ₄ , it was possible to form a sufficiently thick Si ₃ N ₄ film on the corner portion 109, as shown in FIG. Furthermore,
In the same manner as in Example 5, an interlayer insulating film is formed, patterned, and etched to open a connection hole.
A substrate having a laminated structure shown in (f) was obtained.

In this embodiment, the Si ₃ N ₄ layer in the corner portion 109 is also etched when the connection hole is opened, but since the initial film thickness is sufficiently thick, as shown in FIG.
Corner portion 10 of SiO ₂ LDD sidewall 113
In FIG. 9, a Si ₃ N ₄ etching stop layer having a thickness that can ensure a predetermined dielectric strength can be left. Therefore, Si
SiO that exposes the substrate and has a predetermined withstand voltage
₂ Self-aligned contacts with LDD sidewalls can be realized. In addition, as shown in Example 5, LD using Si ₃ N ₄
In the SAC used for the D sidewall, there is a concern that the reliability may deteriorate due to hot electron injection, but in the case of the structure of the present embodiment, the injection can be suppressed, so the reliability of the contact improves.

Example 12 This example is similar to Example 11 except that SiO ₂ LDD sidewalls are used and Si ₃ N _{4 is} deposited on the sidewalls.
Another example is shown in which the third inventive method is applied to the formation of an SAC provided with an etching stop layer. The difference from Example 11 is that oxygen is injected into the offset Si ₃ N ₄ layer to form a three-layer offset structure. In this embodiment, the offset Si ₃
Except that the film thickness of the N ₄ layer 110 is 210 nm,
First, in the same manner as in the sixth embodiment, FIG.
A substrate having the same laminated structure as the laminated structure shown in FIG.
(A)). Next, the offset Si _x O _y N _z layer 103 having a film thickness of 90nm was formed in the center layer of the offset Si ₃ N ₄ 110 layers by injecting oxygen into the whole substrate surface by ion implantation, Si ₃ N ₄ layer / Si _x O _y N _z layer / Si ₃ was formed offset of a three-layer structure of N ₄ layer (see FIG. 25 (b)). At this time, oxygen is implanted so that the composition ratio of the offset Si _x O _y N _z layer 103 becomes y >> z.

Then, as shown in FIG. 25C, the gate electrode is processed in the same manner as in Example 11 to form the LDD implantation region 104, and the LDD is further formed.
A SiO ₂ layer 113 for forming a sidewall is formed and etched back to form an SiO ₂ layer LDD sidewall 113.
Was formed. Next, an S / D implantation region 106 is formed, and a Si ₃ N ₄ etching stop layer 114 is further formed as a second etching stop layer.
A substrate having a laminated structure as shown in (d) was obtained. Then, in the same manner as in Example 11, as shown in FIG. 26 (e), etching back is performed to form an interlayer insulating film, patterning, and etching are performed to open connection holes. The substrate of the laminated structure shown in () was obtained.

In this embodiment, similarly to the eleventh embodiment, when the connection hole is opened, S having a thickness that can ensure a predetermined withstand voltage at the corner portion 109 of the SiO ₂ LDD sidewall 113.
Since the i ₃ N ₄ layer can be left, the SiO ₂ LD that exposes the Si substrate and has a predetermined withstand voltage
A self-aligned contact with a D sidewall can be realized. Further, the structure of this embodiment is similar to that of the eleventh embodiment.
Since the hot electron injection can be suppressed, the contact reliability is improved.

Although the present invention has been described based on the twelfth embodiment, it is needless to say that the present invention is not limited to the above-mentioned embodiments, and the etching plasma source, the device configuration, the laminated structure, and the etching. It goes without saying that the process conditions such as can be appropriately selected without departing from the scope of the present invention.

[0065]

According to the first invention method, a step of forming an offset insulating layer composed of a first etching stop layer and a SiO ₂ layer, which are sequentially formed on a gate electrode, and LDD
A step of forming a sidewall, a step of forming a second etching stop layer on the entire surface of the substrate, and then etching back the second etching stop layer to expose the gate oxide film in the contact formation region. A step of forming an interlayer insulating film and etching back to form a connection hole, and forming a sufficiently thick etching stop layer on a corner portion of the LDD sidewall causes deterioration in breakdown voltage. It prevents thinning of the corners of the LDD sidewall. Further, according to the second invention method, the method includes a step of forming an offset insulating layer on the gate electrode, and a step of implanting ions to form the first etching stop layer inside the offset insulating layer. By forming a sufficiently thick etching stopper layer on the corners of the LDD sidewalls, the thinning of the corners of the LDD sidewalls, which causes the breakdown voltage, is prevented.

As a result, the etching stopper film used for the offset insulating layer is thickened and the gate Si
The thickness of the LDD sidewall sufficient to obtain a dielectric breakdown voltage without causing stress between the O ₂ film or the gate electrode layer and the etching stop layer and causing a decrease in reliability of the gate SiO ₂ film. Self-aligned contacts with can be realized.

[Brief description of drawings]

1A and 1B are cross-sectional views of a substrate for each step of a first embodiment of a method for forming a self-aligned contact according to the present invention.

2 (c) and 2 (d) are views of Embodiment 1 of the method for forming a self-aligned contact according to the present invention, respectively.
It is a board sectional view for each process following (b).

3 (a) and 3 (b) are cross-sectional views of a substrate for each step of Embodiment 2 of the method for forming a self-aligned contact according to the present invention.

4 (c) and 4 (d) are views of Embodiment 2 of the method for forming a self-aligned contact according to the present invention, respectively.
It is a board sectional view for each process following (b).

5 (a) and 5 (b) are cross-sectional views of a substrate for each step of Example 3 of the method for forming a self-aligned contact according to the present invention.

6 (c) and 6 (d) are diagrams of Embodiment 3 of the method for forming a self-aligned contact according to the present invention, respectively.
It is a board sectional view for each process following (b).

7 (a) and 7 (b) are cross-sectional views of a substrate for each step of Example 4 of the method for forming a self-aligned contact according to the present invention.

8 (c) and 8 (d) are views of Embodiment 4 of the method for forming a self-aligned contact according to the present invention, respectively.
It is a board sectional view for each process following (b).

9A and 9B are cross-sectional views of a substrate in each step of a conventional method for forming a self-aligned contact.

FIG. 10 is a cross-sectional view of a substrate of a self-aligned contact formed by a conventional method.

11 (a) to 11 (d) are cross-sectional views of a substrate for each step of Example 5 of the method for forming a self-aligned contact according to the present invention.

12 (e) and 12 (f) are views of Embodiment 5 of the method for forming a self-aligned contact according to the present invention, respectively.
It is a board sectional view for each process following 1 (d).

13 (a) to 13 (d) are cross-sectional views of a substrate for each step of Example 6 of the method for forming a self-aligned contact according to the present invention.

14 (e) and 14 (f) are views of Example 6 of the method for forming a self-aligned contact according to the present invention, respectively.
It is a board sectional view for each process following 3 (d).

15 (a) to 15 (d) are cross-sectional views of a substrate for each step of Example 7 of the method for forming a self-aligned contact according to the present invention.

16 (e) and 16 (f) are respectively FIG. 1 of Example 7 of the method for forming a self-aligned contact according to the present invention.
FIG. 5C is a cross-sectional view of the substrate for each step subsequent to 5 (d).

17 (a) to 17 (d) are cross-sectional views of a substrate for each step of Example 8 of the method for forming a self-aligned contact according to the present invention.

18 (e) and 18 (f) are respectively FIG. 1 of Example 8 of the method for forming a self-aligned contact according to the present invention.
FIG. 7C is a sectional view of a substrate in each step following 7 (d).

19 (a) to 19 (d) are cross-sectional views of a substrate for each step of Example 9 of the method for forming a self-aligned contact according to the present invention.

20 (e) and 20 (f) are views of Embodiment 9 of the method for forming a self-aligned contact according to the present invention, respectively.
FIG. 9C is a cross-sectional view of the substrate for each step subsequent to 9 (d).

21 (a) to 21 (d) are cross-sectional views of a substrate for each step of Example 10 of the method for forming a self-aligned contact according to the present invention.

22 (e) and 22 (f) are cross-sectional views of the substrate in each step subsequent to FIG. 21 (d) of Example 10 of the method for forming a self-aligned contact according to the present invention.

23A to 23D are cross-sectional views of a substrate in each step of Example 11 of the method for forming a self-aligned contact according to the present invention.

24 (e) and 24 (f) are cross-sectional views of the substrate in each step subsequent to FIG. 23 (d) of Example 11 of the method for forming a self-aligned contact according to the present invention.

25 (a) to 25 (d) are cross-sectional views of the substrate in each step of Example 12 of the method for forming a self-aligned contact according to the present invention.

26E and 26F are cross-sectional views of the substrate in each step following FIG. 25D of Example 12 of the method for forming a self-aligned contact according to the present invention.

[Explanation of symbols]

10 ... Si substrate, 12 ... SiO ₂ film, 14 ... po
ly-Si layer, 16 ... Offset Si ₃ N ₄ layer, 18
...... Offset SiO ₂ layer, 20 …… Si ₃ N ₄ layer, 2
2 ... Interlayer insulating film, 24 ... Resist layer, 26 ... Corner portion, 30 ... Si substrate, 32 ... SiO ₂ film, 34
...... Poly-Si layer, 36 ...... WSix layer, 38 ......
Antireflection film, 40 ... Offset Si ₃ N ₄ layer, 42 ...
… Offset SiO ₂ layer, 44 …… Si ₃ N ₄ layer, LD
D sidewall, 46 ... Interlayer insulating film, 48 ... Resist layer, 49 ... Corner portion, 50 ... Si substrate, 52
...... SiO ₂ film, 54 …… poly-Si layer, 56 ……
Antireflection film, 58 ... Offset SiO ₂ layer, 60 ...
Si ₃ N ₄ layer, LDD sidewall, 62 ... Interlayer insulating film, 64 ... Resist layer, 66 ... Corner portion, 70
...... Si substrate, 72 …… SiO ₂ film, 74 …… poly
-Si layer, 76 ...... first offset Si ₃ N ₄ layers, 78
...... Offset SiO ₂ layer, 80 …… Second offset S
i ₃ N ₄ layer LDD sidewall, 82 ... Si ₃ N ₄
Etching stop layer, 84 ... Interlayer insulating film, 86 ... Resist layer, 88 ... Corner portion, 90 ... Si substrate, 91
...... SiO ₂ film, 92 ・ ・ ・ poly-Si layer, 93 ・ ・ ・
Offset SiO ₂ layer, 94 ... SiO ₂ LDD sidewall layer, LDD sidewall, 95 ... Si ₃ N
₄ Etching stop layer, 96 ... SiO ₂ interlayer insulating film, 9
7 ...... resist layer, 98 ...... connection hole, 99 ...... corners, 1 ...... interconnect plug, 2 ...... Si ₃ N ₄ offset insulating layer, 3 ...... Si ₃ N ₄ LDD sidewall, 4 ......
Corner, 100 ... SiO ₂ film, 101 ... Pol
y-Si, 102 ... Offset SiO ₂ layer, 103 ...
... offset Si _x O _y N _z film, 104 ... LDD implantation region, 105 ... Si ₃ N ₄ LDD sidewall, 106 ... Source / Drain
(S / D) Implantation region, 107 ... Inter-layer Si ₃ N ₄ film, 111 ... WSix, 112 ... Si _x
O _y N _z -H antireflection film, 113 ...... SiO ₂ LDD sidewalls, 114 ...... Si ₃ N ₄ etching stop layer.

Claims (10)

[Claims] 1. A method of forming a self-aligned contact with an LDD sidewall, comprising: a first etch stop layer over the gate electrode layer and then Si.
A step of forming an offset insulating layer including an O ₂ layer, forming a gate electrode, further forming a second etching stop layer on the entire surface of the substrate, and then etching back the second etching stop layer. And exposing the gate oxide film in the contact formation region and forming an LDD sidewall, and a step of forming an interlayer insulating film and etching to form a connection hole. Method of forming a matching contact. 2. The method for forming a self-aligned contact according to claim 1, wherein the amount of overetching in the etchback step is set to be equal to or less than the thickness of the SiO ₂ layer forming the offset insulating layer. 3. The method for forming a self-aligned contact according to claim 1, wherein the first etching stop layer and the second etching stop layer are films containing Si ₃ N ₄ . 4. A method of forming a self-aligned contact having an LDD sidewall, comprising a step of forming an offset insulating layer on a gate electrode, and implanting ions in the vicinity of the gate electrode of the offset insulating layer to form a first insulating layer. Forming an etching stopper layer, forming a gate electrode, forming a second etching stopper layer on the entire surface of the substrate, and then etching back the second etching stopper layer to form a contact formation region. A method of forming a self-aligned contact, comprising: an etchback step of exposing a gate oxide film and forming an LDD sidewall; and a step of forming an interlayer insulating film and etching to form a connection hole. 5. The method for forming a self-aligned contact according to claim 4, wherein the amount of overetching in the etchback step is within a range that does not expose the first etching stop layer. 6. A method of forming a self-aligned contact having an LDD sidewall, comprising a step of forming an offset insulating layer on a gate electrode, and implanting ions into the vicinity of the gate electrode and the surface layer of the offset insulating layer. , A step of forming two first etching stop layers sandwiching the offset insulating layer, a step of forming a gate electrode and then an LDD sidewall, and a step of forming a second etching stop layer on the entire surface of the substrate. Then, a method of forming a self-aligned contact, comprising: a step of etching back the first etching stop layer on the surface layer; and a step of forming an interlayer insulating film and etching to form a connection hole. 7. forming a SiO ₂ layer as an offset insulating layer, the nitrogen in the SiO ₂ layer by ion implantation, the first to convert the SiO ₂ layer of a predetermined thickness on the Si _x N _y O _z layer 5. It functions as an etching stop layer.
7. The method for forming a self-aligned contact according to any one of items 1 to 6. 8. The composition ratio of N and O of the Si _x N _y O _z layer is y.
The method for forming a self-aligned contact according to claim 7, wherein nitrogen is ion-implanted into the SiO ₂ layer so that z becomes >> z. 9. A film of Si ₃ N ₄ layer as the offset insulating layer, oxygen ions are implanted into Si ₃ N ₄ layer, a Si ₃ N ₄ layer having a predetermined thickness on the Si _x N _y O _z layer 7. The method for forming a self-aligned contact according to claim 4, wherein the self-aligned contact is oxidized to function as a first etching stop layer. 10. The method according to claim 9, wherein oxygen is ion-implanted into the Si ₃ N ₄ film so that the composition ratio of N and O in the Si _x N _y O _z layer is _y << _z . Method of forming self-aligned contact.