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JPH09283693A - High frequency semiconductor device - Google Patents

High frequency semiconductor device

Info

Publication number
JPH09283693A
JPH09283693A JP8908096A JP8908096A JPH09283693A JP H09283693 A JPH09283693 A JP H09283693A JP 8908096 A JP8908096 A JP 8908096A JP 8908096 A JP8908096 A JP 8908096A JP H09283693 A JPH09283693 A JP H09283693A
Authority
JP
Japan
Prior art keywords
substrate
ground conductor
dielectric film
high frequency
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8908096A
Other languages
Japanese (ja)
Other versions
JP3081786B2 (en
Inventor
Kenjiro Nishikawa
健二郎 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP8908096A priority Critical patent/JP3081786B2/en
Publication of JPH09283693A publication Critical patent/JPH09283693A/en
Application granted granted Critical
Publication of JP3081786B2 publication Critical patent/JP3081786B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To realize compactness and high integration by mounting a multilayer mode-high frequency circuit chip which is formed to multi-layer and has a grounding conductor by flip chip mounting on a mounting board formed by forming a dielectric film and a wiring layer in multi-layer on a semiconductor board by using a bump. SOLUTION: A mounting board 1 is constituted of a semiconductor board 3, a multilayer dielectric film 7 formed thereon and a grounding conductor 9 formed in a rear of the mounting board 1. A control circuit 12, etc., are formed on the semiconductor substrate 3. A pad for connection with a high frequency circuit chip 2 is formed in a surface of a dielectric film uppermost layer of the mounting board 1 and the multilayer-mode high frequency circuit chip 2 is connected thereto by a face-down structure through a bump 4 formed on a pad. The semiconductor substrate 3, the dielectric film 7 and the grounding conductor 9 are formed in the multilayer-mode high frequency circuit chip 2. Since a circuit can be formed also on a mounting board immediately below the high frequency circuit chip 2 mounted in this way, compactness and high integration can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、例えば1GHz以
上の高周波信号を処理する半導体装置に関し、特に高周
波半導体装置の小形化、高集積化を図ると共に、ミリ波
領域まで良好な高周波特性を得ることのできる高周波半
導体装置に係る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for processing a high frequency signal of, for example, 1 GHz or more, and particularly to downsizing and high integration of the high frequency semiconductor device and obtaining good high frequency characteristics up to the millimeter wave region. The present invention relates to a high-frequency semiconductor device that can be manufactured.

【0002】[0002]

【従来の技術】半導体基板上に誘電体膜と配線層を多層
に形成して高周波回路を形成する多層化高周波回路チッ
プを、実装基板上に実装する方法として、金等で構成さ
れる半田バンプを用い、フェイスダウン構造で接続され
るフリップチップ実装が用いられている。
2. Description of the Related Art A solder bump made of gold or the like is used as a method for mounting a multi-layered high-frequency circuit chip in which a dielectric film and wiring layers are formed in multiple layers on a semiconductor substrate to form a high-frequency circuit on a mounting substrate. Flip-chip mounting, which is connected in a face-down structure, is used.

【0003】図4は、従来の多層化高周波回路のフリッ
プチップ実装について説明する図であって、(a)は斜
視図、(b)はAA断面図を示している。(b)の断面
図では、その断面の様子を理解し易くするため誘電体部
の断面については斜線を施さないで示している。これ
は、以降に説明する他の図においても同様である。
4A and 4B are views for explaining flip-chip mounting of a conventional multi-layered high frequency circuit, wherein FIG. 4A is a perspective view and FIG. 4B is a sectional view taken along line AA. In the cross-sectional view of (b), the cross section of the dielectric portion is shown without hatching in order to facilitate understanding of the state of the cross section. This is the same in other drawings described below.

【0004】同図において、数字符号1は実装基板、2
は高周波回路チップ、3は半導体基板、4はバンプ、5
はFET、6はキャパシタ、7は誘電体膜、8は線路、
9は接地導体、10は信号線用バンプパッド、11はス
ルーホールを表わしている。
In the figure, numeral 1 is a mounting board, 2
Is a high frequency circuit chip, 3 is a semiconductor substrate, 4 is a bump, 5
Is an FET, 6 is a capacitor, 7 is a dielectric film, 8 is a line,
Reference numeral 9 is a ground conductor, 10 is a signal line bump pad, and 11 is a through hole.

【0005】このような多層化高周波回路のフリップチ
ップ実装法については、1995 IEEEMTT-S International
Microwave Symposium で発表されている。このような
従来の構成では、多層化高周波回路チップ2の誘電体膜
7の最上層面に接地導体9と信号線用パッド10を形成
し、バンプ4により実装基板1上の信号線10が接地導
体9に接続されている。
A flip-chip mounting method for such a multi-layered high frequency circuit is described in 1995 IEEEMTT-S International.
Presented at the Microwave Symposium. In such a conventional configuration, the ground conductor 9 and the signal line pad 10 are formed on the uppermost layer surface of the dielectric film 7 of the multilayer high-frequency circuit chip 2, and the signal line 10 on the mounting substrate 1 is grounded by the bump 4. 9 is connected.

【0006】従って、フリップチップ実装された後でも
チップ上に形成される高周波回路と実装基板とが接地導
体9により電気的に隔離されるため、高周波回路が実装
基板の影響を受けないという利点があるので、一般的に
多く用いられていた。
Therefore, even after the flip-chip mounting, the high frequency circuit formed on the chip and the mounting board are electrically isolated by the ground conductor 9, so that the high frequency circuit is not affected by the mounting board. Therefore, it was commonly used.

【0007】[0007]

【発明が解決しようとする課題】上述したような従来の
半導体装置の構成では、マイクロバンプを用いた実装方
法の場合、バンプの高さが数μmしかなく、多層化高周
波回路チップを実装する直下の実装基板上には、回路を
形成することが困難であるため、制御回路やIF回路等
を実装基板の他の領域に形成しなければならなかったか
ら、実装基板の面積が大きくなるという問題があった。
In the structure of the conventional semiconductor device as described above, in the case of the mounting method using the micro bumps, the height of the bumps is only a few μm, which is directly under the multilayer high frequency circuit chip. Since it is difficult to form a circuit on the mounting board of, the control circuit, the IF circuit, and the like had to be formed in another region of the mounting board, which causes a problem that the area of the mounting board becomes large. there were.

【0008】一方、スタッドバンプを用いた場合にはバ
ンプ高さが数十μm〜百数十μmとなり、実装基板上に
も回路形成は可能となるが、バンプ寸法が大きいために
これが不要なインダクタンスとなり、高周波特性が劣化
するという問題があった。
On the other hand, when the stud bumps are used, the bump height becomes several tens of μm to hundreds of tens of μm, and a circuit can be formed on the mounting substrate, but since the bump size is large, this is unnecessary inductance. Therefore, there is a problem that the high frequency characteristics are deteriorated.

【0009】また、従来構成では、チップ上の接地導体
が誘電体膜最上層上にのみ存在するために、半導体基板
上に形成されるFETや容量や伝送線路を接地導体に接
続する際に、長いスルーホールを使用する必要があり、
スルーホール寸法が不要なインダクタンスとなるために
高周波特性が劣化するという問題があった。
Further, in the conventional structure, since the ground conductor on the chip exists only on the uppermost layer of the dielectric film, when connecting the FET, the capacitor or the transmission line formed on the semiconductor substrate to the ground conductor, You have to use long through holes,
There is a problem that the high frequency characteristics are deteriorated because the dimension of the through hole becomes an unnecessary inductance.

【0010】特に、ミリ波帯においてはスルーホール寸
法の影響が大きく、これが回路特性を劣化する要因の1
つとなっていた。本発明は、高周波半導体装置の小形・
高集積化とミリ波領域まで良好な高周波特性を示す高周
波半導体装置を実現することを目的としている。
Particularly, in the millimeter wave band, the influence of the through hole size is large, which is one of the factors that deteriorate the circuit characteristics.
It was one. The present invention is a small-sized high-frequency semiconductor device
The objective is to realize a high-frequency semiconductor device that exhibits high integration and good high-frequency characteristics in the millimeter wave region.

【0011】[0011]

【課題を解決するための手段】本発明によれば、上述の
課題は前記特許請求の範囲に記載した手段により解決さ
れる。
According to the present invention, the above-mentioned object is solved by the means described in the claims.

【0012】すなわち、請求項1の発明は、半導体基板
上に誘電体膜と配線層とを多層に形成して成る実装基板
上に、半導体基板上に誘電体膜と配線層とを多層に形成
して成り、その一方の面に接地導体を有する多層化高周
波回路チップを、前記接地導体面が、実装基板の一方の
面の誘電体膜と向き合うように、バンプを用いてフリッ
プチップ実装した高周波半導体装置である。
That is, according to the first aspect of the present invention, the dielectric film and the wiring layer are formed in multiple layers on the semiconductor substrate on the mounting substrate formed by forming the dielectric film and the wiring layer in multiple layers on the semiconductor substrate. A multi-layered high-frequency circuit chip having a ground conductor on one surface thereof is flip-chip mounted using bumps so that the ground conductor surface faces the dielectric film on one surface of the mounting substrate. It is a semiconductor device.

【0013】請求項2の発明は、誘電体基板上に誘電体
層と配線層とを多層に形成して成る実装基板上に、半導
体基板上に誘電体膜と配線層とを多層に形成して成り、
その一方の面に接地導体を有する多層化高周波回路チッ
プを、前記接地導体面が、実装基板の一方の面の誘電体
膜と向き合うように、バンプを用いてフリップチップ実
装した高周波半導体装置である。
According to a second aspect of the present invention, a dielectric film and wiring layers are formed in multiple layers on a semiconductor substrate on a mounting substrate formed by forming dielectric layers and wiring layers in multiple layers on a dielectric substrate. Consists of
A high-frequency semiconductor device in which a multilayered high-frequency circuit chip having a ground conductor on one surface thereof is flip-chip mounted using bumps so that the ground conductor surface faces the dielectric film on one surface of the mounting substrate. .

【0014】請求項3の発明は、請求項1、または、請
求項2記載の高周波半導体装置において、実装基板上
に、IF回路、A/D変換回路、D/A変換回路、ディ
ジタル回路および制御回路等を形成したものである。
According to a third aspect of the present invention, in the high frequency semiconductor device according to the first or second aspect, an IF circuit, an A / D conversion circuit, a D / A conversion circuit, a digital circuit and a control are provided on a mounting board. A circuit or the like is formed.

【0015】請求項4の発明は、半導体基板上に誘電体
膜と配線層とを多層に形成して成り、その一方の面の少
なくとも一部に接地導体を有する実装基板上に、半導体
基板上に誘電体膜と配線層とを多層に形成して成り、そ
の一方の面に接地導体を有する多層化高周波回路チップ
を、多層化高周波回路チップの接地導体面が、実装基板
の接地導体面と向き合うように、バンプを用いてフリッ
プチップ実装した高周波半導体装置である。
According to a fourth aspect of the present invention, the dielectric film and the wiring layer are formed in multiple layers on a semiconductor substrate, and a mounting substrate having a ground conductor on at least a part of one surface thereof is provided on the semiconductor substrate. A multi-layered high-frequency circuit chip having a dielectric conductor and a wiring layer formed in multiple layers and having a ground conductor on one surface thereof, and the ground conductor surface of the multi-layered high-frequency circuit chip is the same as the ground conductor surface of the mounting substrate. The high-frequency semiconductor device is flip-chip mounted using bumps so as to face each other.

【0016】請求項5の発明は、誘電体基板上に誘電体
膜と配線層とを多層に形成して成り、その一方の面の少
なくとも一部に接地導体を有する実装基板上に、半導体
基板上に誘電体膜と配線層とを多層に形成して成り、そ
の一方の面に接地導体を有する多層化高周波回路チップ
を、多層化高周波回路チップの接地導体面が、実装基板
の接地導体面と向き合うように、バンプを用いてフリッ
プチップ実装した高周波半導体装置である。
According to a fifth aspect of the present invention, the dielectric film and the wiring layer are formed in multiple layers on the dielectric substrate, and the semiconductor substrate is provided on the mounting substrate having the ground conductor on at least a part of one surface thereof. A multi-layered high-frequency circuit chip having a dielectric film and a wiring layer formed thereon in a multi-layered manner and having a grounding conductor on one surface thereof, wherein the grounded conductor surface of the multi-layered high-frequency circuit chip is It is a high-frequency semiconductor device that is flip-chip mounted using bumps so as to face with.

【0017】請求項6の発明は、請求項4または請求項
5記載の高周波半導体装置において、実装基板上に、I
F回路、A/D変換回路、D/A変換回路、ディジタル
回路および制御回路等を形成したものである。
According to a sixth aspect of the present invention, in the high frequency semiconductor device according to the fourth or fifth aspect, I is mounted on the mounting substrate.
An F circuit, an A / D conversion circuit, a D / A conversion circuit, a digital circuit and a control circuit are formed.

【0018】請求項7の発明は、請求項1〜請求項6の
いずれか1項に記載の高周波半導体装置において、実装
基板と、これに実装された多層化高周波回路チップの内
少なくとも一方が、多層化された複数の誘電体膜の内の
複数の誘電体膜面に接地導体を有するように構成したも
のである。
According to a seventh aspect of the present invention, in the high-frequency semiconductor device according to any one of the first to sixth aspects, at least one of the mounting board and the multilayered high-frequency circuit chip mounted on the mounting board is It is configured to have a ground conductor on a plurality of dielectric film surfaces among a plurality of multilayered dielectric films.

【0019】本発明の高周波半導体装置においては、実
装基板として誘電体膜を多層に積層して、形成した基板
を用いることにより、高周波回路チップを実装した直下
の実装基板に制御回路やディジタル回路等を形成できる
ために、高周波半導体装置の小形・高集積化を実現でき
る。さらに、実装基板最上層に接地導体を形成したもの
では、高周波回路チップと実装基板上に形成される回路
間の理想的なアイソレーションを実現できる。
In the high frequency semiconductor device of the present invention, by using a substrate formed by laminating dielectric films in multiple layers as a mounting substrate, a control circuit, a digital circuit or the like is mounted on the mounting substrate directly below the high frequency circuit chip. Therefore, the high-frequency semiconductor device can be downsized and highly integrated. Further, in the case where the ground conductor is formed on the uppermost layer of the mounting board, ideal isolation between the high frequency circuit chip and the circuit formed on the mounting board can be realized.

【0020】また、複数の誘電体膜上に接地導体を形成
した構成を採るものにおいては、いずれの層から接地す
る場合でも、最短の距離で接地することができる。従っ
て、スルーホールが、不要なインダクタンスとなること
が無く、ミリ波領域まで良好な高周波特性を維持でき
る。
Further, in the case where the grounding conductor is formed on a plurality of dielectric films, the grounding can be performed in the shortest distance regardless of which layer is grounded. Therefore, the through hole does not become unnecessary inductance, and good high frequency characteristics can be maintained even in the millimeter wave region.

【0021】[0021]

【発明の実施の形態】図1は本発明の実施の形態の第1
の例の高周波半導体装置を示す図であって、断面図を示
している。同図において、数字符号1は実装基板、2は
高周波回路チップ、3は半導体基板、4はバンプ、5は
FET、6はキャパシタ、7は誘電体膜、8は線路、9
は接地導体、10は信号線用バンプパッド、11はスル
ーホール、12は制御回路、13はIF回路を表わして
いる。
FIG. 1 shows a first embodiment of the present invention.
It is a figure which shows the high frequency semiconductor device of the example of FIG. In the figure, reference numeral 1 is a mounting substrate, 2 is a high-frequency circuit chip, 3 is a semiconductor substrate, 4 is a bump, 5 is an FET, 6 is a capacitor, 7 is a dielectric film, 8 is a line, and 9 is a line.
Is a ground conductor, 10 is a signal line bump pad, 11 is a through hole, 12 is a control circuit, and 13 is an IF circuit.

【0022】実装基板1は半導体基板3とその上に形成
される多層の誘電体膜と実装基板1の裏面に形成される
接地導体9より構成されている。半導体基板3(実装基
板)上に、制御回路12やIF回路13等が半導体プロ
セスにより形成される。上記半導体基板3(実装基板)
と制御回路12やIF回路13上に誘電体膜がスピンコ
ーティング等により多層に形成され、上記誘電体膜上に
複数の伝送線路や接地導体が形成される。
The mounting substrate 1 comprises a semiconductor substrate 3, a multi-layered dielectric film formed thereon, and a ground conductor 9 formed on the back surface of the mounting substrate 1. The control circuit 12, the IF circuit 13 and the like are formed on the semiconductor substrate 3 (mounting substrate) by a semiconductor process. The semiconductor substrate 3 (mounting substrate)
A dielectric film is formed in multiple layers on the control circuit 12 and the IF circuit 13 by spin coating or the like, and a plurality of transmission lines and ground conductors are formed on the dielectric film.

【0023】さらに実装基板1の誘電体膜最上層面には
高周波回路チップ2との接続用のパッドが形成され、上
記パッド上に形成したバンプ4を介して、多層化高周波
回路チップ2をフェイスダウン構造で接続する。多層化
高周波回路チップ2は半導体基板3(高周波回路チッ
プ)上に、多層化された誘電体膜を形成し、その最上層
面に接地導体を形成し、かつ複数の誘電体膜上に接地導
体を形成している。
Further, a pad for connection with the high frequency circuit chip 2 is formed on the uppermost surface of the dielectric film of the mounting substrate 1, and the multilayer high frequency circuit chip 2 is faced down through the bumps 4 formed on the pad. Connect by structure. The multilayered high-frequency circuit chip 2 has a multilayered dielectric film formed on a semiconductor substrate 3 (high-frequency circuit chip), a ground conductor formed on the uppermost layer surface thereof, and a ground conductor formed on a plurality of dielectric films. Is forming.

【0024】以上のように構成された高周波半導体装置
は、実装した高周波回路チップの直下の実装基板上にも
回路を形成することができるために、高周波半導体装置
の小形・高集積化が実現できる。
In the high frequency semiconductor device configured as described above, a circuit can be formed on the mounting substrate directly below the mounted high frequency circuit chip, and therefore, the high frequency semiconductor device can be made compact and highly integrated. .

【0025】また、この高周波回路チップ2は複数の誘
電体膜上に接地導体を形成しているので、いずれの層か
ら接地する場合でも、最短の距離で接地することがで
き、スルーホールが、不要なインダクタンスとなること
が無く、ミリ波領域まで良好な高周波特性を維持でき
る。
Further, since the high-frequency circuit chip 2 has ground conductors formed on a plurality of dielectric films, it can be grounded from any layer in the shortest distance, and the through holes are An unnecessary inductance does not occur, and good high frequency characteristics can be maintained even in the millimeter wave region.

【0026】なお、実装基板に使われる半導体基板3
は、例えば、アルミナ等のセラミック多層基板や上記セ
ラミック多層基板上に多層の誘電体膜を形成した多層実
装基板やガラスエポキシ系の多層基板等の多層プリント
基板であってもよい。
The semiconductor substrate 3 used as the mounting substrate
May be, for example, a ceramic multilayer substrate made of alumina or the like, a multilayer mounting substrate in which a multilayer dielectric film is formed on the ceramic multilayer substrate, or a multilayer printed circuit board such as a glass epoxy multilayer substrate.

【0027】図2は本発明の実施の形態の第2の例の高
周波半導体装置を示す図であって、断面図を示してい
る。同図において各数字符号は図1の場合と同じであ
る。実装基板1は半導体基板3とその上に形成される多
層の誘電体膜と実装基板1の裏面に形成される接地導体
9より構成されている。半導体基板3(実装基板)上
に、制御回路12やIF回路13等が半導体プロセスに
より形成される。
FIG. 2 is a diagram showing a high-frequency semiconductor device according to a second example of the embodiment of the present invention and is a sectional view. In the figure, reference numerals are the same as those in FIG. The mounting substrate 1 is composed of a semiconductor substrate 3, a multilayer dielectric film formed thereon, and a ground conductor 9 formed on the back surface of the mounting substrate 1. The control circuit 12, the IF circuit 13 and the like are formed on the semiconductor substrate 3 (mounting substrate) by a semiconductor process.

【0028】上記半導体基板3(実装基板)と制御回路
12やIF回路13上に誘電体膜がスピンコーティング
等により多層に形成され、上記誘電体膜上に複数の伝送
線路や接地導体が形成される。
Dielectric films are formed in multiple layers on the semiconductor substrate 3 (mounting substrate) and the control circuit 12 and the IF circuit 13 by spin coating or the like, and a plurality of transmission lines and ground conductors are formed on the dielectric film. It

【0029】さらに実装基板1の誘電体膜最上層上には
高周波回路チップとの接続用のパッドが形成され、上記
パッド上に形成したバンプ4を介して、多層化高周波回
路チップをフェイスダウン構造で接続する。多層化高周
波回路チップは半導体基板3(高周波回路チップ)上
に、多層化された誘電体膜を形成し、その最上層上に接
地導体を形成し、かつ複数の誘電体膜上に接地導体を形
成している。
Further, a pad for connection with a high frequency circuit chip is formed on the uppermost layer of the dielectric film of the mounting substrate 1, and the multilayer high frequency circuit chip is face-down structure via the bump 4 formed on the pad. Connect with. The multilayered high frequency circuit chip has a multilayered dielectric film formed on a semiconductor substrate 3 (high frequency circuit chip), a ground conductor formed on the uppermost layer thereof, and a ground conductor formed on a plurality of dielectric films. Is forming.

【0030】以上のように構成された高周波半導体装置
は、実装した高周波回路チップの直下の実装基板上にも
回路を形成することができるために、高周波半導体装置
の小形・高集積化が実現できる。実装基板最上層に接地
導体が形成されているために、高周波回路チップと実装
基板上に形成される回路間の理想的なアイソレーション
を実現できる。従って、実装後も高周波特性の劣化を防
ぎ、良好な特性を持つ高周波半導体装置を実現できる。
In the high frequency semiconductor device configured as described above, a circuit can be formed on the mounting substrate immediately below the mounted high frequency circuit chip, and therefore, the high frequency semiconductor device can be made compact and highly integrated. . Since the ground conductor is formed in the uppermost layer of the mounting board, ideal isolation between the high frequency circuit chip and the circuit formed on the mounting board can be realized. Therefore, it is possible to prevent deterioration of the high-frequency characteristics even after mounting and realize a high-frequency semiconductor device having good characteristics.

【0031】また、高周波回路チップおよび実装基板の
複数の誘電体膜上に接地導体を形成しているので、いず
れの層から接地する場合でも、最短の距離で接地するこ
とができ、スルーホールが、不要なインダクタンスとな
ることが無く、ミリ波領域まで良好な高周波特性を維持
できる。
Further, since the ground conductors are formed on the plurality of dielectric films of the high frequency circuit chip and the mounting substrate, the ground can be grounded from any layer in the shortest distance, and the through holes are formed. In addition, it is possible to maintain good high frequency characteristics up to the millimeter wave region without causing unnecessary inductance.

【0032】なお、実装基板に使われる半導体基板3は
例えば、アルミナ等のセラミック多層基板や上記セラミ
ック多層基板上に多層の誘電体膜を形成した多層実装基
板やガラスエポキシ系の多層基板等の多層プリント基板
であってもよい。
The semiconductor substrate 3 used as the mounting substrate is, for example, a ceramic multilayer substrate such as alumina, a multilayer mounting substrate in which a multilayer dielectric film is formed on the ceramic multilayer substrate, or a glass epoxy type multilayer substrate. It may be a printed circuit board.

【0033】図3は本発明の実施の形態の第3の例の高
周波半導体装置を示す図であって、断面図を示してい
る。同図において各数字符号は図1の場合と同様であ
る。実装基板1は半導体基板3とその上に形成される多
層の誘電体膜と実装基板1の裏面に形成される接地導体
9より構成されている。半導体基板3(実装基板)上
に、制御回路12やIF回路13等が半導体プロセスに
より形成される。
FIG. 3 is a view showing a high frequency semiconductor device of a third example of the embodiment of the present invention, and is a sectional view. In the figure, reference numerals are the same as those in FIG. The mounting substrate 1 is composed of a semiconductor substrate 3, a multilayer dielectric film formed thereon, and a ground conductor 9 formed on the back surface of the mounting substrate 1. The control circuit 12, the IF circuit 13 and the like are formed on the semiconductor substrate 3 (mounting substrate) by a semiconductor process.

【0034】上記半導体基板3(実装基板)と制御回路
12やIF回路13上に誘電体膜がスピンコーティング
等により多層に形成され、上記誘電体膜上に複数の伝送
線路や接地導体が形成される。
Dielectric films are formed in multiple layers on the semiconductor substrate 3 (mounting substrate) and the control circuit 12 and the IF circuit 13 by spin coating, and a plurality of transmission lines and ground conductors are formed on the dielectric film. It

【0035】さらに実装基板1の誘電体膜最上層上には
高周波回路チップとの接続用のパッドが形成され、上記
パッド上に形成したバンプ4を介して、複数の多層化高
周波回路チップ2をフェイスダウン構造で接続する。多
層化高周波回路チップ2は半導体基板3(高周波回路チ
ップ)上に、多層化された誘電体膜を形成し、その最上
層上に接地導体を形成し、かつ複数の誘電体膜上に接地
導体を形成している。
Further, a pad for connection to a high frequency circuit chip is formed on the uppermost layer of the dielectric film of the mounting substrate 1, and a plurality of multi-layered high frequency circuit chips 2 are connected through the bumps 4 formed on the pad. Connect with face-down structure. The multilayered high-frequency circuit chip 2 has a multilayered dielectric film formed on a semiconductor substrate 3 (high-frequency circuit chip), a ground conductor formed on the uppermost layer thereof, and a ground conductor formed on a plurality of dielectric films. Is formed.

【0036】以上のように構成された高周波半導体装置
は、実装した高周波回路チップの直下の実装基板上にも
回路を形成することができるために、高周波半導体装置
の小形・高集積化が実現できる。実装基板最上層に接地
導体が形成されているために、高周波回路チップと実装
基板上に形成される回路間の理想的なアイソレーション
を実現できる。従って、実装後も高周波特性の劣化を防
ぎ、良好な特性を持つ高周波半導体装置を実現できる。
In the high-frequency semiconductor device configured as described above, a circuit can be formed on the mounting substrate directly below the mounted high-frequency circuit chip, so that the high-frequency semiconductor device can be made compact and highly integrated. . Since the ground conductor is formed in the uppermost layer of the mounting board, ideal isolation between the high frequency circuit chip and the circuit formed on the mounting board can be realized. Therefore, it is possible to prevent deterioration of the high-frequency characteristics even after mounting and realize a high-frequency semiconductor device having good characteristics.

【0037】また、実装基板の複数の誘電体膜上に接地
導体を形成しているので、いずれの層から接地する場合
でも、最短の距離で接地することができ、スルーホール
が、不要なインダクタンスとなることが無く、ミリ波領
域まで良好な高周波特性を維持できる。
Further, since the grounding conductor is formed on the plurality of dielectric films of the mounting board, the grounding can be performed in the shortest distance regardless of which layer is grounded, and the through hole eliminates unnecessary inductance. It is possible to maintain good high frequency characteristics even in the millimeter wave region.

【0038】なお、実装基板に使われる半導体基板3は
例えば、アルミナ等のセラミック多層基板や上記セラミ
ック多層基板上に多層の誘電体膜を形成した多層実装基
板やガラスエポキシ系の多層基板等の多層プリント基板
であってもよい。
The semiconductor substrate 3 used as a mounting substrate is, for example, a ceramic multilayer substrate such as alumina, a multilayer mounting substrate in which a multilayer dielectric film is formed on the ceramic multilayer substrate, or a glass epoxy type multilayer substrate. It may be a printed circuit board.

【0039】[0039]

【発明の効果】以上説明したように、本発明の高周波半
導体装置では、高周波回路チップを実装する直下の位置
にも制御回路を形成できるので小形・高集積化を実現で
きる。さらに、複数の層に接地導体を設けた構成では、
多層化高周波回路チップと実装基板または高周波回路と
制御回路のアイソレーションを確保しているので、実装
後も良好な高周波特性を得ることができる。
As described above, in the high-frequency semiconductor device of the present invention, the control circuit can be formed immediately below the high-frequency circuit chip, so that the device can be made compact and highly integrated. Furthermore, in the configuration in which the ground conductor is provided in a plurality of layers,
Since the isolation of the multilayered high frequency circuit chip and the mounting substrate or the high frequency circuit and the control circuit is ensured, good high frequency characteristics can be obtained even after mounting.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態の第1の例を示す図であ
る。
FIG. 1 is a diagram showing a first example of an embodiment of the present invention.

【図2】本発明の実施の形態の第2の例を示す図であ
る。
FIG. 2 is a diagram showing a second example of the embodiment of the present invention.

【図3】本発明の実施の形態の第3の例を示す図であ
る。
FIG. 3 is a diagram showing a third example of an exemplary embodiment of the present invention.

【図4】従来の高周波半導体装置の例を示す図である。FIG. 4 is a diagram showing an example of a conventional high frequency semiconductor device.

【符号の説明】[Explanation of symbols]

1 実装基板 2 高周波回路チップ 3 半導体基板 4 バンプ 5 FET 6 容量 7 誘電体膜 8 伝送線路 9 接地導体 10 信号線用バンプパッド 11 スルーホーン 12 制御回路 13 IF回路 1 Mounting Substrate 2 High Frequency Circuit Chip 3 Semiconductor Substrate 4 Bump 5 FET 6 Capacitance 7 Dielectric Film 8 Transmission Line 9 Grounding Conductor 10 Signal Line Bump Pad 11 Through Horn 12 Control Circuit 13 IF Circuit

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に誘電体膜と配線層とを多
層に形成して成る実装基板上に、 半導体基板上に誘電体膜と配線層とを多層に形成して成
り、その一方の面に接地導体を有する多層化高周波回路
チップを、 接地導体面が、実装基板の一方の面の誘電体膜と向き合
うように、バンプを用いてフリップチップ実装したこと
を特徴とする高周波半導体装置。
1. A dielectric substrate and a wiring layer are formed in multiple layers on a semiconductor substrate, and a dielectric film and an interconnection layer are formed in multiple layers on the semiconductor substrate. A high-frequency semiconductor device characterized in that a multilayer high-frequency circuit chip having a ground conductor on its surface is flip-chip mounted using bumps so that the ground conductor surface faces the dielectric film on one surface of the mounting substrate.
【請求項2】 誘電体基板上に誘電体層と配線層とを多
層に形成して成る実装基板上に、 半導体基板上に誘電体膜と配線層とを多層に形成して成
り、その一方の面に接地導体を有する多層化高周波回路
チップを、 接地導体面が、実装基板の一方の面の誘電体膜と向き合
うように、バンプを用いてフリップチップ実装したこと
を特徴とする高周波半導体装置。
2. A dielectric substrate and wiring layers are formed in multiple layers on a dielectric substrate, and a dielectric film and wiring layers are formed in multiple layers on a semiconductor substrate. A high-frequency semiconductor device characterized in that a multilayer high-frequency circuit chip having a ground conductor on its surface is flip-chip mounted using bumps so that the ground conductor surface faces the dielectric film on one surface of the mounting substrate. .
【請求項3】 実装基板上に、IF回路、A/D変換回
路、D/A変換回路、ディジタル回路および制御回路等
を形成した請求項1または請求項2記載の高周波半導体
装置。
3. The high frequency semiconductor device according to claim 1, wherein an IF circuit, an A / D conversion circuit, a D / A conversion circuit, a digital circuit, a control circuit and the like are formed on the mounting substrate.
【請求項4】 半導体基板上に誘電体膜と配線層とを多
層に形成して成り、その一方の面の少なくとも一部に接
地導体を有する実装基板上に、 半導体基板上に誘電体膜と配線層とを多層に形成して成
り、その一方の面に接地導体を有する多層化高周波回路
チップを、 多層化高周波回路チップの記接地導体面が、実装基板の
接地導体面と向き合うように、バンプを用いてフリップ
チップ実装したことを特徴とする高周波半導体装置。
4. A dielectric substrate and a wiring layer are formed in multiple layers on a semiconductor substrate, a mounting substrate having a ground conductor on at least a part of one surface thereof, and a dielectric film on the semiconductor substrate. A multi-layered high-frequency circuit chip having a wiring conductor formed in multiple layers and having a ground conductor on one surface thereof, so that the ground conductor surface of the multi-layered high-frequency circuit chip faces the ground conductor surface of the mounting board. A high-frequency semiconductor device characterized by being flip-chip mounted using bumps.
【請求項5】 誘電体基板上に誘電体膜と配線層とを多
層に形成して成り、その一方の面の少なくとも一部に接
地導体を有する実装基板上に、 半導体基板上に誘電体膜と配線層とを多層に形成して成
り、その一方の面に接地導体を有する多層化高周波回路
チップを、 多層化高周波回路チップの接地導体面が、実装基板の接
地導体面と向き合うように、 バンプを用いてフリップチップ実装したことを特徴とす
る高周波半導体装置。
5. A dielectric film and a wiring layer are formed in multiple layers on a dielectric substrate, and a dielectric film on a semiconductor substrate on a mounting substrate having a ground conductor on at least a part of one surface thereof. A multi-layered high-frequency circuit chip having a ground conductor on one surface thereof, and the ground conductor surface of the multi-layered high-frequency circuit chip faces the ground conductor surface of the mounting board. A high-frequency semiconductor device characterized by being flip-chip mounted using bumps.
【請求項6】 実装基板上に、IF回路、A/D変換回
路、D/A変換回路、ディジタル回路および制御回路等
を形成した請求項4または請求項5記載の高周波半導体
装置。
6. The high frequency semiconductor device according to claim 4, wherein an IF circuit, an A / D conversion circuit, a D / A conversion circuit, a digital circuit, a control circuit and the like are formed on the mounting substrate.
【請求項7】 実装基板と、これに実装された多層化高
周波回路チップの内少なくとも一方が、多層化された複
数の誘電体膜の内の複数の誘電体膜面に接地導体を有す
る請求項1〜請求項6のいずれか1項に記載の高周波半
導体装置。
7. The mounting substrate and at least one of the multilayered high frequency circuit chip mounted thereon has a ground conductor on a plurality of dielectric film surfaces of a plurality of multilayered dielectric films. The high frequency semiconductor device according to claim 1.
JP8908096A 1996-04-11 1996-04-11 High frequency semiconductor device Expired - Lifetime JP3081786B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8908096A JP3081786B2 (en) 1996-04-11 1996-04-11 High frequency semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8908096A JP3081786B2 (en) 1996-04-11 1996-04-11 High frequency semiconductor device

Publications (2)

Publication Number Publication Date
JPH09283693A true JPH09283693A (en) 1997-10-31
JP3081786B2 JP3081786B2 (en) 2000-08-28

Family

ID=13960891

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3081786B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906411B1 (en) 2000-06-29 2005-06-14 Mitsubishi Denki Kabushiki Kaisha Multilayer substrate module and portable wireless terminal
US7425747B2 (en) 2003-08-05 2008-09-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device

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US8112155B2 (en) 2004-02-05 2012-02-07 Motorika Limited Neuromuscular stimulation
WO2005074373A2 (en) 2004-02-05 2005-08-18 Motorika Inc. Methods and apparatus for rehabilitation and training
KR20070061475A (en) 2004-02-05 2007-06-13 모토리카 리미티드 Gait rehabilitation methods and apparatuses
DE602005014215D1 (en) 2004-02-05 2009-06-10 Motorika Ltd NEUROMUSCULAR STIMULATION
CA2584612A1 (en) 2004-08-25 2006-03-02 Motorika Limited Motor training with brain plasticity

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906411B1 (en) 2000-06-29 2005-06-14 Mitsubishi Denki Kabushiki Kaisha Multilayer substrate module and portable wireless terminal
US7425747B2 (en) 2003-08-05 2008-09-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device

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