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JPH09283663A - Manufacture of electronic device and electronic device - Google Patents

Manufacture of electronic device and electronic device

Info

Publication number
JPH09283663A
JPH09283663A JP8110539A JP11053996A JPH09283663A JP H09283663 A JPH09283663 A JP H09283663A JP 8110539 A JP8110539 A JP 8110539A JP 11053996 A JP11053996 A JP 11053996A JP H09283663 A JPH09283663 A JP H09283663A
Authority
JP
Japan
Prior art keywords
hole
glass substrate
electronic device
semiconductor chip
electric wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8110539A
Other languages
Japanese (ja)
Inventor
Tatsuhisa Kawabata
達央 川畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Corp
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Corp, Omron Tateisi Electronics Co filed Critical Omron Corp
Priority to JP8110539A priority Critical patent/JPH09283663A/en
Publication of JPH09283663A publication Critical patent/JPH09283663A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01PMEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P2015/0805Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration
    • G01P2015/0822Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass
    • G01P2015/0825Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass for one single degree of freedom of movement of the mass
    • G01P2015/0828Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass for one single degree of freedom of movement of the mass the mass being of the paddle type being suspended at one of its longitudinal ends

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Pressure Sensors (AREA)

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability and the yield of the product of an electronic device by a method wherein the manufacturing procedure of the device is improved in the electronic device of a structure wherein an electric wiring is formed through a through hole formed in a glass substrate laminated to a device main body. SOLUTION: A glass substrate 3 is laminated to a device main body 1 and thereafter, a through hole 4 is formed in a prescribed position on the substrate 3 to make the main body 1 expose through the depth of the hole 4 and an electrical wiring 5, which is electrically connected with the exposed part of the main body 1 by performing a deposition or the like, is formed through the hole 4. As a polishing of the side of the surface, which is bonded to the main body 1, of the substrate 3 is performed after the formation of the hole 4, it is eliminated that a break or the like is generated in an electronic device, the electric wiring is never cut and a hermetic sealing of the device never becomes incomplete.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、デバイス本体にガ
ラス基板を貼り合わせる構造をもった電子デバイスの製
造方法に関し、とくに、ガラス基板の貫通穴を通してデ
バイス本体に達する電気配線を形成する技術に関する。
この技術は、超小型の加速度センサや圧力センサ、マイ
クロリレー、集積回路などの電子デバイスに応用され
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic device having a structure in which a glass substrate is attached to a device body, and more particularly to a technique for forming electrical wiring reaching the device body through a through hole in the glass substrate.
This technology is applied to electronic devices such as microminiature acceleration sensors, pressure sensors, micro relays, and integrated circuits.

【0002】[0002]

【従来の技術】図1に示すような構造の超小型の加速度
センサが知られている。これは、デバイス本体である半
導体チップ1を第1のガラス基板2と第2のガラス基板
3とで挟み込んだサンドイッチ構造になっている。半導
体チップ1は、IC製造の微細加工技術により加速度セ
ンサの構造体を形成したもので、自由空間1a内に片持
ち梁1bを配設している。そして、加速度を受けて片持
ち梁1bが撓み変位し、その変位に応じた電気信号が生
成される。
2. Description of the Related Art A microminiature acceleration sensor having a structure as shown in FIG. 1 is known. This has a sandwich structure in which a semiconductor chip 1 which is a device body is sandwiched between a first glass substrate 2 and a second glass substrate 3. The semiconductor chip 1 has a structure of an acceleration sensor formed by a microfabrication technique for manufacturing an IC, and a cantilever 1b is arranged in a free space 1a. Then, the cantilever 1b is flexibly displaced in response to the acceleration, and an electric signal corresponding to the displacement is generated.

【0003】半導体チップ1は、第1のガラス基板2の
上に陽極接合により貼り合わされる。そして、半導体チ
ップ1の上に第2のガラス基板3が陽極接合により貼り
合わされる。これにより、3枚の板が一体化されるとと
もに、両ガラス基板2,3により片持ち梁1bの周辺の
自由空間1aが密閉される。
The semiconductor chip 1 is bonded onto the first glass substrate 2 by anodic bonding. Then, the second glass substrate 3 is bonded onto the semiconductor chip 1 by anodic bonding. As a result, the three plates are integrated, and the glass substrates 2 and 3 seal the free space 1a around the cantilever 1b.

【0004】また、第2のガラス基板3の所定位置には
貫通穴4が形成され、その貫通穴4は半導体チップ1の
表面にまで達している。その半導体チップ1の表面に電
気的に接続する電気配線5を貫通穴4を通して形成して
いる。この例の電気配線5は、ガラス基板3の上面と貫
通穴4の内周面と貫通穴4の奥に露出した半導体チップ
1の表面に、蒸着やスパッタリングにより導電体膜をパ
ターン形成したものである。
A through hole 4 is formed at a predetermined position on the second glass substrate 3, and the through hole 4 reaches the surface of the semiconductor chip 1. An electric wiring 5 electrically connected to the surface of the semiconductor chip 1 is formed through the through hole 4. The electrical wiring 5 of this example is formed by patterning a conductor film on the upper surface of the glass substrate 3, the inner peripheral surface of the through hole 4 and the surface of the semiconductor chip 1 exposed at the back of the through hole 4 by vapor deposition or sputtering. is there.

【0005】従来、この加速度センサは次の手順で製造
されていた。半導体チップ1と、第1のガラス基板2
と、第2のガラス基板3とをそれぞれ製作し、第1のガ
ラス基板2の上に半導体チップ1を貼り合わせ、半導体
チップ1の上に第2のガラス基板3を貼り合わせる。こ
こで重要なことは、第2のガラス基板3にはあらかじめ
貫通穴4を形成しておき、その穴加工済みの第2のガラ
ス基板3を半導体チップ1に貼り合わせている点であ
る。この後で、貫通穴4を通しての電気配線5を形成す
る。
Conventionally, this acceleration sensor has been manufactured by the following procedure. Semiconductor chip 1 and first glass substrate 2
And the second glass substrate 3 are respectively manufactured, the semiconductor chip 1 is bonded onto the first glass substrate 2, and the second glass substrate 3 is bonded onto the semiconductor chip 1. What is important here is that the through holes 4 are formed in the second glass substrate 3 in advance, and the second glass substrate 3 having the holes processed is bonded to the semiconductor chip 1. After this, the electric wiring 5 through the through hole 4 is formed.

【0006】[0006]

【発明が解決しようとする課題】従来は、貫通穴4を形
成した第2のガラス基板3を半導体チップ1(デバイス
本体)に貼り合わせる、という製造手順を採っているた
めに、次のような問題があった。
Conventionally, since the second glass substrate 3 having the through hole 4 formed therein is attached to the semiconductor chip 1 (device body), the manufacturing procedure is as follows. There was a problem.

【0007】穴付きの第2のガラス基板3は次のような
手順で加工される。目標板厚より厚いガラス基板に穴あ
け加工を行って貫通穴を形成し、その後に研磨加工を行
ってガラス基板を薄くして、目標板厚にする。これは、
穴あけ加工時の割れによる不良品の発生を減少させるな
ど、歩留り向上のために必要なことであった。
The second glass substrate 3 with holes is processed by the following procedure. A glass substrate thicker than the target plate thickness is perforated to form a through hole, and then a polishing process is performed to thin the glass substrate to a target plate thickness. this is,
This was necessary to improve the yield, such as reducing the occurrence of defective products due to cracking during drilling.

【0008】さらには、貫通穴を形成する際には、図示
省略の取付台に接着剤などを用いてガラス基板を固定し
た状態で行うので、貫通穴を形成後にその取付台からガ
ラス基板を取り外すと、ガラス基板側にも上記接着剤が
付着する。そこで、係る接着剤を除去するためにも上記
研磨を行う。
Further, since the glass substrate is fixed to the mounting base (not shown) with an adhesive or the like when forming the through hole, the glass substrate is removed from the mounting base after the through hole is formed. Then, the adhesive adheres also to the glass substrate side. Therefore, the polishing is also performed in order to remove the adhesive.

【0009】さらにまた、最終的にセンサとして使用す
る際のガラス基板の厚さは非常に薄いので、その厚さに
加工した状態で貫通孔を形成すると割れてしまうため、
必要な強度を得るために最終製品の目標板厚よりも厚い
ガラス基板に対して穴あけ加工を行うのである。
Furthermore, since the thickness of the glass substrate when it is finally used as a sensor is very thin, if the through hole is formed in the state of being processed to that thickness, it will be broken.
In order to obtain the required strength, drilling is performed on a glass substrate that is thicker than the target thickness of the final product.

【0010】ところが、前記の手順で加工される穴付き
第2のガラス基板3でも、図2に示すように、貫通穴4
のエッジ部が欠けたり(図中の符号k)、局所的に大き
く削れる面ダレ(図中の符号m)と呼ばれる現象を生じ
やすい。
However, even in the second glass substrate 3 with a hole which is processed by the above procedure, as shown in FIG.
Is likely to be chipped (reference numeral k in the figure) or locally dripped to cause a phenomenon called surface sag (reference numeral m in the figure).

【0011】すなわち、上記研磨の際に研磨粒子などが
当たり欠けkが生じることがある。さらに、そのまま研
磨を続けると、欠けたガラスが研磨粒子に混ざって貫通
穴の周囲に当たり、面ダレmを生じる原因になる。
That is, during the above-mentioned polishing, abrasive particles or the like may hit and a chipping k may occur. Further, if the polishing is continued as it is, the chipped glass is mixed with the polishing particles and hits the periphery of the through hole, which causes a surface sag m.

【0012】このような欠けkや面ダレmのある第2の
ガラス基板3を用いて、図1に示す構造の加速度センサ
を組み立てて電気配線5を形成した場合、図3に示すよ
うな欠陥品を生じやすい。すなわち、欠陥の1つは、電
気配線5の導電体膜が貫通穴4のエッジ部分で半導体チ
ップ1の表面とつながらず、配線不良(断線)となるこ
とである。また、もう1つの欠陥は、面ダレmのために
第2のガラス基板3と半導体チップ1との接合界面に隙
間を生じ、その隙間を通じてが半導体チップ1の前記自
由空間1aが外部につながり、自由空間1aの気密性が
損われることである。
When the acceleration sensor having the structure shown in FIG. 1 is assembled to form the electric wiring 5 by using the second glass substrate 3 having the above-mentioned chipping k and surface sag m, the defect as shown in FIG. Easy to produce goods. That is, one of the defects is that the conductor film of the electric wiring 5 does not connect to the surface of the semiconductor chip 1 at the edge portion of the through hole 4, resulting in wiring failure (disconnection). Another defect is that due to the surface sag m, a gap is created at the bonding interface between the second glass substrate 3 and the semiconductor chip 1, and the free space 1a of the semiconductor chip 1 is connected to the outside through the gap. The airtightness of the free space 1a is impaired.

【0013】本発明は、上記した背景に鑑みてなされた
もので、その目的とするところは、上記した問題を解決
し、デバイス本体に貼り合わせたガラス基板の貫通穴を
通して電気配線を形成する構造の電子デバイスにおい
て、その製造手順を改良することにより、製品の信頼性
および歩留りを向上することのできる電子デバイスの製
造方法及び電子デバイスを提供することにある。
The present invention has been made in view of the above background, and an object thereof is to solve the above problems and form an electric wiring through a through hole of a glass substrate bonded to a device body. To provide an electronic device manufacturing method and an electronic device capable of improving the reliability and yield of products by improving the manufacturing procedure.

【0014】[0014]

【課題を解決するための手段】上記した目的を達成する
ために、本発明に係る電子デバイスの製造方法では、デ
バイス本体にガラス基板を貼り合わせてから、そのガラ
ス基板の所定位置に貫通穴を形成して、その貫通穴の奥
に前記デバイス本体を露出させ、その露出部分に電気的
に接続する電気配線を、前記貫通穴を通して形成する製
造手順とした(請求項1)。
In order to achieve the above object, in the method of manufacturing an electronic device according to the present invention, a glass substrate is attached to a device body, and then a through hole is formed at a predetermined position of the glass substrate. The device body is formed so as to be exposed in the depth of the through hole, and an electric wiring electrically connected to the exposed portion is formed through the through hole (claim 1).

【0015】この製造方法において、望ましくは、前記
ガラス基板を貼り合わせる前に、前記デバイス本体の前
記露出部分となる位置に適宜なコンタクトを形成してお
くか(請求項2)、あるいは、前記貫通穴を形成した後
で、かつ前記電気配線を形成する前に、前記貫通穴の奥
の前記露出部分に適宜なコンタクトを形成する(請求項
3)ことである。
In this manufacturing method, preferably, an appropriate contact is formed at a position to be the exposed portion of the device body before bonding the glass substrate (claim 2) or the through-hole. After forming a hole and before forming the electric wiring, an appropriate contact is formed in the exposed portion at the back of the through hole (claim 3).

【0016】ここで電子デバイスとしては、実施の形態
で示したようにセンサに利用する場合には、半導体基板
(シリコン基板)がある。そして、コンタクトの手法と
しては、上記したように電子デバイスが半導体の場合に
は、不純物層を形成し、低抵抗層としたものがある。
Here, as the electronic device, there is a semiconductor substrate (silicon substrate) when it is used for a sensor as shown in the embodiments. As a contact method, when the electronic device is a semiconductor as described above, there is a method of forming an impurity layer to form a low resistance layer.

【0017】本発明では、ガラス基板をデバイス本体に
張り付けた後で、穴あけ加工を行い貫通穴を形成しデバ
イス本体の表面を露出させるようにした。その結果、貫
通穴を形成した後に、ガラス基板の接合面側を研磨する
ことがなく、欠けや面ダレを生じない。
In the present invention, after the glass substrate is attached to the device body, a hole is formed to form a through hole to expose the surface of the device body. As a result, the bonded surface side of the glass substrate is not polished after the through hole is formed, and no chipping or surface sagging occurs.

【0018】そして、実際の電気配線処理としては、例
えば前記貫通穴を含むガラス基板の表面所定部位に導電
体膜を成膜し、導電体膜を介して前記デバイス本体の露
出部分と、前記ガラス基板の表面とを電気的に導通させ
るようにすることである(請求項4)。
As an actual electric wiring process, for example, a conductor film is formed on a predetermined portion of the surface of the glass substrate including the through hole, and the exposed portion of the device main body and the glass via the conductor film. It is to electrically connect with the surface of the substrate (claim 4).

【0019】そして、このガラス基板表面に形成した導
電体膜に対して各種のボンディングにより外部回路と接
続・配線することにより、その導電体膜を介して電子デ
バイスの本体の露出部分と外部回路とが導通可能とな
る。
Then, the conductor film formed on the surface of the glass substrate is connected and wired to an external circuit by various kinds of bonding, whereby the exposed portion of the main body of the electronic device and the external circuit are connected through the conductor film. Can be conducted.

【0020】[0020]

【発明の実施の形態】「従来の技術」の項で詳しく説明
した図1の構造の超小型加速度センサに関し、その製造
プロセスに本発明を適用したいくつかの実施の形態につ
いて説明する。なお、本発明の実施の形態を示す図4以
降の図面において、図1と共通する部分には同じ符号を
付けており、すでに詳しく説明した事柄については再説
明しなbい。
BEST MODE FOR CARRYING OUT THE INVENTION Several embodiments in which the present invention is applied to the manufacturing process of the microminiature acceleration sensor having the structure of FIG. 1 described in detail in the section "Prior Art" will be described. 4 and subsequent figures showing the embodiment of the present invention, parts common to those in FIG. 1 are denoted by the same reference numerals, and the matters already described in detail will not be explained again.

【0021】本発明の第1実施の形態を図4,図5に示
している。図4(A)の段階では、第1のガラス基板2
の上に半導体チップ1を貼り合わせ、半導体チップ1の
上に第2のガラス基板3を貼り合わせる。ここで注目す
べきことは、第2のガラス基板3には貫通穴がまだ形成
されていないことである。
A first embodiment of the present invention is shown in FIGS. At the stage of FIG. 4A, the first glass substrate 2
The semiconductor chip 1 is bonded onto the semiconductor chip 1, and the second glass substrate 3 is bonded onto the semiconductor chip 1. What should be noted here is that the through hole is not yet formed in the second glass substrate 3.

【0022】次の図4(B)の工程において、第2のガ
ラス基板3の所定位置に貫通穴4を形成する。この穴あ
けは、超音波加工あるいはブラスト加工により行う。穴
あけ加工時に、貫通穴4が半導体チップ1の側に食い込
んでもかまわない。換言すると、確実に半導体チップ1
の表面を露出させるためには、半導体チップ1側に若干
量貫通穴4を食い込ませるのがよい。
In the next step of FIG. 4B, the through hole 4 is formed at a predetermined position of the second glass substrate 3. This drilling is performed by ultrasonic processing or blast processing. The through-hole 4 may bite into the semiconductor chip 1 side during the drilling process. In other words, surely the semiconductor chip 1
In order to expose the surface of the above, it is preferable that the through hole 4 is slightly bited into the semiconductor chip 1 side.

【0023】その後、図5に示すように、貫通穴4の奥
に露出した半導体チップ1の表面部分に電気的に接続す
る電気配線5を、貫通穴4を通して形成する。この例の
電気配線5は、ガラス基板3の上面と貫通穴4の内周面
と貫通穴4の奥に露出した半導体チップ1の表面に、蒸
着やスパッタリングにより導電体膜をパターン形成した
ものである。
After that, as shown in FIG. 5, the electrical wiring 5 electrically connected to the surface portion of the semiconductor chip 1 exposed at the back of the through hole 4 is formed through the through hole 4. The electrical wiring 5 of this example is formed by patterning a conductor film on the upper surface of the glass substrate 3, the inner peripheral surface of the through hole 4 and the surface of the semiconductor chip 1 exposed at the back of the through hole 4 by vapor deposition or sputtering. is there.

【0024】なお、第2のガラス基板3は、半導体チッ
プ1や第1のガラス基板2と接合一体化されているため
十分な強度が保たれるとともに、従来のように接合面側
の研磨が不要であるので、第2のガラス基板3の厚さ
は、最終製品の目標厚さと同じにしてもよくなる。係る
場合には、従来の研磨工程が不要となり、工程数の削減
も図れる。
Since the second glass substrate 3 is bonded and integrated with the semiconductor chip 1 and the first glass substrate 2, sufficient strength is maintained and the bonding surface side is polished as in the conventional case. Since it is unnecessary, the thickness of the second glass substrate 3 may be the same as the target thickness of the final product. In such a case, the conventional polishing process becomes unnecessary and the number of processes can be reduced.

【0025】また、第2のガラス基板3の厚さを目標厚
さよりも厚くしてももちろんよい。その場合には、貫通
穴4を形成後に上面表面を研磨することになる。この場
合に、貫通穴4の上端周縁のガラス基板に研磨粒子が当
たることがあり、やはり欠けひいては面ダレを生じるお
それがある。しかし、仮に欠け等を生じたとしても、従
来の問題点であった気密性の問題は発生しない。さらに
上面で欠けを生じたとすると、さらにそのなす角βが鈍
角となり、緩やかなテーパ面となるので、その後に形成
する電気配線5の断線のおそれもない。
The thickness of the second glass substrate 3 may of course be thicker than the target thickness. In that case, the upper surface is polished after the through hole 4 is formed. In this case, the abrasive particles may hit the glass substrate around the upper edge of the through hole 4, and there is a risk that the glass particles may still be chipped and the surface may be sagged. However, even if a chip or the like occurs, the problem of airtightness, which is a conventional problem, does not occur. If a chip is further formed on the upper surface, the angle β formed by the chip becomes an obtuse angle and becomes a gentle tapered surface, so that there is no fear of disconnection of the electrical wiring 5 formed thereafter.

【0026】本発明の第2の実施の形態を図6〜図8に
示している。上記した第1の実施の形態と異なるのは、
図6に示すように半導体チップ1の上に第2のガラス基
板3を貼り合わせる前に、半導体チップ1の前記露出部
分となる位置に適宜なコンタクト6を形成する点であ
る。コンタクト6は、本実施の形態ではイオン注入ある
いは不純物拡散により形成した不純物層としている。こ
のコンタクトにより、ロス分を可及的に抑制した状態
で、信号の取り出しが可能となる。
A second embodiment of the present invention is shown in FIGS. The difference from the above-described first embodiment is that
As shown in FIG. 6, before the second glass substrate 3 is bonded onto the semiconductor chip 1, a proper contact 6 is formed at a position which will be the exposed portion of the semiconductor chip 1. In this embodiment, the contact 6 is an impurity layer formed by ion implantation or impurity diffusion. With this contact, the signal can be taken out with the loss amount suppressed as much as possible.

【0027】その後、第1の実施の形態と同様に、第2
のガラス基板3の所定位置に貫通穴4を形成する(図
7)。この時、図7(B)に拡大して示したように、貫
通穴4の掘削深さは、半導体チップ1側に食い込んでも
よいが、その貫通穴4の底面4aは、コンタクト6の底
面6aよりも上方に位置させるようにするのは当然のこ
とである。
After that, as in the first embodiment, the second
Through holes 4 are formed at predetermined positions of the glass substrate 3 (see FIG. 7). At this time, as shown in an enlarged view in FIG. 7B, the excavation depth of the through hole 4 may cut into the semiconductor chip 1 side, but the bottom surface 4 a of the through hole 4 is the bottom surface 6 a of the contact 6. Naturally, it should be positioned above.

【0028】そして、第1の実施の形態における図5の
処理と同様に、貫通穴4を形成してコンタクト6を含む
露出部分に対して蒸着,スパッタ等により電気配線5を
施す(図8参照)。
Then, similarly to the processing of FIG. 5 in the first embodiment, the through hole 4 is formed and the exposed portion including the contact 6 is provided with the electric wiring 5 by vapor deposition, sputtering or the like (see FIG. 8). ).

【0029】また、本実施の形態では、露出部分の全面
にコンタクト6が位置するように形成したが、少なくと
も一部にコンタクト6が存在するようにしてもよいのは
もちろんである。
Further, in the present embodiment, the contact 6 is formed so as to be located on the entire surface of the exposed portion, but it goes without saying that the contact 6 may be present on at least a part thereof.

【0030】本発明の第3の実施の形態を図9,図10
に示している。本実施の形態では、図9に示すように、
貫通穴を形成するまでは第1の実施の形態と同様の工程
を行う。
The third embodiment of the present invention is shown in FIGS.
Is shown in In the present embodiment, as shown in FIG.
The same steps as those in the first embodiment are performed until the through holes are formed.

【0031】ここで本実施の形態では、第1実施の形態
と相違して、半導体チップ1に貼り合わせた第2のガラ
ス基板3に貫通穴4を形成した後で、かつ電気配線5を
形成する前の図10(A)の段階で、貫通穴4の奥の半
導体チップ1の前記露出部分にイオン注入や不純物拡散
により適宜なコンタクト7を形成する点である。そし
て、そのコンタクト7を形成後に、蒸着,スパッタなど
して電気配線5を成膜する。
In this embodiment, unlike the first embodiment, the electrical wiring 5 is formed after the through hole 4 is formed in the second glass substrate 3 bonded to the semiconductor chip 1. 10A before this step is to form an appropriate contact 7 on the exposed portion of the semiconductor chip 1 at the back of the through hole 4 by ion implantation or impurity diffusion. Then, after forming the contact 7, the electric wiring 5 is formed by vapor deposition, sputtering or the like.

【0032】本発明の第4の実施の形態を図11に示し
ている。ここでは、貫通穴4を通しての電気配線の構造
が前記各実施の形態と異なる。図11の電気配線構造で
は、ハンダや導電性ペーストあるいは導電性樹脂などの
導電材5aを貫通穴4に充填するとともに、外部引き出
し用のリード線5bを導電材5aで止着している。そし
て、係る構成は、図示の例では第1の実施の形態に適用
した例を示したが、本発明はこれに限ることはなく、第
2,第3の実施の形態に適用してもよいのはもちろんで
ある。
The fourth embodiment of the present invention is shown in FIG. Here, the structure of the electric wiring through the through hole 4 is different from that in each of the above-described embodiments. In the electrical wiring structure of FIG. 11, the through hole 4 is filled with a conductive material 5a such as solder, a conductive paste, or a conductive resin, and the lead wire 5b for external extraction is fixed with the conductive material 5a. Although the configuration has been shown as an example applied to the first embodiment in the illustrated example, the present invention is not limited to this, and may be applied to the second and third embodiments. Of course.

【0033】[0033]

【発明の効果】本発明では、デバイス本体にガラス基板
を貼り合わせてから、そのガラス基板の所定位置に貫通
穴を形成して、その貫通穴の奥にデバイス本体を露出さ
せ、その露出部分に電気的に接続する電気配線を、前記
貫通穴を通して形成する製造手順としたので、欠けや面
ダレを生じる要因となっていた接合面側の研磨処理が不
要となる。その結果、欠け等の発生を可及的に抑制でき
る。それに伴い、電気配線の破断による信号の取り出し
不能や、気密不良に伴う特性の低下等がなくなり、製品
の信頼性および歩留りが向上する。
According to the present invention, a glass substrate is attached to a device body, a through hole is formed at a predetermined position of the glass substrate, the device body is exposed in the depth of the through hole, and the exposed portion is exposed. Since the electrical wiring to be electrically connected is formed through the through hole, the polishing process on the joint surface side, which is a cause of chipping or surface sagging, is unnecessary. As a result, the occurrence of chipping or the like can be suppressed as much as possible. As a result, the signal cannot be taken out due to the breakage of the electric wiring, the deterioration of the characteristics due to the airtightness is eliminated, and the reliability and the yield of the product are improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の対象となる電子デバイスの一例である
超小型加速度センサの構造図である。
FIG. 1 is a structural diagram of a microminiature acceleration sensor which is an example of an electronic device to which the present invention is applied.

【図2】図1に示す加速度センサについての従来の製造
手順を示す図である。
FIG. 2 is a diagram showing a conventional manufacturing procedure for the acceleration sensor shown in FIG.

【図3】図1に示す加速度センサについての従来の製造
手順を示す図である。
FIG. 3 is a diagram showing a conventional manufacturing procedure for the acceleration sensor shown in FIG.

【図4】図1に示す加速度センサについての本発明の第
1の実施の形態による製造手順を示す図である。
FIG. 4 is a diagram showing a manufacturing procedure of the acceleration sensor shown in FIG. 1 according to the first embodiment of the present invention.

【図5】図1に示す加速度センサについての本発明の第
1の実施の形態による製造手順を示す図である。
FIG. 5 is a diagram showing a manufacturing procedure of the acceleration sensor shown in FIG. 1 according to the first embodiment of the present invention.

【図6】図1に示す加速度センサについての本発明の第
2の実施の形態による製造手順を示す図である。
FIG. 6 is a diagram showing a manufacturing procedure of the acceleration sensor shown in FIG. 1 according to a second embodiment of the present invention.

【図7】図1に示す加速度センサについての本発明の第
2の実施の形態による製造手順を示す図である。
FIG. 7 is a diagram showing a manufacturing procedure of the acceleration sensor shown in FIG. 1 according to a second embodiment of the present invention.

【図8】図1に示す加速度センサについての本発明の第
2の実施の形態による製造手順を示す図である。
FIG. 8 is a diagram showing a manufacturing procedure of the acceleration sensor shown in FIG. 1 according to a second embodiment of the present invention.

【図9】図1に示す加速度センサについての本発明の第
3の実施の形態による製造手順を示す図である。
FIG. 9 is a diagram showing a manufacturing procedure of the acceleration sensor shown in FIG. 1 according to a third embodiment of the present invention.

【図10】図1に示す加速度センサについての本発明の
第3の実施の形態による製造手順を示す図である。
FIG. 10 is a diagram showing a manufacturing procedure of the acceleration sensor shown in FIG. 1 according to the third embodiment of the present invention.

【図11】本発明の他の実施の形態による電気配線構造
を示す図である。
FIG. 11 is a diagram showing an electric wiring structure according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体チップ(デバイス本体) 2 第1のガラス基板 3 第2のガラス基板 4 貫通穴 5 電気配線 5a 導電材 5b リード線 6 コンタクト 7 コンタクト 1 Semiconductor Chip (Device Main Body) 2 First Glass Substrate 3 Second Glass Substrate 4 Through Hole 5 Electrical Wiring 5a Conductive Material 5b Lead Wire 6 Contact 7 Contact

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/84 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 29/84

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 デバイス本体にガラス基板を貼り合わせ
てから、そのガラス基板の所定位置に貫通穴を形成し
て、その貫通穴の奥に前記デバイス本体を露出させ、そ
の露出部分に電気的に接続する電気配線を、前記貫通穴
を通して形成することを特徴とする電子デバイスの製造
方法。
1. A glass substrate is attached to a device body, a through hole is formed at a predetermined position of the glass substrate, the device body is exposed in the depth of the through hole, and the exposed portion is electrically exposed. A method for manufacturing an electronic device, characterized in that electric wiring to be connected is formed through the through hole.
【請求項2】 請求項1において、前記ガラス基板を貼
り合わせる前に、前記デバイス本体の前記露出部分とな
る位置に適宜なコンタクトを形成しておくことを特徴と
する電子デバイスの製造方法。
2. The method of manufacturing an electronic device according to claim 1, wherein an appropriate contact is formed at a position to be the exposed portion of the device body before the glass substrates are bonded together.
【請求項3】 請求項1において、前記貫通穴を形成し
た後で、かつ前記電気配線を形成する前に、前記貫通穴
の奥の前記露出部分に適宜なコンタクトを形成すること
を特徴とする電子デバイスの製造方法。
3. The method according to claim 1, wherein after forming the through hole and before forming the electric wiring, an appropriate contact is formed in the exposed portion at the back of the through hole. Electronic device manufacturing method.
【請求項4】 前記電気配線が、前記貫通穴を含むガラ
ス基板の表面所定部位に導電体膜を成膜し、導電体膜を
介して前記デバイス本体の露出部分と、前記ガラス基板
の表面とを電気的に導通させるようにしたことを特徴と
する請求項1〜3のいずれか1項に記載の電子デバイス
の製造方法。
4. The electric wiring forms a conductor film on a predetermined site on the surface of the glass substrate including the through hole, and exposes the device body through the conductor film and the surface of the glass substrate. 4. The method for manufacturing an electronic device according to claim 1, wherein the electronic device is electrically connected.
【請求項5】 請求項1〜請求項4のいずれかの方法に
より製造された電子デバイス。
5. An electronic device manufactured by the method according to any one of claims 1 to 4.
JP8110539A 1996-04-08 1996-04-08 Manufacture of electronic device and electronic device Withdrawn JPH09283663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8110539A JPH09283663A (en) 1996-04-08 1996-04-08 Manufacture of electronic device and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8110539A JPH09283663A (en) 1996-04-08 1996-04-08 Manufacture of electronic device and electronic device

Publications (1)

Publication Number Publication Date
JPH09283663A true JPH09283663A (en) 1997-10-31

Family

ID=14538387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8110539A Withdrawn JPH09283663A (en) 1996-04-08 1996-04-08 Manufacture of electronic device and electronic device

Country Status (1)

Country Link
JP (1) JPH09283663A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1014094A1 (en) * 1998-12-21 2000-06-28 Murata Manufacturing Co., Ltd. A small size electronic part and a method for manufacturing the same, and a method for forming a via hole in the same
JP2006147892A (en) * 2004-11-22 2006-06-08 Matsushita Electric Works Ltd Electric signal takeout part structure of semiconductor component and its manufacturing method
JP2006194753A (en) * 2005-01-14 2006-07-27 Mitsubishi Electric Corp Method of measuring semiconductor capacity type acceleration sensor
JP2008534306A (en) * 2005-04-05 2008-08-28 リテフ ゲゼルシャフト ミット ベシュレンクテル ハフツング Micromechanical component and method of manufacturing micromechanical component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1014094A1 (en) * 1998-12-21 2000-06-28 Murata Manufacturing Co., Ltd. A small size electronic part and a method for manufacturing the same, and a method for forming a via hole in the same
JP2006147892A (en) * 2004-11-22 2006-06-08 Matsushita Electric Works Ltd Electric signal takeout part structure of semiconductor component and its manufacturing method
JP2006194753A (en) * 2005-01-14 2006-07-27 Mitsubishi Electric Corp Method of measuring semiconductor capacity type acceleration sensor
JP4671699B2 (en) * 2005-01-14 2011-04-20 三菱電機株式会社 Manufacturing method of semiconductor capacitive acceleration sensor
JP2008534306A (en) * 2005-04-05 2008-08-28 リテフ ゲゼルシャフト ミット ベシュレンクテル ハフツング Micromechanical component and method of manufacturing micromechanical component
JP2012020397A (en) * 2005-04-05 2012-02-02 Northrop Grumman Litef Gmbh Micromechanical component and method for fabricating micromechanical component

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