JPH09275398A - Hybrid integrated circuit and ATM-LAN adapter - Google Patents

Abstract

(57) Abstract: An ATM-LAN physical layer interface technology capable of easily matching a characteristic impedance with a transmission line is provided. A hybrid integrated circuit (9) for coupling a line terminating device for constituting an ATM-LAN physical layer interface to a transmission line includes a terminating resistor (R10) for matching characteristic impedance with the transmission line. The second pulse transformer (92) for reception is arranged close to the second pulse transformer (92), and the coupling coefficient of the second pulse transformer is set to 0.9996 or more. As a result, the negative desired inductance component or capacitance component present in the wiring from the secondary side of the second pulse transformer to the terminating resistor can be substantially ignored, and the series resistance of the pulse transformer can be reduced. At the same time, the variation can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM-LAN physical layer interface technology capable of achieving impedance matching for a plurality of types of transmission lines having different characteristic impedances, and more specifically to an ATM-LAN system. The present invention relates to a technique of modularizing a pulse transformer and a terminating resistor for coupling a line terminating device of a physical layer used to a transmission line, for example, an ATM in an IC card.
-It relates to a technique effectively applied to an adapter for a LAN interface.

[0002]

2. Description of the Related Art ATM (Asynchronous Transfer Mode);
Asynchronous transfer mode) technology for LAN (Local Area Network)
The ATM-LAN introduced in k) introduces ATM exchange technology that can freely change the band even during communication, from low speed communication and communication with a small amount of information to high speed and high bandwidth communication, Transmission / reception is performed in a one-to-one correspondence relationship, whereby ultra-high-speed data transmission with improved throughput can be realized.

To explain the concept of the physical layer interface of the ATM-LAN, a transmitting driver circuit is arranged on the transmitting side, a waveform equalizing filter circuit is arranged on the receiving side, and the signal is output from the transmitting driver circuit. The pulse waveform is limited to a prescribed waveform by the transmission waveform template filter circuit, and the output of this template filter circuit is given to one end side of the twisted pair line via the pulse transformer. The other end of the twisted pair wire is given to the waveform equalization filter circuit via a pulse transformer, and the waveform equalization filter circuit reproduces the input reception waveform into a pulse waveform. A terminating resistor is arranged on the secondary side of the pulse transformer on the receiving side to achieve matching with the characteristic impedance of the twisted pair line,
The distortion of the received signal waveform is reduced.

At this time, the functional specifications relating to the physical layer interface of the ATM-LAN are the Physical Interface Specification for 25.6 Mb / s ov issued by the ATM Forum Technical Committee from 1994 to 1995.
er Twisted Pair Cable, the twisted pair wire used for it has a maximum length of 100 m and a characteristic impedance of 100Ω UTP (Unshield Twisted Pair;
Unshielded twisted pair wire) or STP (Shield Twisted Pair) with characteristic impedance of 150Ω or characteristic impedance 120
Ω of FTP (Foiled Twisted Pair).

Transwitch "ATM Line Interface Devices for 25Mbit / s Operat" issued May 1, 1994
pages 24 and 25 of "ion TXC-07025 Chip Set DATA SHEET", TC (Transmission C for ATM-LAN)
onvergence) and PMD (Physical Media Dependent Sub)
layer), which is considered to be a circuit corresponding to the line terminating device of the ATM-LAN physical layer, which includes the transmission driver circuit, the waveform equalization filter circuit, etc. and is formed into a semiconductor integrated circuit, and a filter and A hybrid module with a transformer is shown. The terminating resistor is designed to be externally attached to the LSI (Large Scale Integration).

[0006]

However, when the present inventor examined the above-mentioned prior art, the above-mentioned TC and PMD
When the LSI for realizing the above and the hybrid module are mounted on a printed wiring board or the like, and a terminating resistor is mounted on the wiring of the receiving system connecting them, the secondary in the pulse transformer for reception included in the hybrid module. The distance from the side to the terminating resistor becomes longer,
Further, it is expected that the distance will vary depending on the mounting position of the terminating resistor. As a result, in order to match the characteristic impedance with the transmission line by the terminating resistor, it is not possible to ignore undesired inductance components and capacitance components present in the wiring from the secondary side of the pulse transformer to the terminating resistor, and the terminating resistor can be used. It has been clarified that the characteristic impedance may not be well matched with the transmission line unless the resistance value is adjusted.

Further, in consideration of the series resistance of the pulse transformer (the resistance of the pulse transformer viewed from the primary side) in matching with the characteristic impedance of the transmission line, the series resistance of the pulse transformer and the series resistance of the series resistance of the pulse transformer are considered. When the variation is large, the value of the terminating resistance must be changed depending on which of a plurality of types of twisted pair lines defined in the above-mentioned functional specifications regarding the physical layer interface of the ATM-LAN is adopted. It is expected that it will disappear. In this case, it is inconvenient that a system or an adapter card that controls the physical layer interface of the ATM-LAN and a transmission protocol must be provided for each type of twisted pair wire, and the usability for the user is deteriorated. Found by the person.

An object of the present invention is to provide an ATM-LAN physical layer interface technique which can facilitate matching of characteristic impedance with a transmission line.

Another object of the present invention is to provide an ATM-LAN physical layer interface technology capable of achieving impedance matching with respect to any of a plurality of types of transmission lines having different characteristic impedances without changing the terminating resistance. To do.

Another object of the present invention is to obtain an undesired inductance existing in the wiring from the secondary side of the pulse transformer on the receiving side to the terminating resistor in order to match the characteristic impedance with the transmission line by the terminating resistor. An object of the present invention is to provide an ATM-LAN physical layer interface technology capable of substantially ignoring components and capacity components.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the hybrid integrated circuit (9) for coupling the line terminating device (8) for constructing the ATM-LAN physical layer interface to the transmission line (3, 4) has a characteristic impedance matching with the transmission line. Terminal resistor (R1
0). The terminating resistor is mounted on the substrate (93) of the hybrid integrated circuit at an interval of 10 mm or less with the second pulse transformer (92) for reception. To arrange the second pulse transformer and the terminating resistor close to each other as described above, for example,
The secondary side of the second pulse transformer and the terminating resistor,
It is possible to adopt a mounting form in which the front and back surfaces of the substrate are commonly connected to the pair of output terminals.

According to this, the distance from the secondary side of the pulse transformer to the terminating resistor is extremely short, and
Since the distance is substantially constant in any of the hybrid integrated circuits, in order to match the characteristic impedance with the transmission line by the terminating resistor, the second pulse transformer (9
The negative desired inductance component or capacitance component existing in the wiring from the secondary side of 2) to the terminating resistor (R10) can be substantially ignored. Therefore, it becomes easy to match the characteristic impedance with the transmission line without individually adjusting the value of the terminating resistor. The hybrid integrated circuit outputs a transmission waveform filter circuit (90) for limiting the transmission pulse waveform output from the line terminating device to a prescribed waveform and an output of the transmission waveform filter circuit.
A first pulse transformer (91) received on the next side is also mounted.

The first and second pulse transformers (9
By setting the coupling coefficient of (1, 92) to 0.9996 or more, the number of turns of the pulse transformer can be reduced to, for example, about 30 or less, and the resistance viewed from the primary side of the pulse transformer, that is, the series resistance is reduced. It can be done and the variation can be suppressed. For example, the first and second
Pulse transformer of manganese-zinc system with relative permeability of 5
By applying 000 or more cores, the series resistance can be reduced to 1Ω or less. Since the resistance viewed from the primary side of the pulse transformer, that is, the series resistance can be reduced and its variation can be suppressed, it is possible to reduce the variation of the resistance of the pulse transformer to a plurality of types of transmission lines defined in the functional specifications relating to the physical layer interface of the ATM-LAN. If an intermediate value of those characteristic impedances is adopted as the terminating resistance (R10), the series resistance and the terminating resistance of the second pulse transformer will be the same regardless of which transmission line is used. The impedance does not exceed the allowable range that can match the characteristic impedance of the transmission line, resulting in impedance mismatch.
Thus, for example, as the transmission line, a twisted pair wire with a shield of 150Ω, which is used in an ATM-LAN having a transmission speed of 25.6 megabits / second,
About 1 which is an intermediate value between 100Ω unshielded twisted pair wire and 120Ω shielded twisted pair wire.
When 20Ω is adopted as the resistance value of the terminating resistor, impedance matching can be performed in common with the transmission lines of the three types of specifications. By this, A
A system or an ATM-LAN that is convenient for the user without the inconvenience of having to provide a system or adapter card that controls the physical layer interface or transmission protocol of TM-LAN for each type of twisted pair line An adapter can be provided.

The first pulse transformer (91) for transmission built in the hybrid integrated circuit (9) is also constructed with the same specifications as the second pulse transformer (92) for reception, and its coupling coefficient and series. Since the resistance is the same as that of the second pulse transformer (92), the return loss required on the transmitting side can be made extremely small. This is an ATM-LAN in which a sending node and a receiving node are connected in a one-to-one correspondence.
Due to the nature of the above, the hybrid integrated circuit (9) and the ATM-LAN adapter to which it is applied can improve the transmission accuracy of one transmission system as a whole.

The ATM-LAN adapter comprises the hybrid integrated circuit (9) and a line terminating device (8) coupled to the hybrid integrated circuit, and the line terminating device outputs to the input terminal of the hybrid integrated circuit. Transmission driver circuit (8
0) and a waveform equalization filter circuit (81) whose input is coupled to the output terminal of the hybrid integrated circuit and which reproduces the received waveform obtained from the second pulse transformer into a pulse waveform, thereby forming a semiconductor integrated circuit. be able to. The hybrid integrated circuit eliminates external parts such as the terminating resistor, which contributes to downsizing of the ATM-LAN adapter.

The ATM-LAN adapter is an ATM controller (106-110) for controlling the ATM-LAN protocol for data to be transmitted via the line terminating device and data received via the line terminating device.
In addition, the hybrid integrated circuit and the line terminating device of the physical layer together with the ATM controller can be mounted on a card board (100) of a size mountable in a personal computer to form an IC card.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

<< ATM-LAN Physical Layer System Configuration >> FIG.
An example of a system configuration of a TM-LAN physical layer is shown. AT
The M-LAN is a transmission line exclusive LAN. In the transmission line-proprietary type LAN, only one node is connected to one transmission line, which is concentrated on a hub or the like and exchanged. Although not particularly limited, the embodiments of the invention described below focus on an ATM-LAN of 25.6 megabits / second. In FIG. 3, reference numeral 1 is a terminal device such as a personal computer or a workstation. Reference numeral 2 is an ATM-LAN interface circuit provided in a one-to-one correspondence with the terminal device 1. 3 and 4 are twisted pair lines (transmission lines), 5 is an AT where the above twisted pair lines 3 and 4 are concentrated
M hub, 6 is a cable for high speed transmission. In addition, in FIG. 3, the twisted pair wires concentrated on the ATM hub 5 are 3, 4
However, in reality, twisted pair lines from other terminal devices are also concentrated. Although not shown, the ATM hub 5 includes a switch matrix as an ATM switch for switching the transmission path, a demultiplexing device for performing transmission between the hubs via the high-speed transmission cable 6, and the like.

The ATM-LAN interface circuit 2
The hub and the hub 5 are PMD (Physical Med) for ATM-LAN.
ia Dependent; Physical medium dependent) A line termination device (hereinafter simply referred to as a PMD semiconductor chip) 8 which is made into a semiconductor integrated circuit for a sublayer, and a pulse transformer for connecting the PMD semiconductor chip 8 to the twisted pair lines 3 and 4. It includes a hybrid integrated circuit (hereinafter also simply referred to as a transformer module) 9 provided.

<< PMD Semiconductor Chip >> In FIG.
An example block diagram of the MD semiconductor chip 8 and the transformer module 9 is shown. The PMD semiconductor chip 8 is not particularly limited, but by the CMOS integrated circuit manufacturing technology,
It is formed on one semiconductor substrate such as single crystal silicon. The PMD semiconductor chip 8 has a pair of transmitting terminals TX-A, TX-B, a pair of receiving terminals RX-A, RX-B, and a data output terminal RX-D as representatively shown external terminals.
data, a data input terminal TX-Data, a clock input terminal TX-Clk, and a clock output terminal RX-Clk. The PMD semiconductor chip 8 includes a transmission driver circuit 8
0, waveform equalization filter circuit 81, loopback circuit 8
2. A PLL (Phase lock loop) circuit 83 for clock extraction, a data latch circuit 84 for reception, and a data latch circuit 85 for transmission are provided.

The transformer module 9 will be described in detail later, but as shown in FIG. 1, the input terminal TY-
A differential signal supplied from A and TY-B is received by a transmission waveform filter circuit (hereinafter also simply referred to as a transmission filter or a transmission waveform template filter circuit) 90, and the output of the transmission filter 90 is received by a first pulse transformer (hereinafter simply referred to as "transmission filter"). Also referred to as a transmission transformer) 91 is received on the primary side and its secondary side is coupled to the transmission terminals TZ-A and TZ-B, and the reception terminal R
A primary side of a second pulse transformer (hereinafter also simply referred to as a receiving transformer) 92 is coupled to ZA and RZ-B, a secondary side thereof is coupled to output terminals RY-A and RY-B, and at the same time, a receiving transformer 92 A terminating resistor R10 for impedance matching with the twisted pair wire 4 is arranged close to the secondary side.

The data input terminal TX-D shown in FIG.
data is an input terminal for data signals such as characters and images handled inside the terminal device 1 such as a personal computer, and the data latch circuit 85 is synchronized with the transmission clock supplied from the clock input terminal TX-CLK. Is taken into. The data fetched by the data latch circuit 85 is output from the transmission driver circuit 80 to the transmission terminals TX-A and TX-B as a differential signal. Transmission terminal T
X-A and TX-B are input terminals T of the transformer module 9.
The input terminals TY-A and TY-A are connected to YA and TY-B.
The signal input to TY-B is transmitted by the transmission filter 90.
The output pulse waveform is limited to within the specified value specified by the template, and the transmission terminal TZ is transmitted via the transmission transformer 91.
-A, TZ-B is output. Transmission terminal TZ-A, TZ
The transmission output signal from −B is transmitted via the twisted pair wire 3. The maximum length of the twisted pair wires 3 and 4 is 100m,
UTP (unshielded twisted pair wire) with characteristic impedance of 100Ω or ST of 120Ω or 150Ω
P (shielded twisted pair wire).

On the other hand, as shown in FIG.
The signals input from the receiving terminals RZ-A and RZ-B from
The receiving terminals RX-A and RX of the PMD semiconductor chip 8 through the receiving transformer 92 and the output terminals RY-A and RY-B.
-Entered in B. The input reception signal is reproduced into a pulse waveform by the waveform equalization filter circuit 81. In an ATM-LAN system with a transmission rate of 25.6 Mbit / sec, 4B / 5B converted NRZI (Non-Return to Ze) is used.
Since the ro Inverse) code is used, the actual transmitted signal has a maximum of 32 Mbit / sec and includes frequency components up to 16 MHz. Therefore, the waveform equalization filter circuit 81 is designed to have high-pass characteristics in the frequency range up to 16 MHz.

As shown in FIG. 4, the PLL circuit 83 synchronously extracts a stable 32 MHz clock signal from the output signal of the waveform equalization filter circuit 81 toward the clock output terminal RX-CLK. The output data of the waveform equalization filter circuit 81 is latched by the data latch circuit 84 by the clock signal extracted in synchronization with the data output terminal RX-Da.
Output from ta. The loopback circuit 82 is
At the same time as the circuit provided to hold the synchronization of the PLL for a certain time by substituting the transmission signal when the reception signal detecting means (not shown) detects disconnection of the reception signal during communication. For example, the PMD semiconductor chip 8 has a function of preventing an unnecessary signal from being transmitted during non-transmission immediately after the power is turned on.

<< Transformer Module >> FIG.
A detailed example circuit of the transformer module 9 shown in FIG. 4 is shown. In FIG. 1, the transformer module 9
Is a transmission filter 90, a transmission transformer 91, and a reception transformer 92 on the front and back surfaces of the glass epoxy substrate 93.
And a terminating resistor R10 are arranged, and further, the transmission transformer 9
1 and the transmission terminals TZ-A and TZ-B, and between the reception transformer 92 and the reception terminals RZ-A and RZ-B, a common choke coil 9 for removing a common-mode noise component.
5, 94 are arranged respectively.

The transmission filter 90 has capacitors C24 to C.
29, inductances L3 to L6 and resistors R12 and R1
3, R19 are connected as shown in the figure. As described above, the transmission filter 90 limits the input pulse waveform to within the specified value specified by the template (pulse mask) and outputs it. Such a template is specified by, for example, ATM_Forum / 94-1008R5, and in the physical layer interface of the above ATM-LAN, in order to improve the transmission efficiency, a logical value "0" or "1" in the transmission information is used. The number of consecutive bits (the number of symbols) of "is limited to 5 symbols, and the template defines the waveform (transformer output waveform) for each number of symbols having the same logical value. The transmission filter 90 is adopted to output a transmission waveform satisfying such a template from the secondary side of the transmission transformer 91.

FIG. 2 shows the details of the mounting form of each of the above-mentioned circuit components on the front and back surfaces of the glass epoxy substrate 93. In FIG. 2, LD1 to LD14 are circular lands LD15 to LD, each of which is a conductive pattern communicating with the front and back surfaces.
18 is a rectangular land consisting of a conductive pattern, TH1, TH
Reference numeral 2 is a through hole through which a conductive layer is penetrated on the front and back surfaces of the glass epoxy substrate 93. Each circuit component forming the transmission filter 90 and the terminating resistor R10 are mounted at predetermined positions on a wiring layer (illustrated by a thick solid line) formed on the surface of the glass epoxy substrate 93 as shown in FIG. Has been done. As shown in FIG. 2B, transformers 91, 92 and choke coils 94, 95 are provided on the back surface of the glass epoxy substrate 93, and the lands LD5, LD7, LD8, LD9,
LD17, LD18, LD12, LD14, LD15,
The LD 16 and the through holes TH1 and TH2 are mounted by connecting corresponding lead wires. The leads are conceptually indicated by thick dashed lines. In FIG. 1, lands that are unused in the circuit are not shown.

The glass epoxy board 93 on which each circuit element is mounted is mounted and fixed on a lead frame (not shown) via lands LD1 to LD14 in the assembly process, and in that state, each circuit element is entirely Then, it is molded with resin 96, and finally the frame portion of the lead frame is cut and removed from the lead terminal portion to complete the transformer module 9. In the example of FIGS. 1 and 2, the terminal RZ
-A, RZ-B, TZ-A, TZ-B, RY-A, RY
-B, TY-A, and TY-B are illustrated as circularly fixed lead terminals to the land.

The epoxy substrate 93 is not particularly limited, but has a length of 10.0 mm, a width of 16.5 mm, and a thickness of 0.38 mm, and has a total thickness after mounting the circuit components. It is specified within a range of 1.5 mm at maximum.

Here, the distance between the secondary side of the receiving transformer 92 and the terminating resistor R10 is suppressed to within 10 mm, and the total length of the wiring connecting the secondary side of the receiving transformer 92 and the terminating resistor R10 depends on the distance dimension. It has a relatively short length as specified. According to the example of FIG. 2, the length of the wiring pattern connecting the terminating resistor R10 to the lands LD5 and LD7, the secondary side of the receiving transformer 92 and the lands LD5 and LD5.
The length of the lead wire connecting to LD7 is a few mm in total.
Alternatively, it is suppressed to about 10 mm. The wiring length is substantially constant in any of the transformer modules 9 manufactured in different manufacturing lots due to the property of forming the transformer module 9 including the terminating resistor R10. According to this, since the distance from the secondary side of the receiving transformer 92 to the terminating resistor R10 is extremely short, and the distance is substantially constant in any transformer module, transmission is performed by the terminating resistor R10. In order to match the characteristic impedance with the line, 2 of the receiving transformer 92 is used.
Undesired inductance components and capacitance components existing in the wiring from the next side to the terminating resistor R10 can be substantially ignored.

The transmitting transformer 91 and the receiving transformer 9
Reference numeral 2 is a pulse transformer having an ultra-wide band characteristic, and a coupling coefficient is set to 0.9996 or more by applying a manganese-zinc system core having a relative magnetic permeability of 5000 or more. As a result, the number of turns of the pulse transformers 90 and 91 can be set to about 30 or less, and the resistance viewed from the primary side of the pulse transformer, that is, the series resistance can be reduced to 1Ω or less and its variation can be suppressed. Can be done.

For the transmission transformer 91, this characteristic shows that the return loss (transmitter return loss) of the transmission circuit, which is defined by ATM_Forum / 94-1008R5 or the like.
s = TRL) is satisfied. Return loss is 1 to
14 dB or more in the frequency band of 6 MHz, 6 to 17 MH
It is defined as 12 dB or more in the frequency band of z and 8 dB or more in the frequency band of 17 to 25 MHz. Here, the return loss will be described with reference to FIG. FIG.
As shown in (A) to facilitate understanding, the signal source V
s, the impedance r0 on the signal source side, and the transformer,
Model the impedance RL on the transmission line and the load side,
It is represented as an equivalent circuit as shown in FIG. In FIG. 5, L is the inductance of the transformer, rt is the series resistance of the transformer, and k is the coupling coefficient of the transformer. k
L is the inductance due to the main magnetic flux of the transformer, (1-
k) · L is the leakage inductance. Impedance ZL looking into the load side from the signal source Vs is, ZL = rt + jω (1 -k) L + {ω 2 kL 2 (1-k)
+ JωkL (rt + RL)} / (rt + RL + jωL). Here, ω = 2πf, and f is the frequency.

In the above equation of impedance ZL, k
≈1, ωL >> rt + RL, impedance ZL
Can be simplified to ZL≈2rt + RL.

The definition of return loss is 10 log (1
/ Γ ² ), and Γ (reflectance) is Γ = | (r0-ZL)
/ (R0 + ZL) | Therefore, ATM_Forum / 94-1
In order to satisfy the return loss specified by 008R3 relatively easily, it is desirable to use a high-performance transformer that satisfies the condition of k≈1, ωL >> rt + RL, and the transformers 91 and 92 satisfy the condition. You can do it.

With respect to the characteristics of the above-mentioned transformer, for the receiving transformer 92, the resistance viewed from the primary side of the transformer 92, that is, the series resistance can be made small and its variation can be suppressed. Accordingly, for a plurality of types of transmission lines defined in the functional specifications relating to the physical layer interface of ATM-LAN, if an intermediate value among the characteristic impedances is adopted as the terminating resistor R10, the characteristic impedances are different. Regardless of which transmission line is used, the impedance mismatch between the series resistance of the receiving transformer 92 and the terminating resistor R10 does not exceed the allowable range in which the characteristic impedance of the twisted pair line can be matched, resulting in impedance mismatch. Therefore, each transmission rate is 2
Shielded twisted pair wire of 150Ω, which is used for ATM-LAN of 5.6 megabits / second, 10
About 12 which is an intermediate value between 0Ω unshielded twisted pair wire and 120Ω unshielded twisted pair wire.
If 0Ω is adopted as the resistance value of the terminating resistor R10,
Impedance matching can be commonly applied to any of the three types of transmission lines.

FIG. 6 shows an example of an ATM-LAN adapter 2A to which the PMD semiconductor chip 8 and the transformer module 9 are applied. This ATM-LAN adapter 2A has a transformer module 9 together with a PMD semiconductor chip 8 and other integrated circuits, in a width of 85.6 mm and a length of 5.
It was realized by mounting it on a standard IC card substrate 100 of so-called type 2 having a thickness of 4.0 mm and a thickness of 5.0 mm.
For example, ATM-LAN with a transmission rate of 25.6 Mbit / sec
IC card for. A transmission / reception signal of the transformer module 9 is connected to a twisted pair cable 102 having a maximum length of 5 m through a first terminal group (not shown) provided on the IC card substrate 100 and a connector 101, and the twisted pair cable 102 is a specified jack / socket. 103
Is connected to the twisted pair cable 104 such as UTP, STP or ETP having a maximum length of 90 m. The twisted pair cables 102, 104 and the jack / socket 103 correspond to the twisted pair wires 3, 4.
On the other hand, the IC card substrate 100 is inserted into a personal computer body such as a notebook type,
Card Second terminal group 10 provided on card board 100
5 to PCMCIA (Personal Computer Memory Card)
International Association) It is directly or indirectly connected to the microprocessor installed in the personal computer through a bus interface, etc.
It enables transmission / reception, display, and processing of various data using the TM-LAN adapter card.

The TC (Transmission Con) shown in FIG.
The vergence) unit 106 is an AT together with the PMD semiconductor chip 8.
It constitutes a physical layer in the M-LAN and has functions such as scramble / descramble of transmission / reception data cells, 4-bit / 5-bit conversion, and NRZ / NRZI code conversion. The ATM controller 107, together with the microprocessor 108, the ROM 109, and the RAM 110, realizes functions such as conversion of various data of variable-length packets and ATM cells of fixed length, interface conversion of various different bus formats, and the like. Regarding the functional specifications of PMD and TC, from 1994 to 1995
Physica issued by ATM Forum Technical Committee
l Interface Specification for 25.6Mb / s over Twiste
It is described in detail in d Pair Cable. The TC section 10
6 and ATM controller 107 are a single LSI (AT
M-LSI). The TC section 10
An ATM controller 107, a microcomputer 106, a ROM 109, and a RAM 110 are ATs that perform ATM-LAN protocol control for transmission / reception data.
Configure the M controller. The buffer memory 111 composed of DRAM is used by the TM controller unit 107 as a data buffer when transmitting and receiving data.

According to the above embodiment, there are the following effects. [1] A transformer module (hybrid integrated circuit) 9 for coupling a PMD semiconductor chip (line terminator) 8 for configuring an ATM-LAN physical layer interface to twisted pair lines (transmission lines) 3 and 4 is a twisted pair line. And a terminating resistor R10 for matching the characteristic impedance with. The terminating resistor R10 is mounted on the substrate 93 of the transformer module at an interval of 10 mm or less from the receiving transformer 92. As a mounting mode, the secondary side of the receiving transformer 92 and the terminating resistor R10 are connected from the front and back surfaces of the substrate 93 to the pair of output terminals RY-A, RY-B (lands LD7, L).
By adopting the form of common connection to D5), the wiring length for connecting the secondary side of the receiving transformer 92 and the terminating resistor R10 can be realized with a total length of several mm or 10 mm.

According to this, 2 of the receiving transformer 92
The distance from the next side to the terminating resistor R10 is extremely short,
Since the distance is substantially constant in any transformer module, the wiring from the secondary side of the receiving transformer 92 to the terminating resistor R10 is used for matching the characteristic impedance with the twisted pair line by the terminating resistor R10. The existing negative desired inductance component or capacitance component can be substantially ignored. Therefore, it becomes easy to match the characteristic impedance with the twisted pair wire without individually adjusting the value of the terminating resistance.

[2] By setting the coupling coefficient of the pulse transformers 91 and 92 to 0.9996 or more, the number of turns of the pulse transformer can be set to, for example, about 30 or less, and the series resistance of the pulse transformer can be reduced. It can be done and the variation can be suppressed. By applying a manganese-zinc-based core having a relative magnetic permeability of 5000 or more to the pulse transformers 91 and 92, the series resistance can be set to 1Ω or less.

Since the resistance viewed from the primary side of the pulse transformer, that is, the series resistance can be reduced and its variation can be suppressed, a plurality of types of transmission lines defined in the functional specifications relating to the physical layer interface of the ATM-LAN can be used. On the other hand, if an intermediate value of those characteristic impedances is adopted for the terminating resistor R10, the impedance between the series resistance of the receiving transformer and the terminating resistor R10 will be adopted regardless of which transmission line the characteristic impedances are different from. Does not exceed the allowable range that can match the characteristic impedance of the twisted pair wire, resulting in impedance mismatch. As a result, each of the transmission rates of 25.6 Mbit / sec.
About 150Ω, which is an intermediate value between the shielded twisted pair wire of 150Ω, the unshielded twisted pair wire of 100Ω, and the unshielded twisted pair wire of 120Ω, which is used for the TM-LAN, the terminal resistance R1 is set.
When adopted as a resistance value of 0, impedance matching can be performed in common for the transmission lines of the three types of specifications.

[3] The transmission transformer 91 built in the transformer module is also configured to have the same specifications as the reception transformer 92, and its coupling coefficient and series resistance are also the same as those of the reception transformer 92. The loss can also be made extremely small. This is an ATM-LAN in which a sending node and a receiving node are connected in a one-to-one correspondence.
Due to the nature of the above, the transformer module 9, and further the ATM-LAN adapter to which it is applied or the ATM-LAN adapter in the form of an IC card can improve the transmission accuracy of one transmission system as a whole.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example, the ATM-LAN adapter provided in the hub 5 can be composed of the PMD semiconductor chip 8 and the transformer module 9. Further, the substrate size of the transformer module 9 is not limited to the above description and can be changed as appropriate. Further, the mounting form of the receiving pulse transformer and the terminating resistor is not limited to the mounting form on the front and back sides of the substrate as described above. Also, A
The TM-LAN adapter is not limited to a so-called type 2 IC card, but can be realized as an aerial circuit board.

[0045]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the hybrid integrated circuit (9) has a terminating resistor (R10) for matching the characteristic impedance with the transmission line, and the terminating resistor is the second pulse transformer (9) for receiving.
2) and 10 mm apart from the substrate (9) of the hybrid integrated circuit.
It is implemented in 3). Therefore, the distance from the secondary side of the pulse transformer to the terminating resistor is extremely short,
Moreover, the distance is substantially constant in any of the hybrid integrated circuits. Therefore, in order to match the characteristic impedance with the transmission line by the terminating resistor, the distance from the secondary side of the second pulse transformer (92) to the above Negative desired inductance components and capacitance components existing in the wiring up to the terminating resistor (R10) can be substantially ignored. Then, it becomes easy to match the characteristic impedance with the transmission line without individually adjusting the value of the terminating resistor.

By adopting a mounting form in which the secondary side of the second pulse transformer and the terminating resistor are commonly connected to the pair of output terminals from the front and back surfaces of the substrate, the second pulse transformer and the terminating resistor are connected. The close arrangement of the resistors as described above can be easily realized.

The first and second pulse transformers (9
By setting the coupling coefficient of (1, 92) to 0.9996 or more, the number of turns of the pulse transformer can be reduced to, for example, about 30 or less, and the resistance viewed from the primary side of the pulse transformer, that is, the series resistance is reduced. It can be done and the variation can be suppressed. For example, the first and second
Pulse transformer of manganese-zinc system with relative permeability of 5
By applying 000 or more cores, the series resistance can be reduced to 1Ω or less.

Since the resistance viewed from the primary side of the pulse transformer, that is, the series resistance can be reduced and its variation can be suppressed, a plurality of types of transmission lines defined in the functional specifications relating to the physical layer interface of the ATM-LAN can be used. On the other hand, if an intermediate value of those characteristic impedances is adopted as the terminating resistor (R10), no matter which transmission line the characteristic impedances differ, the series resistance and the terminating end of the second pulse transformer are adopted. The impedance mismatch with the resistance does not exceed the allowable range for matching the characteristic impedance of the transmission line. According to the above, each of the transmission lines is used in an ATM-LAN having a transmission rate of 25.6 Mbit / sec.
About 150Ω shielded twisted pair wire, 100Ω unshielded twisted pair wire, and 120Ω unshielded twisted pair wire, by adopting an intermediate value of about 120Ω as the resistance value of the terminating resistor, 3
It is possible to perform impedance matching in common for transmission lines of various specifications. With them, ATM-LAN
It is not inconvenient to provide a system or adapter card that controls the physical layer interface or transmission protocol for each type of twisted pair wire, and also provides a user-friendly system or ATM-LAN adapter. can do.

The first pulse transformer (91) for transmission, which is built in the hybrid integrated circuit (9), has the same specifications as the second pulse transformer (92) for reception. Since the resistance is the same as that of the second pulse transformer (92), the return loss required on the transmitting side can be made extremely small. Therefore, the ATM-LAN in which the sending node and the receiving node are connected in a one-to-one correspondence
Due to the nature of the above, the hybrid integrated circuit (9) and the ATM-LAN adapter to which it is applied can improve the transmission accuracy of one transmission system as a whole.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a transformer module according to an example of a hybrid integrated circuit of the present invention.

FIG. 2 is an explanatory diagram showing an example of a mounting form of circuit components that constitute a transformer module over both front and back surfaces thereof.

FIG. 3 is an explanatory diagram showing an example of a system configuration of an ATM-LAN physical layer.

FIG. 4 is a block diagram showing an example of a PMD semiconductor chip and a transformer module.

FIG. 5 is an explanatory diagram of return loss.

FIG. 6 is a block diagram showing an example of an ATM-LAN adapter card to which a PMD semiconductor chip and a transformer module are applied.

[Explanation of symbols]

 3, 4 twisted pair line (transmission line) 8 PMD semiconductor chip (line terminator) 80 transmission driver circuit 81 waveform equalization filter circuit TY-A, TY-B input terminal TZ-A, TZ-B transmission terminal RY-A, RY-B output terminal RZ-A, RZ-B reception terminal 9 transformer module (mixed integrated circuit) 90 transmission waveform filter circuit (transmission filter) 91 transmission transformer (first pulse transformer) 92 reception transformer (second pulse transformer) ) 93 substrate LD1 to LD14 circular land R10 terminating resistor 2A ATM-LAN adapter card 100 IC card substrate 106 TC section 107 ATM controller section 108 microcomputer 109 ROM 110 RAM

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuyuki Yokota 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi Computer Engineering Co., Ltd. (72) Inventor Yoshiharu Nagayama 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device In the development center (72) Inventor Toru Ito 244, Katsuragi, Tottori City, Tottori Prefecture Hitachi Ferrite Electronics Co., Ltd.

Claims (7)

[Claims] 1. A pair of input terminals and a pair of output terminals used for connection to a physical layer line terminating device used in an ATM-LAN system, and a connection to a transmission line used in an ATM-LAN system. A board having a pair of transmission terminals and a pair of reception terminals used, a transmission waveform filter circuit for limiting a pulse waveform given from the pair of input terminals to a prescribed waveform, and a transmission waveform filter circuit A first pulse transformer having a secondary side connected and a secondary side connected to the pair of transmission terminals; and a primary side connected to the pair of reception terminals and a secondary side having the first side.
A second pulse transformer connected to the pair of output terminals, and a terminating resistor connected to the second pulse transformer are provided, and the second pulse transformer and the terminating resistor are 10 mm.
A hybrid integrated circuit characterized by being closely arranged at a distance of within. 2. The secondary side of the second pulse transformer and the terminating resistor are commonly connected to the pair of output terminals from the front and back surfaces of the substrate and mounted on the substrate. The hybrid integrated circuit according to claim 1. 3. The hybrid integrated circuit according to claim 1, wherein the first and second pulse transformers each have a coupling coefficient of 0.9996 or more. 4. The first and second pulse transformers,
4. The hybrid integrated circuit according to claim 3, which has a manganese-zinc based core having a relative magnetic permeability of 5000 or more and a series resistance of 1 Ω or less. 5. The terminating resistor, as the transmission line, is an ATM-LAN having a transmission rate of 25.6 megabits / second.
150Ω shielded twisted pair wire, 100Ω unshielded twisted pair wire, 12
The hybrid integrated circuit according to claim 4, wherein the shielded twisted pair wire of 0Ω has a common value of about 120Ω. 6. The hybrid integrated circuit according to claim 4, and the line termination device coupled to the hybrid integrated circuit, wherein the line termination device outputs to the pair of input terminals of the hybrid integrated circuit. And a waveform equalization filter circuit for reproducing the received waveform obtained from the second pulse transformer into a pulse waveform by coupling the input to the pair of output terminals of the hybrid integrated circuit. ATM-LAN characterized by being formed into a semiconductor integrated circuit
adapter. 7. An ATM controller for performing an ATM-LAN protocol control for data to be transmitted via the line terminating device and data received via the line terminating device, further comprising:
6. The ATM- according to claim 5, wherein the hybrid integrated circuit and the line terminating device are mounted on a card board having a size mountable on a personal computer.
LAN adapter.