JPH09270761A - Video/audio multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit and read even audio data asynchronous to video signals without generating noise, to simplify constitution and to improve performance. SOLUTION: Video/audio multiplex composite serial signals are demultiplexed into the video signals and the audio data by a V/A demultiplex circuit 1 and the audio data are stored in a memory 3. At the time of storing the audio data, a write counter 4 counts the number of data written in fixed time. Also, a read counter 6 counts the number of the data read in the fixed time from the memory 3. Two counter values are inputted to a write/read data number difference detection circuit 7 and a difference between the both is obtained. In the case that the number of the read data is smaller than the number of the written data, the read counter 6 is advanced by a variable speed device 5, and as a result, a read speed is accelerated. The read speed from the memory 3 is varied and the transmission of asynchronous digital audio data is made possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video / audio multiplexer, and more particularly to the reproduction of asynchronous digital audio data not synchronized with video.

[0002]

2. Description of the Related Art As a standard for superimposing (multiplexing) digital audio data on a digital composite video signal for transmission, SMPTE-272M and the like are known. The multiplexing method according to this standard uses digital audio data (AES / E
(BU) is time-axis compressed into packets, and then a flag is added to each packet to multiplex the blanking of the video signal.

A method for separating a digital composite video signal and digital audio data will be described below. FIG.
FIG. 1 is a block diagram of a conventional separation circuit of this type.
In the figure, a V / A separation circuit 11 separates the digital audio data from the digital composite video by the flag added to the audio data packet, and temporarily stores the digital audio data in the digital audio data memory 13. On the other hand, the read clock generating circuit 12 generates a clock for reading digital audio data from the digital composite video signal, and the digital audio data in the digital audio memory 13 is time-axis expanded and read by this clock. The digital audio data is reproduced and output as described above.

As another conventional technique, Japanese Examined Patent Publication No. 63-969.
The technique disclosed in Japanese Patent Publication No. 7 is known. In the stuff synchronization method described in Japanese Patent Publication No. 63-9697, the input signal from the asynchronous low order group is once written in the buffer memory by the write clock extracted by the write clock extraction circuit, and the speed is slightly faster than the write clock. It is synchronized by reading with the read clock. However, since the read clock is set to a speed slightly higher than the write clock as described above, the phase of the write clock is gradually delayed, and there is a period in which there is no signal to be read. Therefore, in the phase comparator, the phases of the write clock and the read clock are compared, and when the difference is close to 1 bit, the stuff request signal is sent to the stuff control circuit,
The stuff control circuit stops the read clock by one bit. When the read clock is stopped by one bit in this way, one stuff pulse is eventually inserted in the synchronization signal.

Still another conventional technique is Japanese Patent Laid-Open No. 62-1.
The technique disclosed in 201335 has been proposed.
The technique disclosed in Japanese Unexamined Patent Publication No. 62-120135 discloses a first asynchronous multiplexer and a second asynchronous multiplexer each having a multiplexer for encoding and a divider for decoding. A buffer memory is provided between the buffer memory and the buffer memory, the buffer memory stores data at the data rate of the first asynchronous multiplexer, and the contents of the buffer memory are sampled at the data rate of the second asynchronous multiplexer. A data multiplex transmission device for reading.

[0006]

However, when the above-mentioned prior art is used, the digital audio data that can be transmitted must be synchronized with the digital video signal. When synchronized, the number of digital audio data transmitted in a constant time is constant, but when not synchronized, the number of digital audio data transmitted in a constant time is not constant. For example, the data read clock of the digital audio data stored in the memory is generated from the composite video signal, the number of read digital audio data becomes excessive or insufficient, and the digital audio data cannot be read accurately.

Further, in both of the conventional examples described in Japanese Patent Publication No. 63-9697 and Japanese Patent Application Laid-Open No. 62-120135, the data writing speed and the data reading speed with respect to the memory are changed. Not only is it complicated, but there is considerable difficulty in improving the accuracy in terms of functionality.

Generally, digital audio data synchronized with a digital video signal is usually output from a VTR or the like.
In other cases, for example, live broadcast images and announcer voices are often not synchronized. In the case of synchronization, it is necessary to add equipment such as inputting a video signal to audio equipment, which leads to an increase in constituent equipment.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore the object of the present invention is to solve the above-mentioned problems inherent in the prior art and not to synchronize (asynchronize) with a digital video signal. It is an object of the present invention to provide a novel video / audio multiplexing device which enables transmission of digital audio data, avoids the increase in the number of constituent devices as described above, and improves the functions.

[0010]

In order to achieve the above object, an asynchronous digital audio separation circuit multiplexed in a digital composite video signal according to the present invention is a circuit for varying a speed of a clock for reading digital audio data. Have. Specifically, a write data counter (4 in FIG. 1) used when storing digital audio data in the memory and a read data counter (6 in FIG. 1) used when reading digital audio data from the memory.
And a write / read data number difference detection circuit (7 in FIG. 1) for controlling the variable speed device by calculating the difference between the values of the write data counter and the read data counter, and a control signal from this write / read number difference detection circuit. And a variable speed device (5 in FIG. 1) for changing the speed of the digital audio data read clock.

[0011]

In the present invention, the digital audio data which is not synchronized with the digital video can be read by changing the digital audio data read clock, thus enabling asynchronous audio data transmission.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a preferred embodiment of the present invention.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Referring to FIG. 1, a video / audio multiplexer according to the present invention inputs a digital signal in which video and asynchronous digital audio data are multiplexed, and separates a digital video signal and digital audio data. A separation circuit (V / A separation circuit) 1, a read clock generation circuit 2 for generating a clock for reading digital audio data from a digital video signal output from the V / A separation circuit 1, and the V / A separation circuit 1 A write data counter 4 which receives the digital audio data output from the V / A separation circuit 1 and counts the number of data, and stores the digital audio data from the V / A separation circuit 1 at the address from the write data counter 4 (read clock). Memory 3 for outputting digital audio data with the clock from counter 6
And a variable speed device 5 that receives the clock output from the read clock generation circuit 2 and changes the clock frequency with a control signal output from the write / read number difference detection circuit 7.
And a read data counter 6 that receives a clock from the variable speed device 5 and determines a read address (clock).
And a write / read data number difference detection circuit 7 that compares the addresses (clocks) from the write data counter 4 and the read data counter 6 and outputs a control signal for changing the audio read speed.

The read clock generation circuit 2 is a circuit for extracting a clock from the serial digital video signal, and is realized by using a SAW filter, a tank circuit, etc. Specifically, a 143 MHz clock is generated from the serial digital video signal of 143 Mbps. Extract.

Next, the variable speed device 5 will be described by showing concrete columns, and the variable speed device 5 will receive an input clock (hereinafter referred to as clock 1).
Therefore, a clock (hereinafter referred to as clock 2) having a frequency different from the clock 1 synchronized with the clock 1 is generated. Specifically, a clock of about 48 KHz is generated from a clock of 143 MHz. An example of the generation method will be described below.

When the variable speed device is composed of the counter and the ROM, the clock 1 input to the variable speed device is input to the counter. This counter is 0 to 119 at clock 1.
It is a counter that counts up to 4374. This counter counts up from 0 by 1 each time clock 1 is input, counts up to 1194374, then returns to 0, and counts up again. This counter produces a 21-bit output in binary. This output is input to the ROM, which outputs a sine wave (clock 2) during a period of 1194375 clocks (clock 1).
Generate 8 × 10 ³ times. That is, 48 × 10 ³ times of sine wave data (about 25 addresses and 1 cycle of sine wave data) are recorded at 1194375 addresses. As a result, the clock 2 having a different frequency synchronized with the clock 1 is generated.

The variable speed device 5 is constructed when several other pairs of the counter and the ROM as described above are provided. FIG. 2 is a block diagram showing a concrete example of the variable speed device 5 configured as described above.

Referring to FIG. 2, FIG. 2 shows a case in which two more counter-ROM pairs are provided (three in total: counters 51-53 and ROMs 54-55). Block 1 consisting of counter 51 and ROM 54 is 1
The block 2 consisting of the counter 52 and the ROM 54 outputs sine wave 48 × 10 ³ times at 194375 clock, and the sine wave 48 × 1 at block 1194374 clock.
0 ³ times output configurations, the counter 53, block 3 consisting ROM56 is configured to sine wave 1194376 clock is output 48 × 10 ³ times. If the outputs from these three blocks are switched by the switch 57 with the control signal from the write / read data number detection circuit 7,
Sine waves with different frequencies will be output.

Practically, each ROM 5 shown in FIG.
Elements such as a D / A converter and a filter are inserted between the switches 4 to 56 and the switch 57.

Next, the write / read data number difference detection circuit 7 will be described.

Write / read data number difference detection circuit 7
Detects the difference between the number of digital audio data written in the memory 3 in a certain time and the number of digital audio data read from the memory 3 in a certain time, and determines the speed of reading the digital audio data by the difference. This is a circuit that outputs a control signal to the variable speed changer 5 that is changed. Here, the fixed time is generally a time required for 5 fields. The reason for 5 fields is that the number of clocks of the parallel digital video signal and the number of clocks of the digital audio data have the same time relationship. Specifically, it is the time when the clock of the parallel digital video signal is 1194375 clock and the clock of the digital audio data is 8008 clock at the same time. The number of the audio data written in the memory 3 and the number of the audio data read from the memory 3 are compared during this fixed time, and the control signal is output.

Next, a method of comparing the number of voice data written in the memory 3 and the number of voice data read from the memory 3 at a fixed time will be described. Figure 3 is a light /
FIG. 6 is a block diagram showing a peripheral circuit of the read data number difference detection circuit in some detail. The data written in the memory 3 is simultaneously input to the write data counter 4. The write data counter 4 counts up the number of input data by the counter. This counter 4 is reset at a constant time (1194375 clocks in clock 1),
It is a counter that counts up with input data after it reaches 0.

On the other hand, the read data counter 6 counts the clock 2 input from the variable speed device 5. The counter 6 is also reset at a constant time (1194375 clocks for the clock 1), and after reaching 0, is further counted up by the input clock 2.

Next, the difference between the above two counters (write data counter 4 and read data counter 6) is calculated. The upper limit of the number of counts of the above two counters is usually 8007
(The number of counts of 8008 pieces of data including 0) is 0. However, if the number of pieces of data within a certain period of time is 8007 pieces, 0 is output as a control output.

On the other hand, if the two counters have different numbers of counts for a certain period of time, a difference occurs. Specifically, the count number of the write data counter 4 for a certain period of time is 800
7, the read data counter 6 counts 8006
In this case, +1 is output as the control output. On the contrary, the count number of the write data counter 4 for a fixed time is 8006
When the count number of the read data counter 6 is 8007, -1 is output as the control output. This control output is input to the variable speed device 5 to change the speed of the clock 2.

Next, the operation of the embodiment of the present invention will be described with reference to FIG. 1. A digital video signal in which digital audio data is multiplexed is input to a V / A separation circuit 1 and V / A separation circuit 1 is applied. The A separation circuit 1 identifies the flag added to the digital voice data packet and separates the digital composite signal from the digital voice data.
The separated digital audio data is once input to the digital audio data memory 3 and at the same time, is also input to the write data counter 4, and the write data counter 4 counts the number of digital audio data written in a fixed time.

On the other hand, in the read clock generation circuit 2,
A clock for reading digital audio data is generated from the digital composite video signal separated by the V / A separation circuit 1.

Clock generation will now be described. Generally, digital audio data is data sampled at 48 KHz. The digital composite video signal is data obtained by sampling the NTSC signal at 14.3 MHz. Between these two samplings, there is a relationship that the time of 5 fields of the video signal and the time of 4004 digital audio data are the same. However, this relationship is established when the video signal and the audio signal are synchronized. Utilizing this relationship, a read clock is generated from the digital composite video signal.

Next, the read clock is input to the variable speed device 5. In the variable speed device 5, the frequency of the read clock is changed by the control signal from the write / read data number difference detection circuit 7. A method of changing the value will be described.
Normally, 4004 read clocks are generated in 5 fields of the video signal (1194375 clocks).
Now, as an example, the write / read data number difference detection circuit 7
If the control signal from -1 is -1, the video signal 11
It is assumed that 4004 read clocks are generated at 94374 clocks. In this case, the read clock speed (frequency) is increased. Conversely, if the control signal is +1 and if 4004 read clocks are generated at the video signal 1194376 clocks, the read clock speed (frequency) will decrease, and the read speed will change. .

Next, the clock of the variable speed device 5 is input to the digital voice data memory 3, and the digital voice data is read out in accordance with this clock. Further, the clock of the variable speed device 5 is input to the read data counter 6,
The read data counter 6 counts the number of data read from the data memory 3 in a fixed time.

In the write / read data number difference detection circuit 7, the difference between the numbers of data written or read by the write data counter 4 and the read data counter 6 is output to the variable speed device 5 as a control signal. To do.

[0033]

As described above, according to the present invention,
Even if the number of digital audio data multiplexed in the digital conduit video signal is not constant (in the case of audio asynchronous to the video), the data read speed from the data memory 3 depends on the number of transmitted digital audio data. By changing it, it is possible to obtain an effect that the digital audio data to be read can be accurately transmitted without excess or deficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example of a variable speed device that is one of the main parts of the present invention.

FIG. 3 is a block diagram showing the periphery of a write / read data number difference detection circuit which is one of the main parts of the present invention.

FIG. 4 is a block diagram showing an example of a conventional technique.

[Explanation of symbols]

 1, 11 ... V / A separation circuit 2, 12 ... Read clock generation circuit 3, 13 ... Digital voice data memory 4 ... Write data counter 5 ... Variable speed device 51-53 ... Counter 54-56 ... ROM 57 ... Switch 6 ... Read data counter 7 ... Write / read data number difference detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication H04N 7/081

Claims (4)

[Claims] 1. A V / A separation circuit for inputting a digital composite video signal in which asynchronous digital audio data is multiplexed with video and separating the digital audio data and the digital video signal, and an output from the V / A separation circuit. A read clock generation circuit for generating a clock for reading digital audio from the digital video signal, a write data counter for receiving the digital audio data output from the V / A separation circuit and counting the number of the data, and the write data counter. The V from the clock from the data counter
/ A separation circuit for storing the digital audio data output from the A / A separation circuit and outputting the digital audio data with the clock from the read data counter described later, and the write / read data number difference detection described below by receiving the clock from the read clock generation circuit. A variable speed device that varies a clock frequency with a control signal from a circuit, a read data counter that determines a read clock by receiving a clock from the variable speed device, and a difference between clocks from the write data counter and the read data counter And a write / read data number difference detection circuit that outputs a control signal for detecting the read speed and changing the audio read speed. 2. The variable speed device is formed by connecting a plurality of circuits each consisting of a pair of a counter and a ROM in parallel, a common connection point of the counter is connected to an output of the read clock generation circuit, and each of the ROMs is connected. 2. The video / audio multiplex circuit according to claim 1, further comprising: a read / write data counter connected to the read / data counter via a changeover switch controlled by a control signal of the write / read data number difference detection circuit. . 3. The number of audio data written to the memory and the number of audio data read from the memory are counted by the read and write data counter for a certain period of time. The video / audio multiplex circuit described in 1. 4. The image according to claim 3, wherein the fixed time is a time required for 5 fields.
Audio multiplex circuit.