JPH09270538A - Superconducting transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a superconducting transistor which has good controllability in the thickness of a semiconductor channel portion and a sufficiently high mechanical strength and which is suitable for higher integration, and manufacture thereof. SOLUTION: An SOI structure is provided in which an island-like Si single crystal channel portion 14 having a thickness of about 100nm is buried in a recessed form on the surface of an insulating layer 12 on an Si substrate 10 as a holding substrate 10 having a sufficient thickness. On the lower side of the Si single crystal channel portion 14, a gate electrode 18 is formed via a gate insulating film 16. That is, the Si single crystal channel portion 14 and the gate electrode 18 with the gate electrode 16 provided between them are buried in the insulating layer 12 on the Si substrate 10. Also, a superconducting source electrode 22 and a superconducting drain electrode 24 which are connected respectively to the upper side of the Si single crystal channel portion 14 are arranged at a spacing of about 200nm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting transistor and a manufacturing method thereof, and more particularly to a field effect type superconducting transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional superconducting transistor and its manufacturing method will be described with reference to FIG. 10 (edited by Otsuki, Ikushima, Ito, Kawabe, “Forefront of Physics”, Kyoritsu Shuppan, pp.136-13).
9, and T. Nishino, M. Miyake, Y. Harada, and U. Kawabe,
“Three-Terminal Superconducting Device Using a S
i Single-Crystal Film "IEEE Electron Device Letter
s, vol.EDL-6, pp.297-299,1985).

The lower surface of the Si single crystal substrate 30 is partially etched by a wet etching method using a difference in impurity concentration to form a Si single crystal thin film portion having a thickness of about 100 nm, and this thin film portion is formed into a Si single crystal channel. Part 32. Then, by thermal oxidation, a gate oxide film 34 having a thickness of about 40 nm is formed on the lower surface of the Si single crystal substrate 30 including the Si single crystal channel portion 32, and then on the lower surface of the gate oxide film 34, Al is evaporated to a thickness of about 40 nm. An Al gate electrode 36 of 700 nm is formed.

In addition, on the upper surface of the Si single crystal substrate 30, SiO ₂
The film 38 is formed, and Si is formed using the photolithography technique.
After forming an opening in the SiO ₂ film 38 on the single crystal channel portion 32, a superconductor layer is deposited on the entire surface. Subsequently, this superconductor layer is patterned into a predetermined shape, and a superconducting source electrode 40 and a superconducting drain electrode 42 which are respectively connected to the upper surface of the Si single crystal channel portion 32 are formed at intervals of about 200 nm.

In this way, Si having a thickness of about 100 nm is obtained.
An Al gate electrode 36 is provided on the lower surface of the single crystal channel portion 32 via a gate oxide film 34 having a thickness of about 40 nm, and about 200
A superconducting transistor in which the superconducting source electrode 40 and the superconducting drain electrode 42 are provided at intervals of nm is manufactured.

[0006]

However, in the above conventional superconducting transistor, the Si single crystal substrate 3 is used.
Since the Si single crystal channel portion 32 is a portion thinned to a thickness of about 100 nm by partially etching the lower surface of 0, the mechanical strength of this portion in the superconducting transistor was extremely weak.

Further, since the Si single crystal channel portion 32 is formed by thinning it by wet etching, it is difficult to control the channel thickness with high accuracy.

In addition, this superconducting transistor has the same S
When many are formed on the i single crystal substrate 30, an extremely thin S
Since a large number of i single crystal channel portions 32 are formed and an Al gate electrode 36 is formed on the lower surface of the i single crystal channel portions 32 through the gate oxide film 34, the Si single crystal substrate 30 is warped or the mechanical strength is lowered. There is also a problem that it becomes difficult to achieve high integration.

Therefore, the present invention has been made in view of the above problems, and has good controllability of the thickness of the semiconductor channel portion, has sufficiently high mechanical strength, and is suitable for high integration. An object is to provide a superconducting transistor and a method for manufacturing the same.

[0010]

The above object can be achieved by the following superconducting transistor and manufacturing method thereof according to the present invention. That is, the superconducting transistor according to claim 1 includes: (a) a holding substrate; and (b) an island-shaped semiconductor channel portion that is recessed and embedded in a surface of an insulating layer formed on the holding substrate. c) a gate electrode formed on the lower surface of the semiconductor channel portion via a gate insulating film; and (d) first and second superconductors arranged on the upper surface of the semiconductor channel portion with a predetermined distance. And an electrode.

As described above, in the superconducting transistor according to the first aspect, the so-called SOI (Silicon on), in which the entire element region including the semiconductor channel portion is uniformly held by the holding substrate having a sufficient thickness. Insulator)
Due to the structure, the mechanical strength of the superconducting transistor is sufficiently high. Therefore, even when a large number of superconducting transistors are formed on the same substrate, sufficient mechanical strength is maintained and warpage is suppressed, so that high integration can be easily realized.

In the above superconducting transistor, the semiconductor channel portion has an S thickness of about 100 nm.
It is preferably composed of an i single crystal.

In the above superconducting transistor, it is preferable that the holding substrate is a Si substrate.

Further, in the method of manufacturing a superconducting transistor according to a fourth aspect, (a) after forming a convex portion on the surface of the semiconductor single crystal substrate, a gate insulating film is formed on the semiconductor single crystal substrate including the convex portion. A first step of forming, (b) a second step of forming a gate electrode on the convex portion via the gate insulating film, and (c) forming an insulating layer over the entire surface, and then performing the insulation A third step of flattening the layer; (d) a fourth step of attaching a holding substrate on the insulating layer; and (e) an upside down flipping, and the gate insulating film as a stopper. A fifth step of polishing the semiconductor single crystal substrate to leave the convex portion as an island-shaped semiconductor channel portion embedded in the insulating layer surface in a concave shape, and (f) a predetermined surface on the semiconductor channel portion. Forming a first and a second superconductor electrode at a distance And having between step.

As described above, in the method of manufacturing a superconducting transistor according to the fourth aspect, since the semiconductor channel portion is formed by polishing the semiconductor single crystal substrate using the gate insulating film as a stopper, the thickness of the semiconductor channel portion is increased. It is possible to control the height with high precision. Therefore, stable superconducting transistor characteristics can be obtained. Further, when a large number of superconducting transistors are formed on the same substrate, the characteristics of each superconducting transistor are uniform and stable, which is suitable for high integration.

Further, by using the so-called bonding SOI method in which the holding substrate is attached, the element forming portion is held by the holding substrate having this sufficient thickness, so that the mechanical properties of the superconducting transistor are improved. The strength is high enough. Further, even when a large number of superconducting transistors are formed on the same substrate, since each superconducting transistor is uniformly held by the holding substrate having a sufficient thickness,
Sufficient mechanical strength is maintained and warpage is suppressed. Therefore, since normal fine processing can be applied, high integration can be easily realized.

In the above method of manufacturing a superconducting transistor, the semiconductor single crystal substrate is a Si single crystal substrate, the semiconductor channel portion is made of Si single crystal, and the semiconductor channel portion has a thickness of about 100 nm. Yes, it is preferred.

In the above superconducting transistor, it is preferable that the holding substrate is a Si substrate.

[0019]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a sectional view showing a field effect type superconducting transistor according to an embodiment of the present invention. In the field effect type superconducting transistor according to the present embodiment, an insulating layer 12 made of, for example, SiO ₂ is formed on a Si substrate 10 having a sufficient thickness as a holding substrate. An island-shaped Si single crystal channel portion 14 having a thickness of about 100 nm is embedded in the surface in a concave shape. That is, it has an SOI structure.
Then, on the lower surface of the Si single crystal channel portion 14, for example, through the gate insulating film 16 made of SiO ₂ ,
A gate electrode 18 made of 1 or polysilicon is formed. Thus, the entire Si single crystal channel portion 14 and the gate electrode 18 via the gate insulating film 16 are formed by being embedded in the insulating layer 12 on the Si substrate 10.

On the Si single crystal channel portion 14 and the insulating layer 12, for example, SiO ₂ or BPSG (Boro-Pho) is used.
An insulating layer 20 made of spho-Silicate Glass) is formed on the Si single crystal channel portion 14 with a window opened. Then, through this window, the Si single crystal channel portion 14
The superconducting source electrode 22 and the superconducting drain electrode 24, which are respectively connected to the upper surface, are arranged at an interval of about 200 nm, which is similar to the coherent length in the normal conductor. The superconducting source electrode 22 and the superconducting drain electrode 24 may be made of a low temperature superconductor as an electrode material or a high temperature superconductor such as a compound system as an electrode material. Good.

As described above, according to the field effect type superconducting transistor according to the present embodiment, the entire element region including the extremely thin Si single crystal channel portion 14 having a thickness of about 100 nm is maintained with a sufficient thickness. Si substrate 1 as a substrate
Since it has an SOI structure that is uniformly held by 0, the mechanical strength of the superconducting transistor is sufficiently high. In addition, the superconducting transistor is connected to this same Si substrate 1
Even when a large number are formed on the substrate 0, sufficient mechanical strength is maintained and the occurrence of warpage of the Si substrate 10 is suppressed, so that high integration can be easily realized.

Next, the operation of the field effect type superconducting transistor shown in FIG. 1 will be described. From the superconducting source electrode 22 and the superconducting drain electrode 24 to the Si single crystal channel portion 14
A superconducting electron pair oozes out into a quasi-superconducting part.
The spread of the quasi-superconducting portion due to the superconducting adjacency effect is controlled by the gate electrode 18.

That is, when a predetermined voltage is applied to the gate electrode 18, the two quasi-superconducting portions extending from the superconducting source electrode 22 and the superconducting drain electrode 24 intersect and are superconductingly coupled and turned on. The resistance becomes 0Ω, and the superconducting electron pair is transferred from the superconducting source electrode 22 to the superconducting drain electrode 24.
Flows to That is, the superconducting current is turned on. On the other hand, when a predetermined voltage is not applied to the gate electrode 18, the superconducting source electrode 22 and the superconducting drain electrode 24
Since the two quasi-superconducting portions extending from the two do not intersect with each other, they are not superconductingly coupled, and as a result, the superconducting current does not flow and the off-state is obtained.

Thus, by controlling the gate electrode 18,
A switch operation for turning on and off a superconducting current having a resistance of 0Ω can be performed.

Next, a method of manufacturing the field effect type superconducting transistor shown in FIG. 1 will be described with reference to FIGS. 2 to 8 are process cross-sectional views showing a method for manufacturing the field effect type superconducting transistor of FIG.

On the surface of the Si single crystal substrate 14a, the height is about 10
A 0 nm convex portion 14b is formed (see FIG. 2). continue,
By thermal oxidation, for example, SiO ₂ with a thickness of about 10 nm is formed on the entire surface.
A gate insulating film 16 made of is formed (see FIG. 3). Then, after depositing, for example, an Al layer or a polysilicon layer on the gate insulating film 16, it is patterned into a predetermined shape,
A gate electrode 18 made of Al or polysilicon is formed on the convex portion 14b of the Si single crystal substrate 14a via the gate insulating film 16 (see FIG. 4).

Then, for example, SiO ₂ or BPS is applied to the entire surface.
After the insulating layer 20 made of G is formed, the insulating layer 20 is polished and planarized (see FIG. 5). Subsequently, the Si substrate 10 as a holding substrate having a sufficient thickness is attached onto the flattened insulating layer 20. Then, it is turned upside down (see FIG. 6). Subsequently, the Si single crystal substrate 14a is polished using the gate insulating film 16 as a stopper. That is, polishing is performed until the gate insulating film 16 indicated by AA 'in the figure is reached. By polishing the Si single crystal substrate 14a, the protrusions 14
b has a thickness of about 100, which is embedded in the surface of the insulating layer 16 in a concave shape.
Remains as an island-shaped Si single crystal channel portion 14 of nm. Thus, the Si single crystal channel portion 14 and the gate electrode 18 with the gate insulating film 16 interposed therebetween are formed in a state of being embedded in the insulating layer 12 on the Si substrate 10 (see FIG. 7).

Next, after depositing an insulating layer 20 made of, for example, SiO _{2 on} the entire surface, a window 26 is opened on the Si single crystal channel portion 14 by using a photolithography technique (see FIG. 8). Then, after depositing a superconductor layer made of a low-temperature superconductor or a high-temperature superconductor such as a compound system on the entire surface, it is patterned into a predetermined shape, and a Si single crystal channel part is formed at intervals of about 200 nm. 52 superconducting source electrode 22 and superconducting drain electrode 2 respectively connected to the upper surface
4 (see FIG. 9). Thus, the field effect type superconducting transistor shown in FIG. 1 is manufactured.

As described above, according to the method of manufacturing the field effect type superconducting transistor of the present embodiment, the Si single crystal channel portion 14 is formed by polishing the Si single crystal substrate 14a using the gate insulating film 16 as a stopper. To do this S
The thickness of the i single crystal channel portion 14 of about 100 nm can be controlled with high accuracy. Therefore, stable superconducting transistor characteristics can be obtained. Moreover, when a large number of superconducting transistors are formed on the same Si substrate 10, the characteristics of each superconducting transistor can be made uniform and stable, which is suitable for high integration.

Further, by using the bonding SOI method in which the Si substrate 10 as the holding substrate is bonded,
Since the element forming portion is held by the Si substrate 10 having this sufficient thickness, the mechanical strength of the superconducting transistor can be sufficiently increased. Further, even when a large number of superconducting transistors are formed on the same Si substrate 10, each superconducting transistor is uniformly held by the Si substrate 10 having a sufficient thickness to maintain sufficient mechanical strength. Since the occurrence of warpage is also suppressed, ordinary fine processing can be applied, and high integration can be easily realized.

In the method of manufacturing the superconducting transistor according to the above-mentioned embodiment, the Si single crystal channel portion 14 is formed by using the bonding SOI method. Instead of this method, the L-SPE ( Lateral Solid Phase Ep
itaxy; lateral solid phase epitaxial growth) or oxygen doping of the silicon layer, followed by heat treatment SIMOX (Separa
The Si single crystal channel portion 14 may be formed by using the method of Implanted Oxygen), or polysilicon or amorphous silicon in which a polycrystalline silicon layer or an amorphous silicon layer is formed on a silicon oxide layer is used as the channel portion 14. You may use.

[0032]

As described above in detail, according to the superconducting transistor of the present invention, the island-shaped semiconductor channel portion is recessed in the surface of the insulating layer on the holding substrate, and this extremely thin semiconductor channel is formed. Since the entire element region including the portion is held by the holding substrate having a sufficient thickness, the mechanical strength of the superconducting transistor can be sufficiently increased. Therefore, even when a large number of superconducting transistors are formed on the same substrate, sufficient mechanical strength is maintained and warpage is suppressed, so that high integration can be easily realized.

According to the method of manufacturing a superconducting transistor of the present invention, the bonding SOI method is used and the semiconductor channel portion is formed by polishing the semiconductor single crystal substrate using the gate insulating film as a stopper. Thereby, the thickness of the semiconductor channel portion can be controlled with high accuracy. Therefore, stable superconducting transistor characteristics can be obtained. Further, when a large number of superconducting transistors are formed on the same substrate, the characteristics of each superconducting transistor can be made uniform and stable, which is suitable for high integration.

Further, by using the bonding SOI method and holding the element forming portion with the holding substrate having a sufficient thickness, the mechanical strength of the superconducting transistor can be sufficiently increased. Further, even when a large number of superconducting transistors are formed on the same substrate, each superconducting transistor can be uniformly held by a holding substrate having a sufficient thickness, thereby maintaining sufficient mechanical strength, Since the occurrence of warpage is also suppressed, ordinary fine processing can be applied, and high integration can be easily realized.

[Brief description of drawings]

FIG. 1 is a sectional view showing a field effect type superconducting transistor according to an embodiment of the present invention.

2A to 2D are process cross-sectional views (No. 1) showing a method for manufacturing the field effect superconducting transistor of FIG.

3A to 3D are process cross-sectional views (No. 2) showing the method for manufacturing the field-effect superconducting transistor of FIG.

FIG. 4 is a process sectional view (3) showing the method for manufacturing the field effect superconducting transistor of FIG. 1.

5A to 5C are process cross-sectional views (No. 4) showing the method for manufacturing the field-effect superconducting transistor of FIG.

6A to 6C are process cross-sectional views (No. 5) showing the method for manufacturing the field-effect superconducting transistor of FIG.

FIG. 7 is a process sectional view (6) showing the method for manufacturing the field effect superconducting transistor of FIG. 1.

8A to 8C are process cross-sectional views (No. 7) showing the method for manufacturing the field-effect superconducting transistor of FIG.

FIG. 9 is a process sectional view (8) showing the method for manufacturing the field effect type superconducting transistor of FIG. 1.

FIG. 10 is a cross-sectional view illustrating a conventional superconducting transistor and a method for manufacturing the same.

[Explanation of symbols]

10 ... Si substrate, 12 ... Insulating layer, 14 ... Si single crystal channel part, 16 ... Gate insulating film, 18 ... Gate electrode, 20 ... Insulating layer, 22 ... Superconducting source electrode, 2
4 ... Superconducting drain electrode, 26 ... Window, 30 ... Si
Single crystal substrate, 32 ... Si single crystal channel part, 34 ...
Gate oxide film, 36 ... Al gate electrode, 38 ... Si
0 ₂ film, 40 ...... superconducting source electrode, 42 ...... superconducting drain electrode.

Claims (6)

[Claims] 1. A holding substrate, an island-shaped semiconductor channel portion recessed in a surface of an insulating layer formed on the holding substrate, and a lower surface of the semiconductor channel portion formed via a gate insulating film. And a first and a second superconductor electrode which are arranged on the upper surface of the semiconductor channel portion at a predetermined distance from each other, and a superconducting transistor. 2. The superconducting transistor according to claim 1, wherein the semiconductor channel portion is made of a silicon single crystal having a thickness of about 100 nm. 3. The superconducting transistor according to claim 1 or 2, wherein the holding substrate is a silicon substrate. 4. A first step of forming a convex portion on a surface of a semiconductor single crystal substrate, and then forming a gate insulating film on the semiconductor single crystal substrate including the convex portion, and the gate on the convex portion. A second step of forming a gate electrode through an insulating film, a third step of forming an insulating layer on the entire surface and then planarizing the insulating layer, and attaching a holding substrate on the insulating layer Fourth step, and after flipping upside down, the semiconductor single crystal substrate is polished using the gate insulating film as a stopper to form an island-shaped semiconductor channel portion in which the convex portion is embedded in the insulating layer surface in a concave shape. And a first step with a predetermined distance on the upper surface of the semiconductor channel portion.
And a sixth step of forming a second superconducting electrode, and a method for manufacturing a superconducting transistor. 5. The method for manufacturing a superconducting transistor according to claim 4, wherein the semiconductor single crystal substrate is a silicon single crystal substrate, the semiconductor channel portion is made of silicon single crystal, and the semiconductor channel portion has a thickness. Is about 100 nm, The manufacturing method of the superconducting transistor characterized by the above-mentioned. 6. The method of manufacturing a superconducting transistor according to claim 4, wherein the holding substrate is a silicon substrate.