JPH09269760A - Pseudo gradation processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to simultaneously process plural image data by assuming that the image data after change are continued from before the change, forming the error data to be added to the image data after the change and applying them to an operation circuit. SOLUTION: The image data of pixels of odd columns in the horizontal scanning line direction to a latch circuit 13, and the image data of even columns to the latch circuit 14 are serial-parallel converted and applied simultaneously, and the image data of two adjacent pixels are held. The operation circuits 15, 16 add the error data outputted from error control circuits 17, 18 to the image data from the latch circuits 13, 14 respectively. An image discrimination circuit 22 decides image data continuity to discriminate a boundary of an image, and when the boundary exists between the image data applied to the latch circuits 13, 14, it applies a discrimination output to the error control circuit 18, and on the other hand, when the boundary exists between the image data applied to the latch circuit 13 and the image data of a former pixel, it applies the discrimination output to the error control circuit 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo gradation processing device for pseudo display of a gradation number of a predetermined bit or more on a display device for displaying by using image display data of a predetermined bit. In other words, the present invention relates to a pseudo gradation processing device for further increasing the gradation display of an LCD display device by a digital driver of a predetermined bit so as to perform a display close to an original image.

[0002]

2. Description of the Related Art In recent years, a high-definition color LCD display device for OA compatible with multimedia has been developed. This color LCD incorporates a 3-bit or 4-bit digital driver for each of R, G, and B colors. For example,
A color LCD with a 3-bit digital driver
Each color can be displayed in 8 gradations, and 512 colors in total can be displayed. However, this is sufficient when used simply as a monitor for OA, but is insufficient for displaying video such as moving images and still images for multimedia, and further increase in gradation is desired. Was rare.

Therefore, there has been proposed a method of artificially increasing the number of gradations by diffusing a component that cannot be displayed by one pixel into adjacent pixels around the same screen frame (intra-frame error diffusion). In this specification, the term error data means data represented by lower bits of the constituent bits of image data that cannot be displayed by the digital driver of the display device.

For example, when the image data is 8 bits and the displayable bit of the display device is 4 bits, the display data supplied to the display device is the upper 4 bits of the image data, but the lower 4 bits. The error component is held as error data and added to the next image data to diffuse the error component to the next pixel. By repeating such an operation, the error is sequentially diffused and propagated, and the number of gray scales is artificially increased.

However, in the above-described pseudo gradation processing device, the error diffusion process is a horizontal addition process, so that the influence of the image on the left side is transmitted to the image on the right side, and consequently the image display data is affected. become. If the displayed image is moving or the shade changes, this pseudo-gradation process can significantly improve the image quality, but the shade of the displayed image, such as the sky or human face, can be improved. In the case of flatness, the influence of the error data due to the change in the discontinuous image data on the left side appears to the extent that it can be visually recognized, and the display image quality deteriorates.

For example, when a flat background screen is displayed on a personal computer screen and the mouse cursor crawls on the screen, it looks as if the mouse cursor has a tail. That is,
When the mouse cursor is displayed in the light and shade flat image, the error of the image data for displaying the mouse cursor appears on the far right side, and the image changes there.

Further, in a flat image with a light and shade,
Since carry occurs periodically due to addition of error data, the position of a pixel that becomes bright and the position of a pixel that becomes dark are
Since the adjacent horizontal scanning lines are matched with each other and further matched with each other in each frame, vertical lines appear on the display screen, which causes deterioration of image quality. Therefore, the image data of the immediately preceding pixel and the image data of the current pixel are compared, and when the difference is equal to or more than a predetermined value, the contour (edge) of the image, that is, the relationship between the image so far and the future image By determining that there is no such error, the error data accumulated so far is reset to prevent the influence of the previous image from appearing on the next image of different quality.

Further, in a flat image with light and shade,
By resetting the error data for each number of pixels represented by the number of bits of the error data and changing the resetting pixel timing for each horizontal scanning line, in the flat image, every horizontal scanning line is reset. The carry generated by the error data is dispersed, the occurrence of a specific pattern is eliminated, the influence of the error data does not remain, and the image quality of a flat image is improved.

The pseudo gradation processing apparatus having the above-mentioned function is described in detail in Japanese Patent Application No. 6-310817 filed by the present applicant. FIG. 4 is a block diagram for explaining the outline of the above-mentioned pseudo gradation processing device. The device is provided between the output section of the original image data of each color of R, G and B and the LCD driver of each color. It shows one color,
This is a device that processes 8-bit original image data GD and outputs it as 4-bit image display data HD to a 4-bit input LCD driver.

In the pseudo gradation processing device of FIG. 4, the latch circuit 1 is input in synchronization with the dot clock DCK 8
This is a circuit that sequentially holds bit original image data GD.
The arithmetic circuit 2 outputs the image data U output from the latch circuit 1.
It is an 8-bit addition circuit that adds GD and 4-bit error data ED output from the error control circuit 3. Of the 8-bit output image data of the arithmetic circuit 2, the upper 4 bits are held in the latch circuit 4 by the dot clock DCK and supplied as image display data HD to the 4-bit input digital driver of the LCD. On the other hand, the lower 4 bits of the processed image data of the arithmetic circuit 2 are supplied to the latch circuit 5 as error data EN to be added to the image data of the next pixel, and the held error data EN is applied to the error control circuit 3. It The image discrimination circuit 6 receives the applied image data G
This is a circuit for detecting the edge of the image or the pattern of the image by sequentially comparing D, and the signal SEL of the detection result is applied to the error control circuit 3.

The error control circuit 3 outputs the error data EN held in the latch circuit 5 to the arithmetic circuit 2 to perform normal error diffusion processing, and the error data at different pixel positions for each horizontal scanning line. The operation of resetting EN and assuming that the image data after the change is continuous before the change at the boundary of the image, the error data of the lower 4 bits of the image data GD at that time is used for addition. The operation of creating the power error data and applying it to the arithmetic circuit 2 is performed.

FIG. 5 is a block diagram showing a specific configuration of the error control circuit 3. The horizontal counter 7 is a 4-bit counter for obtaining the current horizontal scanning line position in order to change the reset pixel position for each horizontal scanning line, which is reset by the vertical synchronization signal VSYNC and counts the horizontal synchronization signal HSYNC. is there. The decoder 8 outputs a predetermined value according to the count value of the horizontal counter 7. That is, 16 different values for changing the reset pixel position are generated depending on the position of the horizontal scanning line. The value output from the decoder 8 is preset in the dot counter 9 by the horizontal synchronization signal HSYNC.
By the clock signal CLK synchronized with the image data GD,
It is a 4-bit counter that counts up a preset value. Further, the dot counter 9 generates the reset signal RES when each bit output becomes "1", that is, when the count value becomes "15". When the reset signal RES is generated, the reset circuit 10 cuts off the error data EN of the immediately preceding pixel and outputs “0” to the selection circuit 11. That is, when the error data EN becomes “0”,
The diffusion of the error data accumulated so far is reset.

On the other hand, the error creating circuit 12 creates error data to be added to the current image data GD based on the count value of the dot counter 9 and the error data GDE of the current image data GD to be processed. That is, the error data ED to be added is calculated by multiplying the error data GDE by a numerical value obtained by adding “1” to the count value of the dot counter 9. Therefore, even if the calculated error data is different from the image data of the immediately preceding pixel, the current image data G
The error data is obtained assuming that D is continuously applied. The created error data ED is the selection circuit 11
Is applied to The selection circuit 11 is switched and controlled by the signal SEL output from the image discrimination circuit 6, and normally, the error data EN passing through the latch circuit 5 and the reset circuit 10 is selected and output to the arithmetic circuit 2. When the boundary is detected and the signal SEL is output, the error data ED created by the error creating circuit 12 is applied to the arithmetic circuit 2.

Next, the resetting of the error data EN and the creation of the error in FIG. 5 will be described with reference to FIG.
FIG. 6A shows a reset pattern, in which the pixel positions are numbered in the horizontal direction and the line numbers and preset data values are written in the vertical direction. Indicates that it will be done. That is, since the horizontal counter 7 has 4 bits and the dot counter 9 has 4 bits, a repeating pattern is formed in a 16 × 16 pixel area. The error data is reset once every 16 pixels, and the reset positions of the adjacent horizontal scanning lines are shifted by 3 pixels. FIG. 6B
Is the error data E in the reset pattern of (a).
The carry position (position where carry occurs in the upper 4 bits by the arithmetic circuit 2) when N is "8" is indicated by # mark.

For example, by the horizontal synchronizing signal HSYNC,
When the count value of the horizontal counter 7 becomes "1", its decoded output becomes "14", and this numerical value "14" is preset in the dot counter 9. When one clock signal CLK is applied in this state, the count value of the dot counter 9 becomes "15", and the reset signal RES is generated. Therefore, the reset is performed at the pixel position "1". Then, each time the clock signal CLK is applied, the count value of the dot counter 9 is "0, 1, 2, ...
・ ・ 」And count up. Therefore, the count value of the dot counter 9 becomes data indicating the pixel distance from the reset position. For example, the count value of the dot counter 9 at the pixel position “7” is “5”, but assuming that the image data GD of this pixel is continuously applied, it is added to the image data GD of the pixel position “7”. The error data to be processed is a value obtained by multiplying the error data GDE of the image data GD by 6. Therefore, in the error creating circuit 12, the value obtained by adding “1” to the count value of the dot counter 9 and the error data GD
Error data ED to be added by multiplying by E
Is calculated. Therefore, when there is an image boundary between the pixel positions “6” and “7”, the error data ED calculated as if the image data GD was continuously applied before the change at the pixel position “7”. Is added, the carry pattern shown in the column of the pixel position “7” in FIG. 6B is obtained, and the image quality at the boundary portion is improved.

Although a single reset pattern has been described in the above description, a plurality of reset patterns corresponding to the error data GDE of the image data GD are actually prepared. In this case, the decoder 8 and the dot counter 9 are provided by the number of reset patterns, and the output of the dot counter 9 is selected according to the value of the error data DGE. Details are described in Japanese Patent Application No. 6-310817.

[0017]

When the pseudo gradation processing device shown in FIG. 4 is used in a general VGA liquid crystal display device having 640 × 480 pixels, it is synchronized with the image data GD. The frequency of the dot clock DCLK
It becomes almost 25 MHz. However, liquid crystal display devices such as personal computers have become more and more high definition, and are called XGA1.
The number of pixels of 024 × 768 and the number of pixels of 1280 × 1024 have come to be used. When the multi-gradation image processing device of FIG. 4 is used for such a high-definition liquid crystal display device, the dot clock is 70 MHz to 90 MHz.
Therefore, the circuit of FIG. 4 may not operate as an integrated circuit.

[0018]

The present invention has been made in view of the above-mentioned points, and is provided corresponding to a plurality of P-bit image data of consecutive pixels in the horizontal direction. The image data processing circuit includes a plurality of image data processing circuits to which image data are applied simultaneously, and the image data processing circuit corresponds to a unit for outputting the lower PL bits not displayed on the display device as error data, and the immediately preceding pixel. An arithmetic circuit that adds the error data output from the image data processing circuit and the applied image data, and the error data is reset periodically, and the changed image data corresponds to the change of the image data. Create error data to be added to the changed image data assuming that the changed image data was continuous before the change based on the error data An error control circuit for applying the created error data to the arithmetic circuit in place of the error data from the image data processing circuit corresponding to the immediately preceding pixel. Realizes array processing.

According to a second aspect of the present invention, the plurality of image data processing circuits are arranged to perform image data processing for odd-numbered columns to which image data of pixels in horizontally adjacent odd-numbered columns and even-numbered columns are simultaneously applied. It is characterized in that it is a circuit and an image data processing circuit for even columns, which makes it possible to process image data of odd columns and even columns simultaneously. Further, according to a third aspect of the present invention, the error control circuit counts horizontal synchronizing signals in order to change the pixel position for periodically resetting the error data for each horizontal scanning line, and the horizontal counter. An odd column decoder and an even column decoder for specifying the pixel position to be reset based on the count value of the counter, and an odd column pixel counter for obtaining the pixel position of the odd column according to the decode value of the odd column decoder And an even-column pixel counter for obtaining the pixel position of the even-column according to the decoding value of the decoder for the even-column, the pixel positions of the odd-column and the even-column are processed in each image data processing. Required for each circuit.

According to a fourth aspect of the present invention, the odd-column pixel counter and the even-column pixel counter are preset with the decode values of the odd-column decoder and the even-column decoder, respectively, and the preset least significant bit is set. Is fixed, bits other than the least significant bit are added and counted by the clock signal, and each pixel counter can perform counting in 2 pixel steps. The pixel position can be accurately obtained for each circuit.

[0021]

FIG. 1 is a block diagram showing an embodiment of the present invention. The latch circuits 13 and 14 are both 8-bit latch circuits and hold the image data of two adjacent pixels according to the clock signal CLK. Image data GDO of pixels in odd columns in the horizontal scanning line direction is applied to the latch circuit 13, and image data GDE of even columns is applied to the latch circuit 14. Normally, the image data and the dot clock are synchronously provided in serial, but this is serial-parallel converted so that the image data of the odd-numbered columns and the even-numbered columns are simultaneously applied to the latch circuits 13 and 14. ing. This serial-parallel conversion is performed in two stages of eight, which are shift-controlled by a dot clock.
This can be realized by using a bit parallel shift register and latching the outputs of the first and second stages of the shift register when two dot clocks are applied. Therefore, the clock signal CLK that controls the operation of the circuit shown in FIG. 1 is a clock having a frequency half that of the dot clock.

The image data UGDO and UGDE output from the latch circuits 13 and 14 are output to the arithmetic circuits 15 and 16 respectively.
And the lower 4 bits of the outputs of the latch circuits 13 and 14, that is, the error data GDEO and GDE.
E is applied to the error control circuits 17 and 18, respectively. The arithmetic circuits 15 and 16 respectively apply the applied image data U
The display data of the lower 4 bits, that is, the error data, which cannot be displayed in the immediately preceding pixel is added to the GDO and UGDE, and the error data is added. Therefore, the error control circuits 17 and 18 are provided.
The error data EDE and EDO output from are added to the image data GDO and GDE, respectively. Also, the arithmetic circuit 1
When carry is generated as a result of the addition, 5 and 16 output the maximum value represented by 8 bits, that is, "1".
1111111 ”. The upper 4 bits of the outputs of the arithmetic circuits 15 and 16 are display data HDO and H, respectively.
Latched by the latch circuits 19 and 20 as DE, the lower 4 bits are error data ENO and E to the next pixel, respectively.
It is output as NE. In particular, the error data ENE is held in the latch circuit 21, and pixels in odd columns held in the latch circuit 13 at the timing of the next clock signal CLK,
That is, the error data is to be added to the image data of the pixel next to the pixel in the even column processed at this timing.

The image discrimination circuit 22 holds a predetermined number of applied image data GDO and GDE, determines continuity and discontinuity of the image data, and discriminates the boundary of the image. If there is a boundary between the image data applied to the latch circuits 13 and 14, the discrimination output SE
LE is applied to the error control circuit 18, while the latch circuit 1
If there is a boundary between the image data applied to 3 and the image data of the previous pixel, the discrimination output SELO is applied to the error control circuit 17.

In FIG. 1, a latch circuit 13, an arithmetic circuit 15, an error control circuit 17, and a latch circuit 19 constitute an image processing circuit for odd columns, and a latch circuit 14, an arithmetic circuit 16, an error control circuit 18, And the latch circuit 20
An image processing circuit for even columns is configured. Then, the display data HDO that is the output of the image processing circuit for odd columns and the display data HDE that is the output of the image processing circuit for even columns are parallel-
The data is serially converted and supplied to the liquid crystal display device in synchronization with the dot clock.

Further, the error control circuits 17 and 18 shown in FIG. 1 have the same function as the error control circuit 3 shown in FIG.
And ENO to the arithmetic circuits 15 and 16 to perform normal error diffusion processing, an operation of resetting the error data ENE and ENO at different pixel positions for each horizontal scanning line, and a change at the image boundary. Assuming that the subsequent image data is continuous before the change, the lower 4-bit error data G of the image data GDO and GDE at that time
The operation of creating error data to be added using DEO and GDEE and applying it to the arithmetic circuits 15 and 16 is performed.

The error control circuits 17 and 18 are almost the same as the configuration shown in FIG. 5, but the difference is that the decoder 8 and the dot counter 9 are different between the odd column and the even column. . Hereinafter, description will be made with reference to FIG. FIG.
At the horizontal counter 23, the vertical synchronizing signal VSYN
It is a 4-bit binary counter which is reset by C and obtains the horizontal scanning line position of the supplied image data by counting the horizontal synchronizing signal HSYNC.
The horizontal counter 23 is commonly used by the image processing circuit for odd columns and the image processing circuit for even columns. Horizontal counter 2
The count output of 3 is applied to the odd-numbered column decoder 24 provided in the error control circuit of the odd-numbered image processing circuit, and at the same time, for the even-numbered column provided in the error control circuit of the even-numbered image processing circuit. It is applied to the decoder 25.

The odd column decoder 24 and the even column decoder 25 respectively respond to the count value of the horizontal counter 23 in order to change the timing of periodically resetting the error data ENO and ENE according to the horizontal scanning line position. Output a 4-bit value. The latch circuit 26 and the odd column counter 27 constitute a dot counter for the odd column, the least significant bit output of the odd column decoder 24 is applied to the latch circuit 26, and the upper three bits of the odd column decoder 24 are applied.
The bit output is applied to the odd column counter 27. On the other hand, the latch circuit 28 and the even-column counter 29 constitute a dot counter for the even-column, and the least significant bit output of the even-column decoder 25 is applied to the latch circuit 28 to cause the even-column decoder 25 to output. The upper 3 bits output is applied to the even column counter 29. These latch circuits 2
The preset operation of the counter 27 for 6 and odd columns, the latch circuit 28, and the counter 29 for even columns is controlled by the horizontal synchronization signal HSYNC.
The 7 and even column counter 29 counts the clock signal CLK and counts up the preset numerical value.
That is, since the two image data GDO and GDE are supplied in synchronization with the clock signal CLK, the pixel positions of the odd-numbered column and the even-numbered column advance by “2”. for that reason,
The least significant bit remains fixed and the upper 3 bits are counted up by the clock signal CLK. Further, the value output from the even column decoder 25 is a numerical value that is "1" more than the value of the odd column decoder 24.

Latch circuit 26 and odd column counter 27
Outputs OE0, OE1, OE2, and OE3 are applied to the error generation circuit as shown in FIG. 5 as data representing the pixel positions of the odd-numbered column pixels, and are also applied to the AND gate 30. Similarly, the outputs EE0, EE1, EE2, and EE3 of the latch circuit 28 and the counter 29 for even-numbered columns are applied to the error creating circuit as data representing the pixel positions of even-numbered column pixels, and are also applied to the AND gate 31. The AND gates 30 and 31 detect a pixel position for resetting the error data, and when the data indicating the pixel position becomes "1111", the reset signal ORE is set.
The S and ERES are output to the reset circuit 10 shown in FIG.

Next, the operation shown in FIG. 2 will be described with reference to FIG. FIG. 3 shows preset data output from the decoder 24 for odd columns and the decoder 25 for even columns at each horizontal scanning line position in order to generate the same pattern as the reset pattern shown in FIG. 6A. It is a thing. For example, when the count value of the horizontal counter 23 is “1”, the numerical value output from the odd-numbered column decoder 24 is “1”.
3 ”, and the numerical value output from the even-column decoder 25 is“ 14 ”. The clock signal CL with these numerical values preset in the latch circuit 26 and the odd column counter 27, the latch circuit 28 and the even column counter 29.
When K is applied, the outputs of the latch circuit 26 and the odd column counter 27 become “15”, and the AND gate 30 outputs the reset signal ORES. Therefore, the error data ENE is reset in the image processing circuit for odd columns. At this time, the output of the other latch circuit 28 and the even column counter 29 becomes "0". Then, each time the clock signal CLK is applied, each count value is incremented by "2". When there is an image boundary between pixel positions "7" and "8" at the horizontal scanning line position "1", the discrimination output S from the image discrimination circuit 22.
Since ELE is output, the error control circuit 18 of the image processing circuit for even columns adds "1" to the separation distance "6" from the reset position represented by the outputs of the latch circuit 28 and the counter 29 for even columns. Error data GDEE
The error data created by multiplying by is applied to the arithmetic circuit 16. As a result, the output of the image processing circuit for even columns becomes the display data HDE assuming that the image data GDE at that time is continuous.

The count value of the horizontal counter 23 is "2".
When the horizontal scanning line position is "2", the output of the odd-numbered column decoder 24 is "10" and the output of the even-numbered column decoder 25 is "11". These values are preset in the latch circuit 26 and the odd column counter 27, the latch circuit 28 and the even column counter 29 by the horizontal synchronizing signal HSYNC, and then the clock signal C
When two LKs are applied, the outputs of the latch circuit 26 and the odd column counter 27 become "14", and the outputs of the latch circuit 28 and the even column counter 29 become "15". Therefore, in this case, the reset signal ERES is generated from the AND gate 31, and the error data ENO is reset in the odd-column image processing circuit.

Thus, as in the circuit shown in FIG.
By holding the least significant bit of the output of the odd-numbered column decoder 24 and the even-numbered column decoder 25 by the latch circuits 26 and 28, the error data reset timing is correct regardless of whether it is an odd pixel position or an even pixel position. In addition, the distance from the reset pixel position is obtained for each of the supplied odd-numbered and even-numbered image data, and the odd-column image processing circuit and the even-column image processing circuit independently generate an error. The data can be created.

Although FIG. 2 shows an example in which one reset pattern is generated, when a plurality of different reset patterns are generated according to the error data GDEO and GDEE, the odd column decoder 24, Latch circuit 2
6, and odd column counter 27 and even column decoder 2
5, the latch circuit 28, and the counter 29 for even-numbered columns are provided by the number of reset patterns, and the output thereof is the error data G
It may be selected according to DEO and GDEE.

[0033]

As described above, according to the present invention, it is possible to process a plurality of image data at the same time. That is, since the pixel position and the reset position can be accurately grasped in the processing of each image data, even if a plurality of image data are processed at the same time, the reset pattern for periodically resetting the error data can be accurately measured. Can occur in. Further, since the separation distance from the reset position can be grasped in the processing of each image data, when a plurality of image data are processed at the same time, the changed image is continuous regardless of the boundary of the images. Error data can be created as a thing. Therefore, XG with many pixels
A high-speed pseudo-gradation processing device corresponding to a display device such as A can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of some of the blocks shown in FIG.

FIG. 3 is a diagram showing a reset pattern generated by FIG. 2;

FIG. 4 is a block diagram showing a conventional example.

5 is a block diagram showing a configuration of a part of the blocks shown in FIG.

FIG. 6 is a diagram showing a reset pattern and a carry pattern generated by FIGS. 4 and 5;

[Explanation of symbols]

 13, 14 Latch circuit 15, 16 Arithmetic circuit 17, 18 Error control circuit 19, 20, 21 Latch circuit 22 Image discrimination circuit 23 Horizontal counter 24 Odd column decoder 25 Even column decoder 26, 28 Latch circuit 27 Odd column counter 29 Counters for even columns 30, 31 AND gates

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location // G06T 5/00 G06F 15/68 310A

Claims (4)

[Claims] 1. A floor which is applied to a display device in which image display data of each pixel is composed of L bits, and which is displayed by the image display data of L bits, and which is displayed by image data of P bits larger than L bits. In an image processing device for displaying tones on the display device in a pseudo manner, the image processing device is provided corresponding to a plurality of P-bit image data of consecutive pixels in the horizontal direction, and the plurality of image data are applied simultaneously. A plurality of image data processing circuits are provided, and the image data processing circuit is a subordinate P- that is not displayed on the display device.
A means for outputting L bits as error data, an arithmetic circuit for adding the error data output from the image data processing circuit corresponding to the immediately preceding pixel and the applied image data, and the error data is reset periodically. Along with
Error data to be added to the changed image data on the assumption that the changed image data is continuous before the change based on the error data of the changed image data corresponding to the change of the image data. And an error control circuit for applying the created error data to the arithmetic circuit in place of the error data from the image data processing circuit corresponding to the immediately preceding pixel. Processing equipment. 2. The image data processing circuit for an odd number column and the image data processing circuit for an even number column, wherein the plurality of image data processing circuits are simultaneously applied with image data of pixels of adjacent odd number columns and even number columns in the horizontal direction. The pseudo gradation processing device according to claim 1, wherein 3. The error control circuit is based on a horizontal counter that counts a horizontal synchronizing signal and a count value of the horizontal counter in order to change the pixel position for periodically resetting the error data for each horizontal scanning line. An odd column decoder and an even column decoder for specifying the pixel position to be reset, an odd column pixel counter for obtaining the pixel position of the odd column according to the decoding value of the odd column decoder, and the even column 3. The pseudo gradation processing device according to claim 2, further comprising a pixel counter for an even column for obtaining a pixel position of an even column according to a decode value of the decoder. 4. The odd-column pixel counter and the even-column pixel counter are preset with the decoding values of the odd-column decoder and the even-column decoder, respectively, and the preset least significant bit is fixed, 4. The pseudo gradation processing device according to claim 3, wherein bits other than the least significant bit are added and counted by the clock signal.