JPH09266352A - Semiconductor light emitting device - Google Patents
Semiconductor light emitting deviceInfo
- Publication number
- JPH09266352A JPH09266352A JP7422196A JP7422196A JPH09266352A JP H09266352 A JPH09266352 A JP H09266352A JP 7422196 A JP7422196 A JP 7422196A JP 7422196 A JP7422196 A JP 7422196A JP H09266352 A JPH09266352 A JP H09266352A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- cap layer
- gan
- light emitting
- type
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
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- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Abstract
(57)【要約】
【課題】 半導体発光素子においてインピーダンスを低
減する。
【解決手段】 サファイア基板1上にn-GaN低温バッフ
ァ層2、n-GaNバッファ層3、n-InGaN バッファ層4、n
-AlGaN クラッド層5、n-GaN 光ガイド層6、活性層
7、p-GaN 光ガイド層8、一部にリッジストライプ部を
有するp-AlGaN クラッド層9、リッジストライプ状のp-
GaN 下部キャップ層10が積層され、p-AlGaNクラッド層
9のリッジストライプ以外の部分に、SiN 膜11を製膜す
る。さらに、p-GaN 上部キャップ層12をSiN 膜11上およ
びp-GaN 下部キャップ層10上に成長した後、塩素イオン
を用いたRIBEにより発光領域を含む部分以外のエピ
タキシャル層をn-GaN バッファ層3が露出するまでエッ
チング除去する。この後、n-GaN バッファ層3上にTi/A
l/Ti/Au n側電極14を、また、上部キャップ層12上にNi
/Au p側電極13を真空蒸着・窒素中アニールしてオーミ
ック電極を形成する。
(57) Abstract: Impedance is reduced in a semiconductor light emitting device. An n-GaN low temperature buffer layer 2, an n-GaN buffer layer 3, an n-InGaN buffer layer 4, n are formed on a sapphire substrate 1.
-AlGaN clad layer 5, n-GaN light guide layer 6, active layer 7, p-GaN light guide layer 8, p-AlGaN clad layer 9 partially having a ridge stripe portion, ridge stripe p-
A GaN lower cap layer 10 is laminated, and a SiN film 11 is formed on a portion of the p-AlGaN cladding layer 9 other than the ridge stripe. Further, after growing the p-GaN upper cap layer 12 on the SiN film 11 and the p-GaN lower cap layer 10, the epitaxial layer other than the portion including the light emitting region is formed by n-GaN buffer layer by RIBE using chlorine ions. Etch away until 3 is exposed. After this, Ti / A is deposited on the n-GaN buffer layer 3.
l / Ti / Au n-side electrode 14 and Ni on top cap layer 12
/ Au p side electrode 13 is vacuum-deposited and annealed in nitrogen to form an ohmic electrode.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体発光素子の
構造関し、特に詳しくは、発光ダイオード(LED)お
よび半導体レーザを含む半導体発光素子にに関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor light emitting device, and more particularly to a semiconductor light emitting device including a light emitting diode (LED) and a semiconductor laser.
【0002】[0002]
【従来の技術】従来より、500nm を切る短波長光源とし
てAlInGaN系のLEDおよび半導体レーザが注目されて
いる。本材料は青・緑の波長領域の高輝度LEDとして
極めて優れた特性を有し(文献(1)Jpn.J.Appl.Phys.
vol.34,No.7A,pp.L797-799(1995))、信号機や屋外表示
装置の光源として実用化が進められている。また、半導
体レーザとしては、最近室温で417nm のパルス発振が報
告された(文献(2)Jpn.J.App1.Phys.vol35, No.1B,p
p.L74-76(1996))。2. Description of the Related Art AlInGaN-based LEDs and semiconductor lasers have hitherto attracted attention as short-wavelength light sources below 500 nm. This material has extremely excellent characteristics as a high-intensity LED in the blue / green wavelength range (Reference (1) Jpn.J.Appl.Phys.
vol.34, No.7A, pp.L797-799 (1995)), is being put to practical use as a light source for traffic lights and outdoor display devices. As a semiconductor laser, a pulse oscillation of 417 nm has recently been reported at room temperature (Reference (2) Jpn.J.App1.Phys.vol35, No.1B, p).
p.L74-76 (1996)).
【0003】上記文献(2)記載のAlInGaN 系半導体レ
ーザでは、p型半導体層と電極との接触抵抗が非常に高
いため、パルス駆動時の動作電圧が数十ボルトと高くな
り、発振時に素子に投入される電力は通常の素子より10
倍程度高くなるため、素子の発熱や、変調時の歪みが大
きくなるという欠点がある。そこで、素子のインピーダ
ンスの低減が課題とされている。In the AlInGaN type semiconductor laser described in the above-mentioned document (2), since the contact resistance between the p-type semiconductor layer and the electrode is very high, the operating voltage during pulse driving becomes as high as several tens of volts, and the element is oscillated during oscillation. The power input is 10 compared to normal devices
Since it is about twice as high, there is a drawback that the element heats up and distortion during modulation increases. Therefore, reduction of the impedance of the element has been an issue.
【0004】また、上記AlInGaN 系半導体レーザの応用
としては短波長化により現在実現されている630nm 半導
体レーザより格段に小さい径の光スポットが得られるこ
とから、光ディスクメモリの高密度化への応用が最も期
待される。このためには、安定な光ビームが得られる単
一モードレーザの実現が必須であり、AlInGaN 系で期待
される360-500nm の短波長域では横モード安定化のため
の作りつけの光導波路のストライプ幅は2μm程度かそれ
以下の狭ストライプであることが必要となる。Further, as an application of the above AlInGaN type semiconductor laser, since a light spot having a diameter much smaller than that of the 630 nm semiconductor laser which is currently realized can be obtained by shortening the wavelength, it is applicable to high density optical disk memory. Most expected. For this purpose, it is essential to realize a single-mode laser that can obtain a stable light beam, and in the short wavelength range of 360-500 nm expected for AlInGaN system, a built-in optical waveguide for transverse mode stabilization is required. The stripe width needs to be a narrow stripe of about 2 μm or less.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記文
献に示される従来構造の素子においては、基板上にn型
半導体層を先に積層した後にp型半導体層を積層して作
製する構成をとっており、狭ストライプを設ける場合、
p型半導体層とp側電極との接触面積が狭められ、さら
にインピーダンスを増加させることとなる。However, in the device having the conventional structure disclosed in the above document, the n-type semiconductor layer is first laminated on the substrate and then the p-type semiconductor layer is laminated. If a narrow stripe is provided,
The contact area between the p-type semiconductor layer and the p-side electrode is narrowed, and the impedance is further increased.
【0006】このように、p型半導体層の抵抗率が大き
く、p側電極との接触抵抗が大きい半導体発光素子にお
いて、素子のインピーダンスを低減することが望まれて
いる。As described above, in a semiconductor light emitting device in which the p-type semiconductor layer has a large resistivity and the contact resistance with the p-side electrode is large, it is desired to reduce the impedance of the device.
【0007】本発明は、上記事情を鑑みてなされたもの
であり、インピーダンスを低減した半導体発光素子を提
供することを目的とするものである。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor light emitting device having a reduced impedance.
【0008】[0008]
【課題を解決するための手段】本発明の半導体発光素子
は、基板上に、少なくともn型クラッド層、活性層、p
型クラッド層の各半導体層がこの順に積層され、前記p
型クラッド層の一部に発光領域を定めるストライプ部が
形成され、前記ストライプ部上にp型キャップ層を形成
され、該p型キャップ層上にp側電極が形成されている
半導体発光素子において、前記p型キャップ層が、前記
ストライプ部上に積層されたストライプ状の下部キャッ
プ層と、前記下部キャップ層上に形成された該下部キャ
ップ層よりも広い面積を有する上部キャップ層とからな
り、前記p側電極と前記p型上部キャップ層との接触面
積が、下部キャップ層と上部キャップ層との接触面積よ
りも広いことを特徴とするものである。A semiconductor light emitting device of the present invention comprises a substrate, at least an n-type clad layer, an active layer, and a p-type layer.
The semiconductor layers of the mold clad layer are laminated in this order,
In a semiconductor light emitting device, a stripe portion that defines a light emitting region is formed in a part of the mold cladding layer, a p-type cap layer is formed on the stripe portion, and a p-side electrode is formed on the p-type cap layer. The p-type cap layer includes a stripe-shaped lower cap layer stacked on the stripe portion and an upper cap layer formed on the lower cap layer and having an area larger than that of the lower cap layer. The contact area between the p-side electrode and the p-type upper cap layer is larger than the contact area between the lower cap layer and the upper cap layer.
【0009】すなわち、本発明は、電極との接触抵抗の
大きいp型半導体層とp側電極との接触面積を広くとる
ことにより、素子のインピーダンスを低減するものであ
る。That is, the present invention reduces the impedance of the element by increasing the contact area between the p-type semiconductor layer having a large contact resistance with the electrode and the p-side electrode.
【0010】前記上部キャップ層が、前記下部キャップ
層上に積層されている部分と前記下部キャップ層上から
張り出した張出部とからなっていてもよい。The upper cap layer may include a portion laminated on the lower cap layer and an overhang portion protruding from the lower cap layer.
【0011】また、前記張出部が、前記p型クラッド層
上の前記ストライプ部を除いた部分上に形成された絶縁
膜上に形成されていてもよい。Further, the projecting portion may be formed on an insulating film formed on a portion of the p-type clad layer excluding the stripe portion.
【0012】上記構造は、AlxInyGa1-x-yN(0≦x、y≦
1)系の半導体発光素子に用いることができる。The above structure has Al x In y Ga 1-xy N (0≤x, y≤
It can be used for 1) type semiconductor light emitting devices.
【0013】[0013]
【発明の効果】本発明の半導体発光素子は、p型半導体
層とp側電極との接触面積を広くとることにより、従来
の素子構造の場合と比較してインピーダンスを低減する
ことができ、この結果、動作電圧を低減でき、横モード
の安定した半導体発光素子を提供することができる。According to the semiconductor light emitting device of the present invention, by increasing the contact area between the p-type semiconductor layer and the p-side electrode, the impedance can be reduced as compared with the conventional device structure. As a result, the operating voltage can be reduced, and a semiconductor light emitting device having a stable transverse mode can be provided.
【0014】従って、これらの光源を用いた印刷・写真
・医療画像などのハードコピー出力システムの高速化・
高品位化、あるいは高密度の光メモリの高性能化を実現
することができる。Therefore, the speedup of the hard copy output system for printing, photographs, medical images, etc., using these light sources,
Higher quality or higher performance of high-density optical memory can be realized.
【0015】[0015]
【発明の実施の形態】以下に図面を用いて本発明の半導
体発光素子の実施の形態を説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor light emitting device of the present invention will be described below with reference to the drawings.
【0016】図1は本発明に係る第一の実施の形態の半
導体レーザ断面模式図を示す。サファイアc面基板1上
にMOCVD法を用いて、n-GaN低温バッファ層2、n-G
aNバッファ層3(Siドープ、5μm )、n-In0.1Ga0.9N
バッファ層4(Siドープ、0.1μm )、n-Al0.15Ga0.85N
クラッド層5(Siドープ、0.5μm)、n-GaN光ガイド層
6(Siドープ、0.1μm)、アンドープ活性層7、p-GaN
光ガイド層8(Mgドープ、0.1μm )、p-Al0.15Ga0.85N
クラッド層9(Mgドープ、0.5μm)およびp-GaN下部キ
ャップ層10(Mgドープ、0.2μm)を成長する。活性層7
は、アンドープAl0.04Ga0.96N 障壁層(0.01μm)、ア
ンドープIn0.2Ga0.8N量子井戸層(3nm)およびアンド
ープAl0.04Ga0.96N障壁層(0.01μm)の3層構造とす
る。FIG. 1 is a schematic sectional view of a semiconductor laser according to the first embodiment of the present invention. N-GaN low temperature buffer layer 2, nG is formed on the sapphire c-plane substrate 1 by MOCVD method.
aN buffer layer 3 (Si-doped, 5 μm), n-In 0.1 Ga 0.9 N
Buffer layer 4 (Si-doped, 0.1 μm), n-Al 0.15 Ga 0.85 N
Cladding layer 5 (Si-doped, 0.5 μm), n-GaN optical guide layer 6 (Si-doped, 0.1 μm), undoped active layer 7, p-GaN
Optical guide layer 8 (Mg-doped, 0.1 μm), p-Al 0.15 Ga 0.85 N
A clad layer 9 (Mg-doped, 0.5 μm) and a p-GaN lower cap layer 10 (Mg-doped, 0.2 μm) are grown. Active layer 7
Is a three-layer structure of an undoped Al 0.04 Ga 0.96 N barrier layer (0.01 μm), an undoped In 0.2 Ga 0.8 N quantum well layer (3 nm) and an undoped Al 0.04 Ga 0.96 N barrier layer (0.01 μm).
【0017】次にフォトリソグラフィとエッチングによ
り幅2.2μm程度のリッジストライプをp-Al0.15Ga0.85N
クラッド層9の残し厚が0.1μmとなるようにして形成す
る。Next, a ridge stripe having a width of about 2.2 μm is formed by p-Al 0.15 Ga 0.85 N by photolithography and etching.
The clad layer 9 is formed so that the remaining thickness is 0.1 μm.
【0018】次にSiN 膜11をプラズマCVDで全面に製
膜した後、フォトリソグラフィとエッチングによりリッ
ジ上の不要部分を除去する。Next, a SiN film 11 is formed on the entire surface by plasma CVD, and then unnecessary portions on the ridge are removed by photolithography and etching.
【0019】この後、2回目のMOCVD成長によりp-
GaN上部キャップ層12(Mgドープ)を成長する。その
後、窒素ガス雰囲気中で熱処理によりp型不純物を活性
化する。Thereafter, p- is formed by the second MOCVD growth.
A GaN upper cap layer 12 (Mg-doped) is grown. Then, the p-type impurities are activated by heat treatment in a nitrogen gas atmosphere.
【0020】この後、塩素イオンを用いたRIBE(rea
ctive ion beam etching )により発光領域を含む部分以
外のエピタキシャル層をn-GaN バッファ層3が露出する
までエッチング除去する。この際にレーザの共振器端面
をエッチングにより形成することが可能であるが、その
場合は端面に相当する部分でリッジ幅を10μm 程度以上
に広げてリッジ部形状の端面の平坦性へ及ぼす悪影響を
低減することが望ましい(J.Quantum Electronics vol.
27,pp.1319-1331(1991))。劈開により共振器端面を形成
する場合は端面のリッジ幅を拡げる必要はない。After this, RIBE (rea
The epitaxial layer other than the portion including the light emitting region is etched away by ctive ion beam etching) until the n-GaN buffer layer 3 is exposed. At this time, it is possible to form the laser cavity end face by etching, but in that case, the ridge width is expanded to 10 μm or more at the part corresponding to the end face, and there is no adverse effect on the flatness of the ridge shape end face. It is desirable to reduce the amount (J. Quantum Electronics vol.
27, pp. 1319-1331 (1991)). When forming the resonator end face by cleavage, it is not necessary to widen the ridge width of the end face.
【0021】この後、n-GaN バッファ層3上にn側電極
14としてTi/Al/Ti/Auを、また、上部キャップ層12上に
p側電極13としてNi/Auを真空蒸着・窒素中アニールし
てオーミック電極を形成する。After that, an n-side electrode is formed on the n-GaN buffer layer 3.
Ti / Al / Ti / Au as 14 and Ni / Au as the p-side electrode 13 on the upper cap layer 12 are vacuum deposited and annealed in nitrogen to form an ohmic electrode.
【0022】上記実施の形態では基板として絶縁性物質
であるサファイアを用いているが、SiC のような導電性
の基板101 を用いて図2に示す第二の実施形態に係る半
導体レーザを作成することも可能である。この場合、n-
GaN バッファ層3をエッチングにより露出させる必要は
なく、基板101 下面にn側電極を形成する。Although sapphire, which is an insulating material, is used as the substrate in the above-described embodiment, a semiconductor laser according to the second embodiment shown in FIG. 2 is produced using a conductive substrate 101 such as SiC. It is also possible. In this case, n-
It is not necessary to expose the GaN buffer layer 3 by etching, and the n-side electrode is formed on the lower surface of the substrate 101.
【0023】本発明に係る第三の実施の形態の半導体レ
ーザ断面模式図を図3に示す。基板の種類を含む活性層
以下の構造は種々の構造が採用できるため、図1に示す
前記第一の実施の形態と同様の構成とし、p-GaN 光ガイ
ド層8より上部の構造のみを示す。本実施の形態では、
2回目のMOCVD成長において、絶縁膜211 上に積層
しにくい選択成長を用いてp-GaN下部キャップ層10上にp
-GaN上部キャップ層212 を選択的に成長してp側電極21
3 との接触面積を大きくとった。FIG. 3 shows a schematic sectional view of a semiconductor laser according to a third embodiment of the present invention. Various structures can be adopted for the structure below the active layer including the type of substrate. Therefore, the structure is the same as that of the first embodiment shown in FIG. 1, and only the structure above the p-GaN optical guide layer 8 is shown. . In this embodiment,
In the second MOCVD growth, the p-GaN lower cap layer 10 is p-doped on the p-GaN lower cap layer 10 by selective growth that is difficult to stack on the insulating film 211.
-The GaN upper cap layer 212 is selectively grown to form the p-side electrode 21.
The contact area with 3 was increased.
【0024】本発明の第四の実施の形態の半導体レーザ
断面模式図を図4に示す。リッジ導波路型の横モード制
御は前記の実施の形態と同様であるが、リッジの両側を
5μm 程度の幅の溝形状314 にエッチングして、SiO2絶
縁膜311 は塗布型の影両のスピンコートと熱処理を用い
て形成し、溝部314 を埋め込む形とした。この上に図
1、図2の実施の形態と同様にp-GaN 上部キャップ層31
2 を成長してp側電極313 との接触面積を大きくとっ
た。図4の実施の形態の構造について、SiO2絶縁膜を超
音波を加えながらのウエットエッチングにより除去し
て、この際に結晶性のよくないGaN 下部キャップ層310
上近傍のエピタキシャル層以外の部分をリフトオフ除去
して図5に示す第五の実施の形態の半導体レーザを作成
してもよい。A schematic sectional view of a semiconductor laser according to the fourth embodiment of the present invention is shown in FIG. The ridge waveguide type lateral mode control is the same as that of the above-described embodiment, except that both sides of the ridge are etched into a groove shape 314 having a width of about 5 μm, and the SiO 2 insulating film 311 is formed into a coating type shadow spin layer. It was formed by using a coat and heat treatment, and had a shape in which the groove 314 was embedded. On top of this, the p-GaN upper cap layer 31 is formed similarly to the embodiment of FIGS.
2 was grown to increase the contact area with the p-side electrode 313. In the structure of the embodiment of FIG. 4, the SiO 2 insulating film is removed by wet etching while applying ultrasonic waves, and at this time, the GaN lower cap layer 310 having poor crystallinity is used.
The semiconductor laser of the fifth embodiment shown in FIG. 5 may be produced by removing the portion other than the epitaxial layer near the upper portion by lift-off.
【0025】本発明の効果はリッジ形成、絶縁膜層形成
および2回目のGaN 上部キャップ層の成長により得られ
るものである。従って、半導体レーザの層構造としては
上記実施の形態以外に多重井戸構造や量子井戸を用いな
いダブルヘテロ構造など一般に考えられる種々の構造を
採用することが可能である。基板としてサファイアやSi
C 以外にスピネル構造を有す物質(例えば、AlMg2O4 )
等任意のものを用いることができる。The effect of the present invention is obtained by forming a ridge, forming an insulating film layer, and growing the GaN upper cap layer for the second time. Therefore, as the layer structure of the semiconductor laser, various generally conceivable structures such as a multiple well structure and a double hetero structure not using quantum wells can be adopted in addition to the above-described embodiment. Sapphire or Si as substrate
Substances with a spinel structure other than C (eg AlMg 2 O 4 )
Etc. can be used.
【0026】前記実施例においては、レーザ端面を塩素
イオンを用いたRlBEにより形成したが、通常の劈開
や光学研磨法などを用いて形成してもかまわない。In the above-mentioned embodiment, the laser end face is formed by RlBE using chlorine ions, but it may be formed by a usual cleavage or optical polishing method.
【0027】以上半導体レーザ素子として述べたが、同
様の構造で端面発光型LEDとして用いる場合にも効果
があることは言うまでもない。Although the semiconductor laser device has been described above, it is needless to say that it is also effective when it is used as an edge emitting LED with the same structure.
【0028】また、本発明の構造は、基板上にn型半導
体層から形成し、電流注入窓側がp型半導体層とした半
導体発光素子であって、p型半導体層の抵抗率および電
極との接触抵抗率の高い物質の場合にはいかなる組成の
半導体発光素子においても有効である。Further, the structure of the present invention is a semiconductor light emitting device which is formed from an n-type semiconductor layer on a substrate and has a p-type semiconductor layer on the side of the current injection window, and the resistivity of the p-type semiconductor layer and the electrode A material having a high contact resistivity is effective in a semiconductor light emitting device having any composition.
【図1】本発明の第一の実施の形態に係る半導体レーザ
の断面模式図FIG. 1 is a schematic sectional view of a semiconductor laser according to a first embodiment of the present invention.
【図2】本発明の第二の実施の形態に係る半導体レーザ
の断面模式図FIG. 2 is a schematic sectional view of a semiconductor laser according to a second embodiment of the present invention.
【図3】本発明の第三の実施の形態に係る半導体レーザ
の断面模式図FIG. 3 is a schematic sectional view of a semiconductor laser according to a third embodiment of the present invention.
【図4】本発明の第四の実施の形態に係る半導体レーザ
の断面模式図FIG. 4 is a schematic sectional view of a semiconductor laser according to a fourth embodiment of the present invention.
【図5】本発明の第五の実施の形態に係る半導体レーザ
の断面模式図FIG. 5 is a schematic sectional view of a semiconductor laser according to a fifth embodiment of the present invention.
1 サファイアc面基板 2 n-GaN低温バッファ層 3 n-GaNバッファ層 4 n-In0.1Ga0.9Nバッファ層 5 n-Al0.15Ga0.85Nクラッド層 6 n-GaN光ガイド層 7 アンドープ活性層 8 p-GaN光ガイド層 9 p-Al0.15Ga0.85Nクラッド層 10 p-GaN下部キャップ層 11 SiN膜 12 p-GaN光ガイド層 13,14 電極1 Sapphire c-plane substrate 2 n-GaN low temperature buffer layer 3 n-GaN buffer layer 4 n-In 0.1 Ga 0.9 N buffer layer 5 n-Al 0.15 Ga 0.85 N clad layer 6 n-GaN optical guide layer 7 undoped active layer 8 p-GaN optical guide layer 9 p-Al 0.15 Ga 0.85 N clad layer 10 p-GaN lower cap layer 11 SiN film 12 p-GaN optical guide layer 13,14 Electrode
Claims (4)
活性層、p型クラッド層の各半導体層がこの順に積層さ
れ、前記p型クラッド層の一部に発光領域を定めるスト
ライプ部が形成され、前記ストライプ部上にp型キャッ
プ層を形成され、該p型キャップ層上にp側電極が形成
されている半導体発光素子において、 前記p型キャップ層が、前記ストライプ部上に積層され
たストライプ状の下部キャップ層と、前記下部キャップ
層上に形成された該下部キャップ層よりも広い面積を有
する上部キャップ層とからなり、前記p側電極と前記p
型上部キャップ層との接触面積が、下部キャップ層と上
部キャップ層との接触面積よりも広いことを特徴とする
半導体発光素子。1. A substrate having at least an n-type cladding layer,
The semiconductor layers of the active layer and the p-type clad layer are laminated in this order, a stripe portion that defines a light emitting region is formed in a part of the p-type clad layer, and a p-type cap layer is formed on the stripe portion. In a semiconductor light emitting device having a p-side electrode formed on a p-type cap layer, the p-type cap layer is formed on a stripe-shaped lower cap layer laminated on the stripe portion, and on the lower cap layer. And an upper cap layer having an area larger than that of the lower cap layer, the p-side electrode and the p-side electrode.
A semiconductor light emitting device, wherein a contact area with the upper mold cap layer is larger than a contact area between a lower cap layer and an upper cap layer.
プ層上に積層されている部分と前記下部キャップ層上か
ら張り出した張出部とからなることを特徴とする請求項
1記載の半導体発光素子。2. The semiconductor light emitting device according to claim 1, wherein the upper cap layer includes a portion laminated on the lower cap layer and an overhang portion protruding from the lower cap layer. .
記ストライプ部を除いた部分上に形成された絶縁膜上に
形成されていることを特徴とする請求項1または2記載
の半導体発光素子。3. The semiconductor according to claim 1, wherein the projecting portion is formed on an insulating film formed on a portion of the p-type clad layer excluding the stripe portion. Light emitting element.
ッド層およびp型キャップ層がAlxInyGa1-x-yN(0≦x、
y≦1)系の半導体層であることを特徴とする請求項1か
ら3いずれか記載の半導体発光素子。4. The n-type cladding layer, the active layer, the p-type cladding layer and the p-type cap layer are made of Al x In y Ga 1-xy N (0 ≦ x,
4. The semiconductor light emitting device according to claim 1, wherein the semiconductor layer is a y ≦ 1) type semiconductor layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7422196A JPH09266352A (en) | 1996-03-28 | 1996-03-28 | Semiconductor light emitting device |
| US08/827,252 US6072818A (en) | 1996-03-28 | 1997-03-28 | Semiconductor light emission device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7422196A JPH09266352A (en) | 1996-03-28 | 1996-03-28 | Semiconductor light emitting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09266352A true JPH09266352A (en) | 1997-10-07 |
Family
ID=13540926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7422196A Pending JPH09266352A (en) | 1996-03-28 | 1996-03-28 | Semiconductor light emitting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09266352A (en) |
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| US6169296B1 (en) | 1997-10-27 | 2001-01-02 | Matsushita Electric Industrial Co., Ltd. | Light-emitting diode device |
| US6400742B1 (en) * | 1996-09-09 | 2002-06-04 | Kabushiki Kaisha Toshiba | Semiconductor laser and method of fabricating same |
| US6456640B1 (en) * | 1998-01-26 | 2002-09-24 | Sharp Kabushiki Kaisha | Gallium nitride type semiconductor laser device |
| EP1047163A3 (en) * | 1999-04-23 | 2004-02-25 | Sony Corporation | Semiconductor laser, manufacturing method thereof, semiconductor device and manufacturing method thereof |
| US6744800B1 (en) * | 1998-12-30 | 2004-06-01 | Xerox Corporation | Method and structure for nitride based laser diode arrays on an insulating substrate |
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| WO2005086244A1 (en) * | 2004-03-05 | 2005-09-15 | Epivalley Co., Ltd. | Iii -nitride semiconductor light emitting device |
| US7015053B2 (en) | 1999-03-04 | 2006-03-21 | Nichia Corporation | Nitride semiconductor laser device |
| US7352008B2 (en) * | 2000-06-02 | 2008-04-01 | Microgan Gmbh | Heterostructure with rear-face donor doping |
| US7629623B2 (en) | 2002-03-26 | 2009-12-08 | Sanyo Electric Co., Ltd. | Nitride-based semiconductor device and method of fabricating the same |
| USRE42074E1 (en) | 1996-04-26 | 2011-01-25 | Sanyo Electric Co., Ltd. | Manufacturing method of light emitting device |
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-
1996
- 1996-03-28 JP JP7422196A patent/JPH09266352A/en active Pending
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| US6400742B1 (en) * | 1996-09-09 | 2002-06-04 | Kabushiki Kaisha Toshiba | Semiconductor laser and method of fabricating same |
| JPH10294533A (en) * | 1997-02-21 | 1998-11-04 | Toshiba Corp | Nitride compound semiconductor laser and method of manufacturing the same |
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| US7015565B2 (en) | 1998-01-26 | 2006-03-21 | Sharp Kabushiki Kaisha | Gallium nitride type semiconductor laser device |
| US6456640B1 (en) * | 1998-01-26 | 2002-09-24 | Sharp Kabushiki Kaisha | Gallium nitride type semiconductor laser device |
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| US7496124B2 (en) | 1999-03-04 | 2009-02-24 | Nichia Corporation | Nitride semiconductor laser device |
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| US7352008B2 (en) * | 2000-06-02 | 2008-04-01 | Microgan Gmbh | Heterostructure with rear-face donor doping |
| US7655484B2 (en) * | 2002-03-26 | 2010-02-02 | Sanyo Electric Co., Ltd. | Nitride-based semiconductor device and method of fabricating the same |
| US7629623B2 (en) | 2002-03-26 | 2009-12-08 | Sanyo Electric Co., Ltd. | Nitride-based semiconductor device and method of fabricating the same |
| KR100489039B1 (en) * | 2002-08-19 | 2005-05-11 | 엘지이노텍 주식회사 | Fabrication method for GaN semiconductor LED |
| WO2005086244A1 (en) * | 2004-03-05 | 2005-09-15 | Epivalley Co., Ltd. | Iii -nitride semiconductor light emitting device |
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