JPH09266253A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability upon the part in lower writing-in voltage in the state before writing-in a high resistance thin film layer by reducing the dispersion in the writing-in voltage induced by the underneath stepped part shape, in a non-volatile semiconductor memory using an anti-fuse. SOLUTION: This device is composed of an insulator layer 102 provided at least on a substrate 101, a lower part metallic wiring 103 on the insulator layer 102, insulating layers 104, 106 insulating the lower metallic wiring 103 and upper part metallic wirings 105, 109, a connecting hole 7 connecting the upper and lower part metallic wirings formed by isotropic etching step, a high resistant a-Si layer 108 formed in the connecting hole 107 and the upper part metallic wirings 105, 109. In such a constitution, the connecting part of on the connecting hole bottom can be minimized by forming the connecting hole using the isotropic etching step thereby enabling the writing-in part onto the high resistance a-Si layer to be limited.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art There is a device using an antifuse as a nonvolatile semiconductor memory device. FIG. 2 is a cross-sectional view of a conventional semiconductor device having an anti-fuse using a-Si formed between metal wirings. The structure of a semiconductor device having an antifuse according to the related art will be described below with reference to FIG. 201 is a substrate, for example, a silicon substrate is used. 202 is a first insulating layer. Reference numeral 205 is a second metal wiring, and 206 is a second insulating layer 206. The connection hole 207 is formed by a combination of conventional wet etching and dry etching methods. In order to increase the degree of freedom in circuit design, it is desirable that the connection hole 207 be formed on the second metal wiring 205 regardless of the step difference between the element isolation region 202 and the gate electrode 203. 208
Is a high resistance a-Si layer in the antifuse part,
The second and third metal wiring layers 205 and 209 have a sandwiching structure. Details of the above-mentioned prior art are described in JP-A-03-15305.
See 6.

[0003]

In the semiconductor device of the prior art, the connection hole which should have a-Si is formed by the wet / dry method, and the area having the connection hole, for example, 0.8 μm in diameter.
Since it is a structure having a circle of m, and it is desirable to form it without limitation on the step difference of the underlying layer, there is a problem of causing variations in the write voltage and variations in the post-writing resistance. The detailed causes of the above problems will be described below.

Writing of an anti-fuse using a-Si causes a silicide reaction between a-Si and the metal wiring layer by heat generated by applying a voltage to one metal wiring layer sandwiching a high resistance a-Si. , Refers to bringing into conduction. Therefore, writing is performed with an electric field strength higher than a certain level, and generally writing occurs in a very small area only at the edge portion of the connection hole. A comparison will be made between an antifuse formed on a plane as shown in FIG. 2 and an antifuse formed on a slope due to a step difference in the base. In the case of an antifuse formed on a flat surface, the angle between the wall surface of the contact hole and the metal wiring layer at the bottom of the contact hole is approximately a right angle, whereas in the case of an antifuse formed on a slope, the angle is an acute angle in the lower part of the slope. Therefore, the upper side of the slope has an obtuse angle. In this case, in the lower portion of the slope of the antifuse formed on the slope, the effective electric field strength applied to a-Si is higher than that of the antifuse formed on another underlying step, and writing The voltage required for However, since the write voltage applied from the outside is simple and constant, it does not depend on the underlying shape, and since the pattern with a high write voltage is set as a reference, the antifuse formed on the slope effectively has a high electric field. The strength is increased and the writing voltage is lowered. Furthermore, the area in which the silicide reaction occurs is large and the resistance after writing is lower than that of other patterns.
In this way, the writing voltage and the resistance after writing vary. The problem of variation in write voltage is that in the antifuse part where the write voltage is low, the effective electric field strength applied to a-Si is high and the stress is large even at the power supply voltage, and the reliability in the insulation state before writing is deteriorated. Is to let.

The present invention is intended to solve such a problem, and an object of the present invention is to prevent variations in write voltage.
It is an object of the present invention to provide a semiconductor device which can be reduced without being restricted by the underlying step at the place where a connection hole is formed and which has improved reliability in an insulating state before writing an a-Si film.

[0006]

At least for an insulating layer provided on a substrate, a lower metal wiring layer on the insulating layer, and a connection between upper and lower two metal wiring layers, the metal wiring indirect points are minimized. A semiconductor device comprising a contact hole having a point-like contact structure, a high resistance thin film layer formed in the contact hole, and an upper metal wiring layer.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a sectional view of a semiconductor device according to the present invention. An element isolation region 102 is formed on a substrate 101 made of a silicon substrate by thermal oxidation. The first metal wiring 103 is formed by using, for example, poly Si. When the first metal wiring 103 is arranged on the element isolation region 102 as shown in FIG. 1, a step difference with respect to the substrate 101 is about 500.
The height is 0Å. A first insulating layer 104 is formed of, for example, silicon oxide. 105 is a second metal wiring,
Mainly by sputtering, for example, Al-Cu, the above Al-Cu
The upper layer is formed by using, for example, TiN. Reference numeral 106 denotes a second insulating layer, which is mainly made of silicon dioxide by using a chemical vapor deposition method. Reference numeral 107 denotes a connection hole for connecting the second metal wiring 105 and the third metal wiring 109, which is formed using only isotropic etching, and etching is performed until the surface of the second metal wiring 105 is exposed. Therefore, the connection hole 1
The second metal wiring 1 in which the 07 shape is on the ridge and is exposed
Reference numeral 05 is a dot shape, and a minimum contact having a diameter of 0.2 μm, for example, is formed. By forming the connection hole 107 by the above means,
Even if the step of the second metal wiring 105 is flat or sloped, the above-mentioned minimum contact is formed in the same manner. As a method of forming the connection hole 107, for example, a wet etching method using a hydrofluoric acid aqueous solution, a dry etching method using a CF ₄ gas, or a combination of the above dry etching and wet etching is used. The film thickness of the second insulating layer 106 may vary depending on the shape of the underlying step, for example, 5000 Å to 800
It varies with 0Å. In this case, when the isotropic etching is performed, the etching is excessively performed on the thin portion of the second insulating layer 106, which may increase the diameter of the connection hole as compared with the thick portion. To solve this problem, for example, for the connection hole 107 where the second insulating layer formed on the slope of the second metal wiring 205 due to the step difference between the element isolation region 102 and the first metal wiring 103 is thin, patterning in the conventional photo process is performed. The mask size used in this case is reduced to 0.6 μm at the connection hole diameter, which is usually 0.8 μm. The etching rate is determined by the supply rate of the etching chemical species to the material to be etched, the reaction rate, and the rate of desorption from the surface.By decreasing the area to be etched, the etch rate can be lowered. The connection hole diameter can be made constant by controlling the etching amount.

Reference numeral 108 is a high resistance a-Si layer which constitutes an antifuse, and is formed by, for example, a chemical vapor deposition method. Reference numeral 109 denotes a third metal wiring, which is formed by, for example, a sputtering method and has TiN as a lower layer and Al—Cu as an upper layer. The structure of the semiconductor device of the present invention has been described above.

[0009]

In the semiconductor device of the present invention, by minimizing the opening of the connection hole and forming it into a dot shape, the place where silicide occurs during antifuse writing can be limited. This eliminates the dependency of the write voltage on the underlying step,
This is useful for improving the reliability of the high resistance a-Si film in the state before the writing in the portion where the conventional writing voltage is low. In addition,
By using the isotropic etching for forming the contact hole, the throwing power of the upper metal wiring becomes good, which contributes to the improvement of the reliability of the metal wiring and the contact of the contact hole.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 101, 201 Substrate 102, 202 Element isolation region 103, 203 First metal wiring 104, 204 First insulating layer 105, 205 Second metal wiring 106, 206 Second insulating layer 107, 207 Connection hole 108, 208 High resistance a- Si layer 109, 209 Third metal wiring

Claims (1)

[Claims] 1. An insulator layer provided on at least a substrate,
A lower metal wiring on the insulator layer, an insulating layer for insulating between the lower metal wiring and the upper metal wiring, an upper portion formed by isotropic etching, a connection hole for connecting the lower metal wiring, and a connection hole formed in the connection hole. A semiconductor device comprising a high resistance thin film layer and the upper metal wiring.