JPH0926468A - Frequency/cycle measuring device in semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput in the DUT inspection by providing a plurality of channels of frequency/cycle measuring circuits to enable simultaneous measurement of the plurality of channels in the measurement of frequency/ cycle of a signal outputted from the DUT. SOLUTION: In the measurement of frequency or cycle of a signal outputted from a device under test DUT, a plurality of multiplexers 70 that receive signals outputted from plural M comparators wherein the signals outputted from the DUT are converted into digital signals and multiplex them from M to N, is provided. N channels of frequency/cycle counting sections 20 that receive the plural N signals selected by the multiplexers 70 and measure each frequency and cycle of each of the clock signals is further provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for measuring the frequency or period of a pulse output from a device under test (DUT) in a semiconductor test apparatus.

[0002]

2. Description of the Related Art FIG. 3 is an apparatus configuration diagram showing frequency / period measurement of a conventional IC test system. The configuration is a test head 100, a DC 60, and a frequency / cycle counter 5
It consists of 0 and.

The DUT which is the device under test has a device having one or a plurality of oscillation circuits such as a PLL (Phase Locked Loop) circuit, a device for outputting a signal obtained by arbitrarily dividing these, or a high frequency signal. There is a device that outputs a signal such as a communication device, and these signals are often signals that are asynchronous with the IC test system side. The IC test system has a frequency / cycle measuring function for measuring signals output from these devices.

The test head 100 tests one or a plurality of DUTs. A test pattern 150pat shaped into a desired waveform from a PG (Pattern Generator) is received, converted into a desired amplitude level by a driver 110, and then applied to an input pin. The plurality of M output signals from the DUT are converted into digital signals by the comparator 120,
Supply to DC60.

A DC 60 (digital comparator) is a comparison unit 62 which uses logic data from the comparator 120 and PG
PASS / FAIL by comparing with expected value data
The information of the determination result of is output. In addition to this, there is an MPX 70 that selects and outputs a desired signal to the frequency / cycle counter 50. This MPX (multip
The lexer) 70 is provided with a plurality of 8to1 selectors, for example, and supplies the N-channel signal after selecting a desired signal from the number M of input signals to the frequency / cycle counting section 50.

The frequency / cycle counter 50 is a 1-channel counter that counts frequencies or cycles under desired measurement conditions, receives an N-channel signal from the DC 60, and a multiplexer (MPX) 52 outputs Nto1. One of the selected signals is received, the reference clock 55clk is received, and the frequency or period is counted by the counter 56 having a length of 30 bits, for example. As a result, the frequency / cycle measurement function is realized for any one of the signals output by the DUT in the test head 100. As described above, in the related art, since the function for measuring the frequency / cycle of one channel is used, there is a problem that a plurality of DUTs cannot be measured simultaneously and the test time becomes long. In addition, there are some DUTs having a plurality of oscillation circuits, and there is a problem that simultaneous measurement cannot be performed.

[0007]

As described above, in the conventional one-channel frequency / cycle counter 50, signals from a plurality of pins of the test head 100 cannot be simultaneously measured and must be serially measured. . For this reason, there are problems in use such that the test time becomes long and the throughput is lowered, the test pattern program is constrained, or the test pattern becomes long and large.

Therefore, the problem to be solved by the present invention is to provide a plurality of channels of the frequency / cycle measuring circuit at the time of measuring the frequency / cycle output from the DUT to enable simultaneous measurement, thereby facilitating the DUT test. In addition, the purpose is to improve throughput.

[0009]

In order to solve the above-mentioned problems, in the structure of the present invention, in measuring the frequency or period of the signal output from the device under test DUT, a plurality of signals output from the DUT are converted into digital signals. The frequency / cycle counter 20 receives the signals from the M comparators, receives the plurality of N signals selected by the plurality of multiplexers 70 that multiplex into MtoN, and individually measures the frequencies or periods of these clock signals. The configuration means is provided with N channels. As a result, in measuring the clock frequency or the clock period of the signal output from the device under test, it is possible to simultaneously measure the frequency / period of a plurality of channels.

The frequency / cycle counter 20 has counters 30a to 30 for measuring the frequency and cycle of N channels.
n or Pto1 multiplexers 32a ...
There is a means for configuring the counters 30a to 30q which are provided with 32q and receive the signal after selecting the N-channel input signal and individually measure the frequency or period. Further, as the frequency / cycle counting section 20, there is a configuration means in which at least two channels for frequency / cycle measurement are provided and multiplexers 32a to 32q corresponding thereto are provided.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows the frequency / frequency of multiple channels of the present invention.
It is a block diagram of an IC test system having a cycle measuring circuit. The configuration includes a test head 100, a DC 60, and a frequency / cycle counter 20. Frequency / cycle counter 20
Other than that, the configuration is the same as the conventional one.

The frequency / cycle counting section 20 is a counter 30 for frequency / cycle measurement for simultaneously counting a plurality of N signals.
a to 30n. N selected by MPX70 of DC60
It is an N-channel counting unit that receives a book signal and counts a frequency or a period under independent measurement conditions.

As a result, when a plurality of output pins of a single DUT or a plurality of DUTs are simultaneously measured, the signals from the output pins of these DUTs are simultaneously received, and the frequency / frequency
The period can be measured simultaneously, the DUT test can be shortened, and the throughput of the device test can be improved. At the same time, the test program for this device test is short, and there is no limitation in creating the test program.

In the above description of the embodiment, the example in which the MPX 70 receives the N signals selected and individually provides the counters 30a to 30n for measuring the frequency / cycle of the N channel has been described. Multiple multiplexers 32a
.About.32q and a plurality of counters 30a to 30q, as shown in the block diagram of FIG.
2a to 32q are selected, these q signals are received, and these frequencies or periods are measured. That is, at least q = 2 channels of counters for frequency / cycle measurement may be provided, and an MPX 32 corresponding thereto may be provided, which can be implemented in the same manner and is effective.

[0015]

Since the present invention is configured as described above, it has the following effects. The frequency / cycle counter 20 can simultaneously measure the frequencies / cycles of a plurality of N signals. This makes it possible to measure frequency / period simultaneously when measuring multiple output pins of a single DUT or multiple DUTs.
The T test can be shortened, and the throughput of the device test can be improved. Furthermore, since the test program for device test can be shortened and there is no limitation in creating the test program, the attendant effect of facilitating the test program creation can be obtained. From these, there is an advantage that the throughput of the DUT test at the time of frequency / cycle measurement can be improved and the test pattern length for this purpose can be shortened to eliminate the restriction on the test program creation.

[Brief description of drawings]

FIG. 1 is an example of a configuration diagram of an IC test system having a frequency / cycle measuring circuit of a plurality of channels according to the present invention.

FIG. 2 illustrates a plurality of multiplexers 32a-32 of the present invention.
q and a plurality of counters 30a to 30q,
It is an example of a circuit configuration diagram of a frequency / cycle counter.

FIG. 3 is a device configuration diagram showing frequency / period measurement of a conventional IC test system.

[Explanation of symbols]

20, 50 Frequency / cycle counter 56, 30a to 30n, 30q Counter 32a to 32q, 52, 70 Multiplexer (MP
X) 55clk Reference clock 60 DC (digital comparator) 62 Comparator 100 Test head 110 Driver 120 Comparator 150pat Test pattern

Claims (3)

[Claims] 1. In a frequency or period measurement of a signal output from a device under test (DUT), the signal output from the DUT is converted into a digital signal, and signals from a plurality (M) of comparators are received and multiplexed into MtoN. A plurality of (N) signals selected by the plurality of multiplexers (70) are received, and N channels of frequency / cycle counters for individually measuring the frequency or cycle of these signals are provided. Frequency / cycle measuring device in semiconductor test equipment 2. The frequency / cycle counter comprises a counter for measuring the frequency or cycle of N channels, or a Pto1 multiplexer is provided to receive signals after selecting an N channel input signal, A counter configured to measure a cycle.
A frequency / period measuring device in the semiconductor testing device described. 3. The frequency / cycle counting section is provided with at least two channels for frequency / cycle measurement counters, and multiplexers (32a-32) corresponding thereto are provided.
The frequency / period measuring device in the semiconductor test device according to claim 1, wherein q) is provided.