JPH09261211A - Bit synchronization system - Google Patents

Abstract

There is provided a bit synchronization method capable of recovering an optimum reception clock even for a reception signal having a deviated duty ratio and capturing bit synchronization by receiving data in a short time. Kind Code: A1 A bit synchronization method including a receiving unit that receives serial data, a clock generation unit that reproduces the transmission timing from the received data, and a signal detection unit that detects the received data at the timing of the clock, In order to generate the reproduction clock, the reproduction clock is generated at the central timing of each representative value obtained by integrating the timings at which the rising change point and the falling change point of the received data are detected. It has the following structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization system used for detecting data by recovering a clock corresponding to a transmission rate of data transmitted from the received data when receiving serial data.

[0002]

2. Description of the Related Art A conventional method is shown in FIG. The phase comparison unit 11 detects the difference between the change point of the received data and the reception clock generated by the reception clock generation unit 10 and controls the reception clock generation unit 10 to advance or delay the reception clock so as to eliminate the difference. The PLL system is used to perform the above operation and adjust the generated reception clock to the timing of the reception data. The reception clock is the data detection unit 12
Used to detect received data.

[0003]

In the case of this method, when the duty ratio of the received data is biased, in order to prevent the phase of the received clock from being locked at the timing shifted by 90 °, the rise or fall changes. Only detects and is bit-synchronized. In this case, the change information for synchronization is halved, and the time required to capture the bit synchronization is doubled. Further, when the duty ratio is 1/4 or less, there is a drawback that reception becomes impossible.

An object of the present invention is to provide a bit synchronization system capable of recovering an optimum reception clock even for a reception signal having a deviated duty ratio and capturing bit synchronization by receiving data in a short time. .

[0005]

To achieve this object, a bit synchronization system according to the present invention comprises a receiving section for receiving serial data, a clock generating section for reproducing the transmission timing from the received data, and In a bit synchronization system equipped with a signal detection unit that detects received data according to clock timing, in order to generate the above-mentioned reproduced clock, each timing at which a rising change point and a falling change point of received data are detected is integrated The reproduced clock is generated at the central timing of each of the representative values obtained in this way.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of a block of the system of the present invention. The change point integration unit 1 obtains the timing of the change point from the received data and accumulates it in the change point integration memory 2. In this case, the change point is calculated and integrated at the cycle of the transmission speed of the received data. FIG. 1B shows the change timing frequency accumulated in the change point accumulation memory 2. After N bits are received, the average value or median value of the rising timing and the falling timing is obtained as a representative value, and the center timing of each representative value at each of the rising and falling timings is used as a reception clock for data reading and a recovered clock is reproduced. Play in part 4. The data detector 4 correctly detects the received data using the recovered clock. Further, erroneous synchronization due to noise or the like can be prevented by not performing synchronization correction when the change timing frequency is M or less.

[0007]

As described in detail above, according to the present invention, it is possible to capture the bit synchronization in half the time as compared with the conventional PLL system. Further, even when the duty is 1/4 or less, the received signal can be correctly detected.

[0008]

[Brief description of drawings]

FIG. 1 is a block diagram (a) showing a configuration example of an embodiment of the present invention, a frequency distribution diagram (b) showing a change point integrating operation, and a signal detection timing diagram (c).

FIG. 2 is a block diagram (a) and a signal detection timing diagram (b) of a conventional bit synchronization method.

[Explanation of symbols]

 1 Change Point Integration Section 2 Change Point Integration Memory 3 Reproduced Clock Generation Section 4, 12 Data Detection Section 10 Received Clock Generation Section 11 Phase Comparison Section

Claims (2)

[Claims] 1. A bit synchronization system comprising a receiving section for receiving serial data, a clock generating section for reproducing the transmission timing from the received data, and a signal detecting section for detecting the received data at the timing of the clock. In order to generate the regenerated clock, the regenerated clock is generated at the central timing of each representative value obtained by integrating the respective timings at which the rising change point and the falling change point of the received data are detected. Characteristic bit synchronization method. 2. A bit synchronization method, wherein a rising change point and a falling change point are adopted as the change points of the received data.