JPH09261210A - Synchronization clock distribution system for synchronization transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To warrant phase synchronization among plural synchronization transmitters even on the occurrence of a fault in any of synchronization clock distribution lines with redundant configuration. SOLUTION: Ring distribution lines R0, R1 for 0 system/1 system synchronizing clocks CK0, CK1 are formed by interconnecting a distributed clock system(DCS) 1 and synchronization transmitters 21-2n by distribution lines L00-L0n and L10-L1n respectively as rings. Each of the synchronization transmitters 21-2n relays respectively the 0 system/1 system synchronizing clocks CK0, CK1 but stops a synchronizing clock to be outputted to a succeeding transmitter upon the detection of a fault in the synchronizing clock being received. Thus, on the occurrence of a fault anywhere in the distribution lines L00-L0n and L10-L1n, the synchronizing clock to be returned to the DCS 1 is missing. The DCS 1 receives/monitors the synchronizing clocks CK0, CK1 outputted by itself and in the case of detecting clock missing, the DCS 1 stops output of the missing synchronizing clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock distribution system for distributing a synchronous clock in a synchronous transmission system in a station building, for example.

[0002]

2. Description of the Related Art Recently, synchronization of transmission systems has become a global trend, and the unification of hierarchies is being promoted. In particular, the SDH (Synchronous Digital Hierarchy) system is becoming the standard of the trunk optical transmission system, and up to the present, STM-16, that is, 2.4 GHz system has been put to practical use.

However, a system having a higher transmission speed is currently out of the SDH hierarchy due to device restrictions and the like, and there is a means for increasing the speed by multiplexing the STM-16 signal by simple bit multiplexing. It is taken. The advantage of this method is that it enables free design such as the use of error correction codes to ensure the transmission quality during ultra-high speed transmission.

As a matter of course, in order to enable the bit multiplexing, it is necessary that the bit synchronization of the signals to be multiplexed be established. FIG. 8 shows a conventional example of a synchronous clock distribution system for establishing this synchronization.

FIG. 8 shows the structure of a conventional synchronous transmission system based on the synchronous clock distribution system, and 101 is a synchronous clock distribution device (DCS: Digital Clock Supply). The DCS 101 inputs a 0-system synchronous clock CK0 and a 1-system synchronous clock CK1 and outputs these synchronous clocks C
K0 and CK1 are distributed in a star shape to a plurality of (two in FIG. 6) synchronous transmission devices 102 and 103.

In the conventional synchronous clock distribution system, first, all synchronous transmission devices are synchronized with the 0-system synchronous clock. That is, the synchronous transmission devices 102 and 103 operate in synchronization with the 0 system, and transmit transmission data to the bit multiplexing device 104. The bit multiplexer 104 is reset in the initial state, and bit-multiplexes the transmission data from the synchronous transmission devices 102 and 103 and outputs it.

However, in the conventional system, when a failure occurs in any of the 0-system / 1-system synchronous clock distribution paths, only the synchronous transmission device of the system in which the failure has occurred synchronizes with the 1-system clock. . At this time, if the phases of the 0-system and 1-system synchronous clocks are completely the same, no problem will occur, but in reality, the phase difference will fluctuate due to wander due to differences in clock paths, or a specific synchronous transmission will occur. Only the device switches to the 1 system due to the failure of the synchronous clock.

In such a case, the bit phases of the transmission signals are deviated from each other, and the operating point of the memory for absorbing the phase difference is deviated in the bit multiplexer 104, and in the worst case, the memory overflows. The transmitted signal slips.

That is, according to the conventional concept of the synchronous clock distribution system, it is impossible to guarantee the bit synchronization between the plurality of synchronous transmission devices 102 and 103, and it is extremely difficult to introduce the bit multiplexing device 104. .

[0010]

As described above, in the synchronous clock distribution system used in the conventional synchronous transmission system, a plurality of synchronous clocks are distributed to each synchronous transmission device to form a redundant configuration. However, when a failure occurs in any of the synchronous clock distribution paths, only the synchronous transmission device of that path is switched to the redundant synchronous clock, and the synchronous relationship with other synchronous transmission devices cannot be maintained.

The present invention solves the above-mentioned problems, and even if a failure occurs in any of the synchronous clock distribution paths of the redundant configuration,
An object of the present invention is to provide a synchronous clock distribution system that can guarantee phase synchronization among a plurality of synchronous transmission devices.

[0012]

In order to achieve the above object, a synchronous clock distribution system of a synchronous transmission system according to the present invention is a transmitting means for transmitting a plurality of synchronous clocks of at least two systems, and this transmitting means. Receiving means for receiving a plurality of synchronous clocks transmitted by the above step, and a disconnection for monitoring the receiving state of each of the synchronous clocks of the receiving means to detect an input disconnection of the synchronous clock and stopping the output of the synchronous clock corresponding to the transmitting means. Synchronous clock supply device including detection means, receiving means for receiving the plurality of synchronous clocks, transmitting means for transmitting the plurality of synchronous clocks received by the receiving means, inputting of the synchronizing clocks by monitoring the receiving state of the receiving means Disconnection detecting means for detecting disconnection and stopping output of the synchronization clock corresponding to the transmitting means, and a plurality of synchronizations received by the receiving means A plurality of synchronous transmission devices provided with a selection means for selecting one of the locks in a predetermined priority order, and a plurality of synchronous clocks output from the synchronous clock supply device are sequentially relayed by the plurality of synchronous transmission devices. A plurality of ring distribution paths are formed so as to be sent back to the synchronous clock supply circuit.

In particular, the selection means of the synchronous transmission device is of a non-revertive type that performs a selection switching operation when a failure occurs in the selected synchronization clock and does not switch back when the failure is recovered.

Further, the disconnection detecting means of the synchronous clock supply device, after stopping transmission of the synchronous clock for disconnection detection,
The transmitting means is caused to start transmitting the clock periodically, and the state in the ring distribution path is monitored.

Further, the plurality of ring distribution paths are arranged so as to have the same length between the respective synchronous transmission devices. That is, in the synchronous clock distribution system having the above-mentioned configuration, the distribution of the synchronous clock is a so-called ring-shaped connection in which a synchronous transmission device is inserted in the distribution path, and when an error occurs at any one of the positions, the same on the redundant side. As described above, control is performed so that the synchronous clock is switched to the clock distribution system that is ring-connected.

According to this, since the clock distribution path is a ring network, any failure between a plurality of synchronous transmission devices can be detected, and at the same time when the failure occurs, the distribution path has the same ring configuration. Since the redundant system can be switched to the redundant system, it is possible to synchronize a plurality of synchronous transmission devices receiving the clock with the clock of the same system even when a failure occurs. Therefore, the wander between the synchronization clocks caused by the wander between the devices can be ignored, and only the devices need to be managed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 shows the configuration of a synchronous transmission system in a station using the synchronous clock distribution system according to the present invention, where 1 is 0 system (normal system) /
DCSs 21, 22, 22, ..., 2n for distributing and supplying 1-system (standby system) synchronous clocks CK0 and CK1 are 0-system / 1
A synchronous transmission device 3 which receives the system synchronous clocks CK0 and CK1 and performs data processing based on either one of the synchronous clocks is bit-multiplexed while phase-synchronizing the transmission data from the synchronous transmission devices 21 to 2n and output. It is a bit multiplexing device that does.

In the synchronous transmission system of this embodiment, the DCS 1 and the synchronous transmission devices 21 to 2n are used for network synchronization.
And L0n are connected in a ring shape by distribution lines L00, L01, L02, ..., L0n to form a ring distribution line R0 of the 0-system synchronous clock CK0, and distribution lines L10, L
, L12, ..., L1n are connected in a ring shape to form a ring distribution path R for the 1-system synchronous clock CK1.
Form one.

That is, the synchronous transmission device 21 distributes the 0-system / 1-system synchronous clocks CK0 and CK1 to the distribution lines L00 and L00, respectively.
Received from L10 and used for internal data processing,
It outputs to the distribution lines L01 and L11 toward the next synchronous transmission device 22. Similarly to the synchronous transmission device 21, the synchronous transmission device 22 uses the received clocks CK0 and CK1 for internal data processing, and at the same time, the next synchronous transmission device (not shown).
To the distribution lines L02 and L12. The last synchronous transmission device 2n returns the received synchronous clocks CK0 and CK1 to DCS1 through the distribution lines L0n and L1n.

Further, each of the synchronous transmission devices 21 to 2n has a function of detecting a failure when the received synchronous clock disappears and, at the same time, stopping the synchronous clock output to the next device. Therefore, the synchronization clock that should return to the DCS1 disappears no matter where the failure occurs in the distribution paths L00 to L0n or L10 to L1n.

In DCS1, distribution lines L00-L0
n, L10 to L1n, the synchronous clocks CK0 and CK1 output by itself are terminated, and the synchronous clocks CK0 and CK0,
When the clock loss is detected by receiving / monitoring CK1, it has a function of stopping the output of the synchronization clock on the lost side.

The processing operation of the above configuration will be described with reference to FIG. In FIG. 2, in order to make the explanation easy to understand, n = 2 is set, and DCS1 and synchronous transmission devices 21 and 22 are set.
Are connected by distribution lines L00 to L02 to form a ring distribution line R0 for the synchronous clock CK0.
A case where the ring distribution path R1 for the synchronous clock CK1 is formed by connecting with L12 will be described.

First, it is assumed that the synchronous transmission devices 21 and 22 are operating in synchronization with the synchronous clock CK0 received from the distribution lines L00 and L01, respectively, in the state where no failure occurs. In this state, when a failure occurs in the distribution line L01 and the input clock CK0 of the synchronous transmission device 22 disappears, the synchronous transmission device 22 synchronizes with the synchronization clock CK1 on the distribution line L11 side.
, But at the same time, the distribution path L is selected.
The output clock CK0 to 02 is stopped.

As a result, the synchronous clock CK0 from the distribution line L02 disappears even in DCS1, so that the DCS1 stops the synchronous clock CK0 output to the distribution line L00. As a result, the input clock CK0 of the synchronous transmission device 21
Disappears, and the synchronous transmission device 21 also operates by switching to the synchronous clock CK1 from the distribution line L10.

The time required for this series of processing operations also depends on the frequency of the synchronizing clock to be distributed, but even in the case of the most common 64 kHz +8 kHz composite signal, it is necessary to detect the clock loss and stop the output. The required time is only 1 msec for one synchronous transmission device.

Considering the case of FIG. 2, the synchronous transmission device 22
As shown in FIG. 3, the time difference between the timing t1 when the loss of the synchronous clock CK0 is detected and the switching starts and the timing t2 when the synchronous transmission device 21 finally starts the switching is 2 msec + transmission delay of the ring distribution path R0. Determined in minutes.

Since the ring currently being considered is the ring inside the station building, the maximum ring length is considered to be about 1 km.
Therefore, the delay time on the ring distribution path R0 is 5 nsec / m.
× 1000 m = 5 μsec, which can be ignored.

When the number of synchronous transmission devices connected to the ring distribution lines R0 and R1 is n, the ring structure is the same with n + 1 units including the DCS1. In this case, a failure is first detected. The time difference between the switching device and the last switching device is 1 msec × n = nmsec. Therefore, for example, with 10 units, the ring distribution paths R0, R
Even if 1 is assembled, the time difference will be about 10 msec. Set the frequencies of the synchronization clocks CK0 and CK1 to 1.
If the speed is increased to 5MHz or 2MHz, the time can be shortened by one digit or more.

The effect will be described below. Distribution line L00
And L10, L01 and L11, and L02 and L12 are set to have substantially equal lengths, as shown in FIG. 4, the synchronous clock C between the synchronous transmission devices 21 and 22 is set.
As for the phase difference between K0 and CK1, the device determines the distribution paths L00 and L01.
This is the same when operating by selecting the side and when selecting the distribution paths L10 and L11.

That is, the phase difference of the reception clocks between the synchronous transmission devices 21 and 22 is the distribution line L0 when the 0 system is selected.
The phase difference corresponds to the delay time of 1, and the phase difference corresponds to the delay time of the distribution path L11 when the 1-system is selected. For this reason, if both lengths are equal, the phase difference between the two units does not change when selecting the 0-system and when selecting the 1-system.

Therefore, it can be considered that the phases of the data signals output from the synchronous transmission devices 21 and 22 are also substantially the same. In other words, it is considered that the bit phase of the output between the two units is substantially constant in the steady state regardless of whether the 0 system is selected or the 1 system is selected.

Next, the transient response in which the ring transmission path is switched due to the occurrence of the above-mentioned failure will be described with reference to FIG. FIG. 5 shows the time before and after the occurrence of a failure on the horizontal axis and the phases of the synchronous transmission devices 21 and 22 on the vertical axis, and shows changes in both phases at the time of switching. Explaining with the configuration of FIG. 2, the synchronous transmission device 22 first causes the phases ι 11 to 1 at the time t1 due to the failure of the distribution line L01.
It starts to change to the reference phase ι21 of the distribution path L11 of the system.
On the other hand, the synchronous transmission device 21 is 2 msec
Later (time t2), the phase change starts toward the reference phase ι20 of the first system.

When the switching is completely completed and becomes stationary,
The phase difference between the two is determined by the same phase difference Δι as before the switching, but during the switching, the phase difference between the two changes so as to decrease in the case of this figure. Depending on the location of the failure, the phase of the synchronous transmission device 21 may change earlier and the phase difference may increase.

Here, in FIG. 5, the state is shown in an extreme manner so that the situation can be clearly seen. As described above, the clock is 64 kHz +
In the case of a composite signal of 8 kHz, the time difference between t1 and t2 is 2 msec, and even if the system becomes large, it will be 10 msec if there are at most 10 units. Therefore, if a high-speed clock such as 2 MHz is used, it can be easily suppressed to 1 msec or less. On the other hand, if the transient response characteristic at the time of switching is set to about 1 second, the change in the phase difference on the way can be suppressed to be extremely small.

As a result, in the configuration of FIG. 2, when the outputs of the two synchronous transmission devices 21 and 22 are bit-multiplexed, the amount of phase fluctuation that must be absorbed by the bit multiplexer 3 side is small, Since the memory does not have to be increased, an economical system as a whole can be realized.

Further, according to this method, it is possible to manage the bit phases of not only two, but also more synchronous transmission devices.
Since the bit multiplexer 3 can be applied not only to 2 bits but also to N bits, it can easily contribute to an increase in transmission rate.

By the way, once a failure occurs, D
Since CS1 stops the output on the fault occurrence side, even if the fault disappears, it is not clear whether the output can be restarted. With respect to this, it may be manually forcibly started up, or an output may be periodically generated to check whether or not a failure remains. In that case, if a switching control function of non-revertive type is provided on the synchronous transmission devices 21 to 2n side, switching can be prevented from occurring at the time of checking.

Specific configurations of the DCS 1 and the synchronous transmission devices 21 to 2n for realizing the above processing operations are shown in FIGS. 6 and 7, respectively. FIG. 6 shows a specific configuration of the DCS1. This DCS1 has a first
And the second reference clock CKref1 and the 1-system synchronization clock CKref2 are digital phase synchronization circuits (hereinafter referred to as DP
LL circuits) 1A and 1B are phase-synchronized with each other, and one is supplied to the 0-system clock transmission circuit 1C and the 1-system clock transmission circuit 1D as a master and the other as a slave. Each of the clock transmission circuits 1C and 1D normally outputs the master clock from the DPLL circuit 1A to the distribution lines L00 and L10 as the synchronous clock CK0 or CK1. If an error occurs in the master clock, switch to the slave side.

Further, the DCS1 sets the synchronous clocks CK0 and CK1 returned from the distribution lines L0n and L1n to 0, respectively.
System clock receiving circuit 1E and 1 system clock receiving circuit 1F
To receive. The disconnection detection circuits 1G and 1H monitor the reception states of the reception circuits 1E and 1F, respectively. When disconnection is detected, the clock transmission circuits 1C and 1D of the corresponding system stop the clock transmission, and when they recover, the clock transmission is performed. Resume.

That is, in the DCS1 having the above configuration,
Normally, the master system clock is used to generate the 0-system / 1-system synchronous clocks CK0 and CK1, which are independently sent to the ring distribution paths R0 and R1, and the return thereof is detected. Here, if an abnormality occurs in the master clock, the operation is guaranteed by switching the clock on the slave side. Further, the return of each of the synchronous clocks CK0 and CK1 is monitored, and when the disconnection is detected, the clock transmission on the detection side is stopped.

FIG. 7 shows a concrete structure of the synchronous transmission device 2i (i is one of 1 to n). The synchronous transmission device 2i includes a 0-system clock receiving circuit 2A that receives the 0-system clock CK0 from the distribution line L0 (i-1), and a 0-system clock CK0 received by the circuit 2A.
A 0-system clock transmission circuit 2B and a 0-system clock reception circuit 2A for sending to i are provided with a disconnection detection circuit 2C for stopping the clock transmission of the 0-system clock transmission circuit 2B when a disconnection is detected.

Similarly, a 1-system clock receiving circuit 2D for receiving the 1-system clock CK1 from the distribution line L1 (i-1),
The 1-system clock transmission circuit 2E that sends the 1-system clock CK1 received by the circuit 2D to the distribution line L1i monitors the reception state of the 1-system clock reception circuit 2D and sends the clock of the 1-system clock transmission circuit 2E when a disconnection is detected. A disconnection detection circuit 2F for stopping the operation is provided.

The 0-system / 1-system synchronous clocks CK0 and CK1 received by the clock receiving circuits 2A and 2D are both supplied to the clock selecting circuit 2G. This clock selection circuit 2
G normally selects and outputs the 0-system synchronous clock CK0, and selectively outputs the 1-system synchronous clock CK1 after the disconnection detection circuit 2C detects disconnection, and the selection control is a non-revertive type.

The synchronous clock selected here is used for data processing of the data processing circuit 2H. The data processed by the data processing circuit 2H is sent to the bit multiplexer 3 by the data transmission circuit 2I.

That is, the synchronous transmission device 2 having the above configuration
In i, the 0-system / 1-system synchronous clocks CK0 and CK1 are always received and sent to the adjacent device 2 (i + 1), and the 0-system synchronous clock CK0 is normally selected and used internally. Here, the 0 system synchronous clock CK that is normally used
When the occurrence of the disconnection of 0 is detected, the sending of the synchronous clock CK0 is stopped and the clock selection is changed to the 1-system synchronous clock CK1.
Switch to

Since the clock selection control is a non-cutback type, even if the 0-system synchronous clock CK0 is restored, the selection is not restored. Therefore, the synchronous transmission devices 21 to 2n all operate on the 1-system synchronous clock CK1,
Only part of it will never return to the 0 series. Therefore,
By using the DCS and the synchronous transmission device configured as described above, it is possible to construct a synchronous transmission system that achieves the effects of the above-described embodiment.

[0047]

As described above, according to the present invention, it is possible to manage the bit phases of a plurality of synchronous transmission devices by a simple method, so that it is possible to easily realize an increase in transmission rate by bit multiplexing. As a result, a small memory for absorbing phase fluctuations provided in the bit multiplexer can be used. Therefore, it is possible to provide a synchronous clock distribution system capable of guaranteeing phase synchronization among a plurality of synchronous transmission devices even if a failure occurs in any of the redundant synchronous clock distribution paths.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a synchronous transmission system using a synchronous clock distribution system according to the present invention.

FIG. 2 is a diagram for explaining a failure operation of the embodiment.

FIG. 3 is a view for explaining a time relationship at the time of failure in the embodiment.

FIG. 4 is a diagram for explaining a phase relationship of the same embodiment.

FIG. 5 is a diagram for explaining a phase variation of the same embodiment.

FIG. 6 is a diagram showing a synchronous clock distribution device (DCS) of the embodiment.
3 is a block circuit diagram showing a specific configuration of FIG.

FIG. 7 is a block circuit diagram showing a specific configuration of the synchronous transmission device of the embodiment.

FIG. 8 is a block circuit diagram showing the configuration of a conventional synchronous transmission system using a synchronous clock distribution system.

[Explanation of symbols]

 1 ... Clock supply device (DCS) 1A, 1B ... Digital phase synchronization circuit (DPLL) 1C ... 0 system clock transmission circuit 1D ... 1 system clock transmission circuit 1E ... 0 system clock reception circuit 1F ... 1 system clock reception circuit 1G, 1H ... disconnection detection circuit 21, 2n ... synchronous transmission device 2A ... 0 system clock reception circuit 2B ... 0 system clock transmission circuit 2C ... disconnection detection circuit 2D ... 1 system clock reception circuit 2E ... 0 system clock transmission circuit 2F ... disconnection detection circuit 2G ... Clock selection circuit 2H ... Data processing circuit 2I ... Data transmission circuit 3 ... Bit multiplexer CK0 ... First synchronization clock CK1 ... Second synchronization clock L00-L0n ... 0-system synchronization clock distribution path L10-L1n ... 1-system synchronization Clock distribution path R0 ... 0 system ring distribution path R1 ... 1 system ring distribution path

Claims (4)

[Claims] 1. A transmitting means for transmitting a plurality of synchronous clocks of at least two systems, a receiving means for receiving a plurality of synchronous clocks transmitted by the transmitting means, and a receiving state of each synchronous clock of the receiving means. A synchronous clock supply device having a disconnection detecting means for detecting an input disconnection of the synchronous clock and stopping the output of the synchronous clock corresponding to the transmitting means, a receiving means for receiving the plurality of synchronous clocks, and a receiving means for receiving by the receiving means. A transmitting means for transmitting a plurality of synchronous clocks, a disconnection detecting means for monitoring the reception state of the receiving means, detecting an input disconnection of the synchronous clock, and stopping the output of the synchronous clock corresponding to the transmitting means, and the receiving means. A plurality of synchronous transmission devices having a selection unit for selecting one of the plurality of received synchronous clocks in a predetermined priority order, Synchronization of a synchronous transmission system characterized in that a plurality of ring distribution paths are formed so that a plurality of synchronous clocks output from a clock supply device are sequentially relayed by the plurality of synchronous transmission devices and sent back to the synchronous clock supply circuit. Clock distribution method. 2. The selection means of the synchronous transmission device is a non-revertive type that performs a selection switching operation when a failure occurs in a selected synchronous clock and does not perform a switchback even when the failure is recovered. The synchronous clock distribution system of the synchronous transmission system according to claim 1. 3. The disconnection detecting means of the synchronous clock supply device, after stopping the transmission of the synchronous clock for disconnection detection, causes the transmitting means to periodically start the transmission of the clock, and in the ring distribution path thereof. 2. A synchronous clock distribution system for a synchronous transmission system according to claim 1, wherein the status is monitored. 4. A synchronous clock distribution system for a synchronous transmission system according to claim 1, wherein said plurality of ring distribution lines are wired with equal length between respective synchronous transmission devices.