JPH09260602A - Semiconductor memory and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM having the unit cell area of 4F<2> (F=desing dimension) capable of realizing, even if the miss-alignment of pattern in the manufacturing step is prospected. SOLUTION: Diffused layers 2(2a, 2b) are formed on an SOI substrate 4. Gate electrodes 1 covered with nitride films 7 are formed on the substrate 4 through the intermediary of gate oxide films 6. A bit line 12 is connected to the diffused layer 2b. An oxide film 8 is formed on the substrate 4 and the nitride film 7. Two of plug electrodes 9 are formed between the gate electrodes 1. A separation insulting film 10 is formed between the two plug electrodes 9. A plug connecting electrode 11, connecting to the plug electrodes 9, is formed on the upper part of the oxide film 8. An another oxide film 15 is formed on the separation insulating film 10 and the oxide film 8 through the intermediary of another nitride film 14. An accumulation electrode 17 is formed on the upper part of the plug, connecting electrode 11 through the intermediary of another electrode 16. Finally, a dielectric film 18 is formed on the accumulation electrode 17 and the oxide film 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, the unit cell area is 4F.
^{The present} invention relates to a semiconductor memory device having ² (F is a design dimension) and a manufacturing method thereof.

[0002]

2. Description of the Related Art A DRAM comprising one transistor and one capacitor cell is the mainstream of currently manufactured DRAMs because the unit cell area is small, the size is small, and the manufacturing cost is low. FIG. 27 shows a memory cell portion of a conventional one-transistor-one capacitor cell DRAM. 27A is a plan view and FIG. 27B is a plan view.
27A is a cross-sectional view of the AA ′ portion, and FIG. 27C is a cross-sectional view of the BB ′ portion.

Reference numeral 1 is a gate electrode (word line), and 2 (2
a, 2b) is a diffusion layer, 5 is an element isolation insulating film, 6 is a gate oxide film, 7 is a nitride film, 8 is an oxide film, 12 is a bit line, 13 and 14 are nitride films, 15 is an oxide film, 1
Reference numeral 7 is a storage electrode of the capacitor, 18 is a dielectric film of the capacitor, 50 is a semiconductor substrate, and 51 is an electrode.

In FIG. 27A, one storage electrode 17 of the capacitor is connected to the diffusion layer 2a between the gate electrodes via the connection electrode 51, and the bit line 12 is connected to the diffusion layer 2b. It The unit cell of the DRAM of this layout is the portion shown in the region C in FIG.
Its area is 6F ² . When the size of the unit cell is reduced, the chip area is reduced and thus the manufacturing cost is reduced.
However, with the above-described conventional DRAM configuration, the area of the unit cell cannot be reduced to 6 F ² or less.

As a unit cell having a size of 6F ² or less, a memory cell having a vertical transistor or a memory cell having a storage electrode in a substrate (Japanese Patent Laid-Open No. 5-12955).
No. 1) has been proposed.

Since a memory cell having a vertical transistor uses a sidewall as a channel, it is more difficult to control a threshold value than a transistor formed on a plane and the subthreshold coefficient tends to be large. It is difficult to realize a high-performance DRAM.

In addition, the memory cell having the storage electrode in the substrate has a unit cell area of 4F ^{2 as a} planar transistor by forming two connection electrodes between adjacent gate electrodes.
Has been realized. However, since the storage electrode is formed in the substrate, the gate electrode pattern and the trench pattern are not formed in a self-aligned manner. Since the connection electrode has a thickness of 1/4 to 1/6 of the design size, there is a fatal defect that the storage electrode and the connection electrode are disconnected due to a slight misalignment, or the bit line is short-circuited to an adjacent cell. It was not a feasible structure.

[0008]

SUMMARY OF THE INVENTION As described above,
In the structure of a stack type general DRAM, the area of the unit cell cannot be reduced to 6F ² or less. Also, 4
Various DRAM structures for realizing F ² have been proposed, but it is difficult to control the threshold value of a transistor,
There is a problem such as short circuit due to misalignment,
It was extremely difficult to achieve 4F ² .

An object of the present invention is to provide a semiconductor memory device in which the area of a unit cell that can be realized is 6F ² or less and a method for manufacturing the same, even if misalignment of patterns is assumed.

[0010]

[Means for Solving the Problems]

(Structure) The semiconductor memory device and its manufacturing method of the present invention are structured as follows.

(1) In a semiconductor memory device in which memory cells each consisting of a MOS transistor and a capacitor are two-dimensionally arranged on a semiconductor substrate, and the storage electrode of the capacitor is formed above the transistor formation region,
One contact hole is formed between the gate electrodes of the MOS transistors adjacent to each other in the memory cell, the source / drain diffusion layers of the MOS transistors adjacent to each other are separated from each other in the contact hole portion, and the diffusion layers are formed in the respective diffusion layers. A connection electrode for connecting to the storage electrode is connected.

(2) A method of manufacturing a semiconductor memory device in which memory cells each consisting of a MOS transistor and a capacitor are two-dimensionally arranged on a semiconductor substrate, and the storage electrode of the capacitor is formed above the transistor formation region. A step of forming a MOS transistor in an element formation region of a semiconductor substrate, the semiconductor substrate and the MOS
Forming an interlayer insulating film on the transistor, forming a contact hole between the gate electrodes of the adjacent MOS transistors, and storing a diffusion layer and a capacitor of each adjacent MOS transistor on the sidewall of the contact hole. Forming a connection electrode for connecting the electrode.

(3) The connection electrode is connected to the upper surface of the diffusion layer of the MOS transistor.

(4) The connection electrode is connected to the side surface of the diffusion layer of the MOS transistor.

(5) An oxide film is formed on at least the semiconductor substrate below the diffusion layer connected to the capacitor of the MOS transistor.

(6) The semiconductor substrate is an SOI substrate.

(7) An electrode is formed on the side surface of the gate electrode of the MOS transistor via an insulating film, and this electrode is connected to the electrode connecting the capacitor and the MOS transistor.

(8) The semiconductor substrate is a single crystal substrate, an oxide film is formed in the single crystal substrate below the diffusion layer of the MOS transistor, and the oxide film is formed between the connection electrodes. Connected to the insulating film.

(9) The connection electrode is also formed on the interlayer insulating film.

(Operation) In the semiconductor memory device of the present invention, one contact hole is formed between the adjacent gate electrodes arranged according to the minimum rule, and the source / drain diffusion layers of the adjacent transistors are separated at this contact hole portion. A connection electrode for connecting to the storage electrode of the capacitor is connected to each diffusion layer through the contact hole. Therefore, the area of the unit cell can be reduced to 4F ² as compared with the conventional case.

The method of manufacturing a semiconductor memory device according to the present invention is
The storage electrode of the capacitor is formed in a self-aligned manner on the connection electrode connected to the source or drain of the OS transistor.
A semiconductor memory device having ^two unit cells can be provided.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a DRA of a first embodiment of the present invention.
1A is a plan view, FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A, and FIG. 2) is a cross-sectional view of the BB ′ portion of FIG.

In FIG. 1A, a plurality of gate electrodes (word lines) 1 are arranged in parallel. Diffusion layers 2a connected to the capacitors are arranged on the respective sides of the adjacent gate electrodes 1. Two diffusion layers 2b are arranged between the gate electrodes 1 which are not connected to the diffusion layer 2a, and the bit line contact hole 3 covers the half of the diffusion layer 2b.
Is arranged. The area C surrounded by a square is a unit cell, and the area thereof is 4F ² .

In FIGS. 1B and 1C, the element isolation insulating film 5 is formed on the SOI substrate 4 including the support substrate 4a, the oxide film 4b, and the silicon 4c, except for the element formation region of the silicon 4c. . The gate electrode 1 covered with the nitride film 7 is formed on the silicon 4c in the element formation region via the gate oxide film 6. Diffusion layers 2 (2a, 2b) are formed in the silicon 4c at both ends of the gate electrode 1.

An oxide film 8 serving as an interlayer insulating film is formed on the substrate 4 and the nitride film 7. A plug electrode 9 is formed on each of the two diffusion layers 2a between the gate electrodes 1, and an isolation oxide film 10 is formed between the diffusion layers 2a and between the plug electrodes 9 and on the oxide film 4b. The plug electrode 9 is connected to the plug connection electrode 11 on the oxide film 8 above the gate electrode 1.

A bit line 12 is formed on the diffusion layer 2b and the oxide film 8.
Are formed. A nitride film 13 is formed on the bit line 12. Oxide film 8, plug electrode 9, isolation oxide film 10
An oxide film 15 is formed on top of the nitride film 14.

A storage electrode 17 of the capacitor is formed on the plug connection electrode 11 via an electrode 16 in a contact hole formed in the oxide film 15. Oxide film 15
A capacitor dielectric film 18 is formed on the storage electrode 17.

In the conventional DRAM, one storage electrode of the capacitor is formed in one contact hole. However, in the DRAM of this embodiment, two MOSs are formed by the contact hole formed between the gate electrodes 1.
Each diffusion layer 2a of the transistor is separated, and an electrode 9 connected to each diffusion layer 2a and an electrode 11 connected to the storage electrode 17 of the capacitor via the electrode 16 are formed.

Next, regarding the manufacturing process of the memory cell portion of the DRAM of this embodiment, the process sectional views of FIGS. 2 to 7 and FIG.
9 to 9 will be described with reference to the pattern of FIG. 2 to 7, the left side corresponds to the section taken along the line AA 'in FIG. 1A, and the right side corresponds to the section taken along the line BB'. Further, in the patterns of FIGS. 8 and 9, the area D in the figure is shown in FIG.
Region D of.

As shown in FIG. 2A, silicon 4c
Then, in order to define an active region in which an element will be formed later, an element isolation insulating film 5 is formed in a portion other than the active region pattern shown in 25 of FIG. 8A. Here, the method for forming the element isolation insulating film 5 is a selective oxidation method, an RIE method, a method combining them, or a method obtained by modifying them.

Then, a gate oxide film 6 is formed on the substrate 4. Then, the gate electrode (word line) 1 shown in the gate electrode pattern 26 of FIG. 8A is formed. A nitride film 7 is formed on the sides and the top of the gate electrode 1. Then, the diffusion layer 2 (2a, 2b) is formed on the silicon 4c. After that, a nitride film 19 having a thickness of about 5 nm to 10 nm is deposited on the entire surface.

Next, an oxide film 8a (interlayer insulating film) is laminated on the entire surface, and if necessary, the surface is flattened by a reflow method, a CMP method, an RIE etchback method or the like. Then, the plug connection electrode 11 is laminated.

As shown in FIG. 2B, FIG.
In order to form the groove shown in the plug electrode groove pattern 27, a resist is formed on the plug connection electrode 11 in a portion other than the pattern 27. Then, using this resist as a mask, the plug connection electrode 11, the oxide film 8a, and the nitride film 19 are each etched by RIE or the like to form a plug electrode groove (contact hole) 20.

As shown in FIG. 2C, the film thickness is 10 to 3
A plug electrode 9 of about 0 nm is deposited on the entire surface. At this time, the film thickness of the electrode 9 is selected such that the plug electrode groove 20 is not filled.

As shown in FIG. 3D, the plug electrode 9
And the plug connection electrode 11 and the diffusion layer 2a, the element isolation insulating film 5 and the buried oxide film 4b as stoppers,
Etch by RIE. The thickness of the electrode 11 is set so as not to disappear by this etching.
In this way, the two connection electrodes 9 between the gate electrodes 1 are electrically insulated and each is connected to the diffusion layer 2 a and the plug connection electrode 11.

As shown in FIG. 3E, an isolation oxide film 10 is formed by depositing an oxide film up to the top of the plug electrode trench 20. After that, reflow method, CMP method, R
Planarization is performed by an IE etch back method or the like so that the electrode 11 is exposed on the surface.

Here, the element isolation oxide film 5 and the isolation oxide film 1
The respective MOS transistors are separated by 0 and the oxide film 4b.

As shown in FIG. 3 (f), FIG. 8 (b)
A resist 21 having a plug electrode separation pattern 28 shown in is formed, and the electrodes 9 and 11 are selectively etched by RIE using the resist 21 as a mask. This allows
The electrode material commonly connected to the plurality of memory cells in the direction along the word line can be separated for each cell. Further, by combining with CDE, the electrode 9 remaining on the side wall of the groove is completely removed.

As shown in FIG. 4G, the resist 21
Are removed, an oxide film 8b is deposited on the entire surface, the uppermost surface of the groove is filled, and the surface is flattened by a reflow method, a CMP method, an RIE etchback method or the like. At this time, the surface of the plug connection electrode 11 may be exposed once, but again 50 nm
Deposit a degree of oxide film.

As shown in FIG. 4 (h), FIG. 8 (b)
In order to form the contact hole of the bit line contact hole pattern 29 shown in FIG. 3, a resist 22 is formed on the oxide film 8b except the pattern 29, and using the resist 22 as a mask, the RI film using the nitride film 19 as a stopper is formed.
The oxide films 8a and 8b are selectively etched by E.

At this time, due to misalignment of the patterns,
It is assumed that the contact hole 3 overlaps the plug connection electrode 11 (dotted line portion). Therefore, as shown in (i) of FIG. 4, after removing the resist, an insulating film 8c having a thickness of about 10 to 30 nm is deposited, and the insulating film (for example, the nitride film) 8c and the nitride film 19 are etched by RIE. The bit line contact hole 3 and the plug connection electrode 11 are completely insulated and separated on the side wall of the contact hole 3.

As shown in FIG. 5J, the bit line 12
An electrode material to be the above is deposited on the entire surface, and a nitride film 13 is deposited on the bit line 12. Then, a resist shown in the bit line forming pattern 30 of FIG. 9 is formed, and the nitride film 13 and the bit line 12 are sequentially etched by RIE using the resist as a mask.

The lower half of the bit line contact hole 3 overlaps with the diffusion layer 3a of the substrate 4, and the upper half overlaps with the bit line 12 formed on the oxide film 8b. R
By the etching by IE, the height of the bit line 12 on the diffusion layer 2b is sufficiently lowered. As a result, the storage electrode contact hole, which will be described later, is opened in the plug connection electrode
When formed above, it is possible to prevent the bit line 12 from being exposed in the storage electrode contact hole due to misalignment of the pattern.

As shown in FIG. 5K, the bit line 12
An oxide film 8d is deposited so as to fill the contact hole 3. Then, the oxide films 8b, 8c and 8d are etched to expose the surface of the plug connection electrode 11. At this time, if the above etching is performed under the condition that the oxide film is selectively etched by using 8c as the oxide film, the nitride film 13 is not etched even if the resist is not used as a mask, and functions as a mask.

Next, a nitride film 14 having a film thickness of about 10 to 30 nm is formed.
Is deposited. Then, if necessary, an oxide film 15a is deposited and flattened by a reflow method, a CMP method, an RIE etchback method or the like.

As shown in FIG. 6L, the oxide film 15a
A resist 23 is formed on a portion other than the storage electrode contact hole pattern 31 shown in FIG. 9, and the oxide film 15a is selectively etched by RIE using the resist 23 as a mask to form a storage electrode contact hole 24. To do. This etching is performed under the condition that the oxide film is selectively etched so that the etching stops at the nitride film 14.

As shown in FIG. 6M, the resist 23
Are removed, and an oxide film 15b having a thickness of about 10 to 30 nm is deposited. Then, the oxide film 15b is etched by RIE so that the oxide film 15b remains only on the side wall portion of the storage electrode contact hole 24, thereby insulating the bit line 12 from the contact hole 24 or reducing the capacitance. This step can be omitted if not necessary.

Next, the stopper nitride film 14 is etched by RIE to expose the plug connection electrode 11 in the storage electrode contact hole 24. The oxide film 15b may be used as a nitride film, and the above RIE of the sidewall remaining and the RIE of the stopper nitride film 14 may be continuously performed. Since the nitride film 14 is thin, the over-etching time can be shortened and the bit line 12 on the diffusion layer 2b can be prevented from being exposed in the contact hole 24. As a result, the storage electrode contact hole 24 is formed on the plug connection electrode 11 in a self-aligned manner.

As shown in FIG. 7N, the electrode 16 is embedded in the contact hole 24, and the storage electrode 17 of the capacitor and the dielectric film 18 are formed. Further, thereafter, although not shown, a plate electrode of the capacitor is formed. Since this process is the same as the manufacturing process for forming a normal stack type capacitor, its detailed description is omitted.

According to the present invention, the structure of forming the storage electrode above the substrate and the structure of expanding the storage electrode plug on the word line to 1F ² have a unit cell area even if misalignment is assumed. It is possible to realize a DRAM having 4F ² .

(Second Embodiment) FIG. 10 shows a memory cell portion of a DRAM according to a second embodiment of the present invention.
10A is a cross-sectional view taken along the line AA ′ of FIG.
FIG. 10B is a cross-sectional view of the BB 'portion. The feature of the DRAM of this embodiment is that the plug electrode of the DRAM of the first embodiment is connected to the upper part of the diffusion layer,
That is, the plug electrode 9 is connected to the side wall of the diffusion layer 2a.

Using the process sectional view of the DRAM of FIG.
A method of manufacturing the DRAM of this embodiment will be described. In FIG. 11, the left side corresponds to the sectional view taken along the line AA ′ in FIG. 1A, and the right side corresponds to the sectional view taken along the line BB ′.

First, the same steps as in FIGS. 2A to 2B of the first embodiment are performed. Then, as shown in FIG. 11A, the diffusion layer 2a under the plug electrode groove 20 (contact hole) is etched by RIE using the oxide film 4b of the SOI substrate 4 as a stopper to separate the diffusion layer 2a.

As shown in FIG. 11B, the film thickness is 10
A plug electrode 9 having a thickness of about 30 nm is deposited on the entire surface. Electrode 9
The film thickness is set to such an extent that the groove 20 is not filled. Next, the electrode 9 is etched by RIE using the oxide film 4b and the element isolation insulating film 5 as stoppers. The electrode 11 has a film thickness that does not disappear by this etching. This electrically insulates the two electrodes 11 between the gate electrodes 1,
Each of them is connected to the side wall of the diffusion layer 2a.

Since the subsequent steps are the same as the steps from FIG. 3E of the first embodiment, the description thereof will be omitted.

Next, the effect of this embodiment will be described. Since the diffusion layer 2a is etched and separated in the step shown in FIG. 11A, the etching time for separating the electrode 9 is sufficient in the step shown in FIG. 11B. If the side wall of the gate electrode 1 has a certain angle and the etching time is long, the plug electrode 9 formed along the side wall of the nitride film 7 may be scraped by the etching and may be broken. However, in this embodiment, since the etching time for the plug electrode 9 is short, the possibility that the plug electrode is disconnected can be reduced.

In this embodiment, the plug electrode 9 is the diffusion layer 2a.
Connected to the side wall of the plug electrode 9 and the diffusion layer 2
If the interface with a is inside the depletion layer of the substrate 4, junction leakage will increase, so it is desirable to form a high impurity concentration near the interface. This structure is effective under the condition that the high impurity layer is not formed under the gate electrode 1. Meanwhile, the first
This problem is alleviated when the plug electrode is connected to the upper surface of the diffusion layer as in the embodiment.

(Third Embodiment) FIG. 12 is a sectional view of a memory cell portion of a DRAM according to a third embodiment of the present invention. Here, the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The feature of the DRAM of this embodiment is that the side wall of the gate electrode 1 is not formed with a nitride film, and the side wall spacer electrode 33 is formed via the oxide film 32 on the side wall of the gate electrode. Is the plug electrode 9
Is to be used as a part of.

Next, the manufacturing method of this embodiment will be described with reference to process sectional views of FIGS. 13 to 15 and a pattern diagram of FIG. In the process cross-sectional views of FIGS. 13 to 15, the left side corresponds to the cross section taken along the line AA ′ in FIG.
-Corresponds to the cross section of B'section. Area D of the pattern diagram of FIG. 16 corresponds to area D of FIG.

As shown in FIG. 13A, an active region pattern 25 shown in FIG. 16A is formed in order to define an active region in the silicon 4a of the SOI substrate 4, which is a portion for forming an element later. The element isolation insulating film 5 is formed on the other portions. The element isolation insulating film 5 is formed by a selective oxidation method, R
According to the IE method, any combination thereof or modification thereof.

The gate oxide film 6, the gate electrode 1, and the nitride film 7 are sequentially laminated on the entire surface of the substrate 4.
The resist shown in the gate electrode pattern 26 of No. 7 is formed. Using this resist as a mask, the nitride film 7 is etched by RIE until the gate electrode 1 is exposed, and the resist is removed. The gate electrode 1 is etched by RIE using the remaining nitride film 7 as a mask until the substrate 4 is exposed. Next, a thermal oxidation process is performed to form an oxide film 32 on the side wall of the gate electrode 1. And nitride film 7
Silicon as a mask, through the gate oxide film, silicon 4c
A diffusion layer 2 (2a, 2b) is formed on the substrate.

An electrode having a film thickness of about 10 to 30 nm is deposited on the entire surface. After that, the electrode is etched by RIE,
A conductive sidewall spacer electrode 33 is formed on the sidewall of the gate electrode 1 with the oxide film 32 interposed therebetween.

As shown in FIG. 13B, a nitride film 19 of about 5 to 10 nm is deposited on the entire surface. An oxide film 8a is laminated on the entire surface up to the nitride film 7 and if necessary, the surface is flattened by a reflow method, a CMP method, an RIE etchback method or the like. After that, the plug connection electrode 11 is laminated on the entire surface.

As shown in FIG. 13C, in order to form the groove shown in the plug electrode groove pattern 27 of FIG. 16A on the electrode 11, the electrode 11 of the portion other than the pattern 27 is formed.
A resist is formed on top. Using this resist as a mask, the electrode 11 and the oxide film 8a are etched by RIE, and then the nitride film 19 is also etched to form a plug electrode groove (contact hole) 20.

As shown in FIG. 14D, a plug electrode 9 having a film thickness of about 10 to 30 nm is deposited on the entire surface. The film thickness of the plug electrode 9 is set so that the groove 20 is not filled. Then, as shown in FIG. 14E, the electrode 9 and the diffusion layer 2a therebelow are etched by RIE using the oxide film 4b as a stopper. As a result, the two plug electrodes 9 between the gate electrodes 1 are electrically insulated and each is connected to the diffusion layer 2a and the plug connection electrode 11.

As shown in FIG. 14F, an isolation oxide film 10 is deposited, and if necessary, a reflow method, a CMP method, a RI method.
E The surface is flattened by an etch back method or the like. This time,
The surface of the connection electrode 11 is exposed.

As shown in FIG. 15G, a resist 34 is formed on a portion other than the first plug electrode separation pattern 28a shown in FIG. 16A, and the electrode 11 is formed by RIE using the resist 34 as a mask. Selectively etch. Thereby, the plug connection electrode 11 can be separately formed in the direction parallel to the gate electrode 1.

As shown in FIG. 15H, the resist 3
4 is removed, and a resist 35 having the pattern shown in the second plug electrode separation pattern 28b of FIG. 16B is formed. Next, oxide film 8a, isolation oxide film 10, nitride film 1
9, the electrode 9 and the spacer electrode 33 are etched using RIE. As a result, the connection electrode 11 and the conductive sidewall spacer 33 can be separately formed in the direction perpendicular to the gate electrode. Further, by combining with CDE, the electrode material remaining on the side wall is completely removed.

As shown in FIG. 15I, an oxide film 8b is deposited on the entire surface, and the surface is flattened by a reflow method, a CMP method, an RIE etchback method or the like.

Then, the DRAM of the present embodiment is subjected to the same steps as the steps after (h) of FIG. 4 in the first embodiment.
Is formed.

Next, the effect of this embodiment will be described. By utilizing the sidewall spacer electrode 33 as a part of the plug electrode 9, there is an effect that the resistance of the plug electrode 9 does not increase even if the distance between the gate electrodes 1 becomes narrow and the plug electrode 9 becomes thin.

When the side wall of the nitride film 7 of the first embodiment has a certain angle, the plug electrode 9 formed along the nitride film 7 may be broken by etching by RIE. However, in the present embodiment, since the sidewall spacer electrode 33 is also used as the plug electrode, the possibility can be reduced.

(Fourth Embodiment) FIG. 17 is a plan view of a memory cell portion of a DRAM according to a fourth embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The feature of this embodiment is that in the first embodiment, either the capacitors or the bit lines are arranged in a line between the adjacent gate electrodes, whereas the plug is provided between the adjacent gate electrodes 1 (word lines). That is, the diffusion layers 2a connected to the electrodes and the diffusion layers 2b connected to the bit lines are alternately arranged.

The method of manufacturing the DRAM of this embodiment is the same as that of the above-described embodiment except that the pattern is different, and therefore only the pattern is shown and detailed description is omitted. If the pattern shown in FIG. 18 is used, the manufacturing method of the third embodiment can be applied as it is. Further, in order to apply the manufacturing method of the first embodiment, in the step of separating the plug electrodes, the first plug electrode separation pattern 28a of FIG.
The plug electrode separation pattern 28 of (b) may be used.

The present embodiment has an effect that the bit line contact hole pattern 29 of FIG. 18B is easily resolved.

(Fifth Embodiment) FIG. 19 is a plan view of a memory cell portion of a DRAM according to a fifth embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The feature of the DRAM of this embodiment is that
That is, the diffusion layer 2 (2a, 2b) is formed obliquely with respect to the gate electrode 1.

The manufacturing process of this embodiment is the same as that of the first embodiment except for the different pattern, and therefore only the pattern is shown and detailed description is omitted.

20 and 21 show patterns used in manufacturing the DRAM of this embodiment. The same patterns as those in FIGS. 8 and 9 are designated by the same reference numerals, and the description thereof will be omitted.

The bit line pattern 30 shown in FIG. 21B.
Like the diffusion layer, is defined obliquely with respect to the gate electrode, but the region of the plug electrode can be secured by arranging so as to have an angle opposite to that of the diffusion layer. 31
Is a storage electrode contact hole pattern.

In the previous embodiment, the bit line and the diffusion layer were connected by a part of the diffusion layer. On the other hand, in the present embodiment, the design dimension is somewhat strict, but the connection electrode to the bit line is the diffusion layer. Since it can be arranged at the center, there is an effect that a larger margin can be secured against misalignment of patterns.

FIG. 22 shows a second arrangement as a modification of this embodiment ((a) of FIG. 22). With this arrangement, the same effect as that of the DRAM of FIG. 19 can be obtained. This DR
In the case of AM, there is no need to bend the plug electrode separation pattern 28 of FIG. 21A (FIG. 22B), and the plug electrode pattern can be more faithfully resolved.

(Sixth Embodiment) FIG. 23 shows a memory cell portion of a DRAM according to a sixth embodiment of the present invention.
23A corresponds to a sectional view taken along the line AA ′ of FIG. 1A, FIG. 23B corresponds to a sectional view taken along the line BB ′, and FIG. 23C illustrates a pattern diagram. Is. 23 (a) and 23 (b), the same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. Also. In FIG. 23 (c), the same patterns as those in FIG. DRA of the present embodiment
The feature of M is that the silicon single crystal substrate 40 is used as the substrate, the oxide film 41 is formed only under the diffusion layer connected to the storage electrode of the capacitor, and the oxide film is not formed in the channel portion. Region E in FIG. 23C is a region where an oxide film is formed in the substrate.

(Seventh Embodiment) Next, a method of manufacturing an oxide film in a substrate of another DRAM will be described with reference to process sectional views of FIGS. 24 and 25 and a pattern diagram of FIG. 23 (c). . The memory cell of the sixth embodiment described above can also be formed using the method of the present embodiment.

As shown in FIG. 24A, the silicon single crystal substrate 40 is thermally oxidized to form a buffer oxide layer 43. Next, a polysilicon 44 having a film thickness of about 100 to 200 nm, which serves as a stopper for CMP used in the flattening in a later step, is deposited. Next, an oxide film 4 having a film thickness of about 200 nm
5 is deposited.

Trench pattern 4 shown in FIG. 23 (c)
A resist is formed on portions other than 2, and the oxide film 45 is etched by RIE using this resist as a mask to transfer a pattern to the oxide film 45. Next, the resist is removed, and the polysilicon 44 is etched by RIE using the oxide film 45 as a mask. Subsequently, the buffer oxide film 43 is etched by RIE. Further, using the remaining oxide film 45 as a mask, R is applied to the substrate 40.
Etching by IE, depth 200 ~ 300nm
To form a trench.

As shown in FIG. 24B, the film thickness of 20 to
A nitride film 46 of about 40 nm is deposited, and then RIE is performed on the nitride film 46 to remove the nitride film 46 at the bottom of the trench. Next, isotropic etching is performed by CDE,
The silicon substrate 40 is selectively etched. This time,
The etching time is adjusted so that no cavity is connected to the closest trench.

As shown in FIG. 25 (c), thermal oxidation is performed to form an oxide film 41a on the side wall of the cavity in the substrate 40.

As shown in FIG. 25D, the nitride film 46 is
Are removed, an oxide film 41b is deposited, and the oxide film 41b is embedded in the cavity and the trench. At this time, since the size of the cavity formed by the CDE in the plane is larger than the size of the trench in the plane, the trench is filled with the oxide film 41b during the deposition of the oxide film 41b. Has a portion where the oxide film 41b is not buried. Therefore, in order to completely fill the cavity with the oxide film 41b, the oxide film 41b in the trench is etched by RIE to expose a portion of the cavity where the oxide film 41b is not buried, and then the oxide film 41b is deposited again. if,
The oxide film 41b can be completely embedded in the cavity.
After that, the oxide films 41b and 45 are etched back by the RIE method,
Alternatively, flattening is performed by the CMP method.

A DRA having a layout of 4F ² is obtained by combining the above steps with the embodiment described above.
M can be realized. Of course, it is also applicable to layouts that are looser than 4F ² .

The formation of the oxide film in the substrate is
It may be before or after the step of forming the element isolation insulating film. Further, it may be performed after forming the gate electrode (word line) of the MOS transistor.

Next, the effect of this embodiment will be described. As shown in FIG. 23C, the MOS between the closest trenches 42.
An oxide film is formed under the source and drain of the transistor, but no oxide film is formed in the channel portion equidistant from the four trenches.

The source and drain of this MOS transistor have a junction area smaller than that of an ordinary single crystal substrate, and the charge retention performance is improved. Further, since the oxide film is not formed below the channel portion, there is no disadvantage due to the substrate floating effect, for example, there is no problem that the potential of the body rises due to the accumulation of holes and the off leak increases.

Further, in this embodiment, the step of forming the SOI substrate itself can be omitted or simplified, which leads to cost reduction.

The present invention is not limited to the above embodiment. For example, in addition to forming the bit line before forming the bit line, that is, below the capacitor, it can be applied to the bit line forming process after forming the bit line after the capacitor, that is, above the capacitor. Is. In this case, it is also possible to adopt a configuration in which the storage electrode of the capacitor is directly connected to the connection electrode formed on the side wall of the contact hole. This structure is shown in FIG.
In this figure, 18 'is a capacitor insulating film, 11' is a plate electrode, 12 'is a bit line, 15' and 15 "are interlayer insulating films, 3'is a bit line contact, and 8c 'is a bit line contact sidewall insulating film. Is.

Further, in all the above-mentioned embodiments, if a nitride film is directly formed on silicon, distortion occurs. Therefore, a nitride film 19 is formed on silicon via an oxide film, but it is omitted here.

In addition, various modifications can be made without departing from the scope of the present invention.

[0097]

In the semiconductor memory device of the present invention, two connection electrodes for connecting the source or drain of each MOS transistor and the storage electrode of the capacitor are provided between the gate electrodes of adjacent MOS transistors. It is possible to provide a DRAM in which the unit cell area is 4F ² .

In addition, in the method of manufacturing the semiconductor memory device of the present invention, the step of forming the connection electrode having a large area above the gate electrode of the MOS transistor is included, so that even if the deviation of the pattern is taken into consideration, the unit A DRAM having a cell area of 4F ² can be manufactured.

[Brief description of drawings]

FIG. 1 is a diagram showing a DRAM according to a first embodiment.

2A to 2C are process cross-sectional views of the DRAM of FIG.

3A and 3B are process cross-sectional views of the DRAM of FIG.

FIG. 4 is a process sectional view (3) of the DRAM of FIG.

FIG. 5 is a sectional view (4) of the process of the DRAM of FIG.

6A and 6B are process cross-sectional views of the DRAM of FIG.

FIG. 7 is a process cross-sectional view (6) of the DRAM of FIG.

FIG. 8 is a diagram (1) showing a pattern when the DRAM of FIG. 1 is formed.

FIG. 9 is a diagram (2) showing a pattern when the DRAM of FIG. 1 is formed.

FIG. 10 is a sectional view of a DRAM according to the second embodiment.

FIG. 11 is a process cross-sectional view of the DRAM of FIG.

FIG. 12 is a sectional view of a DRAM according to a third embodiment.

FIG. 13 is a process cross-sectional view (1) of the DRAM of FIG.

FIG. 14 is a process sectional view (2) of the DRAM in FIG. 12;

FIG. 15 is a process cross-sectional view (3) of the DRAM of FIG.

16 is a diagram showing a pattern when the DRAM of FIG. 12 is formed.

FIG. 17 is a plan view of a DRAM according to the fourth embodiment.

FIG. 18 is a pattern diagram (1) when the DRAM of FIG. 17 is formed.

FIG. 19 is a plan view of a DRAM according to the fifth embodiment.

FIG. 20 is a diagram (1) showing a pattern when the DRAM of FIG. 19 is formed.

FIG. 21 is a view showing a pattern when the DRAM of FIG. 19 is formed (2)

FIG. 22 is a plan view of a DRAM according to the fifth embodiment.

FIG. 23 is a view showing a DRAM according to the sixth embodiment.

FIG. 24 is a process sectional view (1) of the substrate portion of the DRAM of FIG. 23;

FIG. 25 is a process sectional view (2) of the substrate portion of the DRAM of FIG. 23;

26A and 26B are a plan view and a cross-sectional view of a DRAM in a post-bit line manufacturing process.

FIG. 27 is a diagram showing a conventional DRAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Gate electrode (word line) 2 ... Diffusion layer 3 ... Bit line contact hole 4 ... SOI substrate 4a ... Support substrate 4b ... Oxide film 4c ... Silicon 5 ... Element isolation insulating film 6 ... Gate oxide film 7 ... Nitride film 8 ... Oxide film 9 ... Plug electrode (connection electrode) 10 ... Isolation oxide film 11 ... Plug connection electrode (connection electrode) 12 ... Bit line 13 ... Nitride film 14 ... Nitride film 15 ... Oxide film 16 ... Electrode 17 ... Storage electrode 18 ... Dielectric Body film 19 ... Nitride film 20 ... Plug electrode contact holes 21, 22, 23 ... Resist 24 ... Storage electrode contact hole 25 ... Diffusion layer forming pattern 26 ... Gate electrode pattern 27 ... Plug electrode groove pattern 28 ... Plug electrode separation pattern 29 ... bit line contact hole pattern 30 ... bit line pattern 31 ... storage electrode contact hole pattern 32 ... acid Film 33 ... sidewall spacer electrodes 34, 35 ... resist 40 ... silicon single crystal substrate 41 ... oxide film 42 ... trench pattern 43 ... buffer oxide film 44 ... polysilicon 45 ... oxide film 46 ... nitride film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 21/336

Claims (2)

[Claims] 1. A semiconductor memory device in which memory cells each comprising a MOS transistor and a capacitor are two-dimensionally arranged on a semiconductor substrate, and a storage electrode of the capacitor is formed above a formation region of the transistor. One contact hole is formed between the gate electrodes of the MOS transistors adjacent to each other in the cell, the source / drain diffusion layers of the MOS transistors adjacent to each other are separated from each other in the contact hole portion, and the storage electrode is formed in each diffusion layer. A semiconductor memory device, characterized in that a connection electrode for connecting with is connected. 2. A method of manufacturing a semiconductor memory device, wherein memory cells each comprising a MOS transistor and a capacitor are two-dimensionally arranged on a semiconductor substrate, and a storage electrode of the capacitor is formed above a formation region of the transistor. A step of forming a MOS transistor in an element formation region of a semiconductor substrate; a step of forming an interlayer insulating film on the semiconductor substrate and the MOS transistor;
A step of forming a contact hole between the gate electrodes of the S-transistors, and a step of forming a connection electrode connecting a diffusion layer of each of the adjacent MOS transistors and a storage electrode of a capacitor on a sidewall of the contact hole. And a method for manufacturing a semiconductor memory device.