JPH09260483A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A field shield element isolation structure with reduced steps is realized. A thick field oxide film is formed in an element isolation region on a silicon substrate, the field oxide film is removed to form a recess, and a field shield element isolation structure is formed in the recess. [Effect] Unlike the buried type field shield element isolation structure, it is possible to reduce the step difference between the element formation region and the element isolation region surface while suppressing the leak current from the gate oxide film 5 and the sidewall 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is particularly suitable for application to, for example, formation of an element isolation structure by a field shield element isolation method.

[0002]

2. Description of the Related Art Conventionally, a field shield method has been known as one of element isolation technologies. In this field shield method, generally, as shown in FIG. 2, a gate oxide film 25 is formed on a silicon substrate 1, and a shield gate electrode 23 and a CVD oxide film 24 as a cap insulating film are formed in an element isolation region. Usually, a thermal oxide film (not shown) is formed on the side surface of the shield gate electrode 23 in order to suppress the leakage current from the side surface of the shield gate electrode 23, and further, a CVD oxide film is deposited and then a side surface is formed by anisotropic etching. The wall insulating film 28 is formed to form the field shield element isolation structure 21, and element isolation is performed by applying a fixed potential to the shield gate electrode 23.

In the above-mentioned conventional general field shield method, since the field shield element isolation structure 21 having a laminated structure is formed on the silicon substrate 1, for example, the gate electrode structure 10 of the transistor in the element formation region is formed.
And the gate wiring structure 20 on the field shield element isolation structure 21 has a height difference of 5000 Å or more. As a result, with the miniaturization of elements, fine processing after forming the field shield element isolation structure 21 such as contact holes. Has become difficult.

On the other hand, as a method for reducing such height difference, as shown in FIG. 4, a buried field shield method in which a shield gate electrode 43 and an oxide film 44 are buried in a silicon substrate 1 has been proposed. In the case of this embedded field shield method, as shown in FIG. 5, the silicon substrate 1 is dug down by dry etching to form the groove 5
It is general that the field shield structure is formed by forming 1 and forming the oxide film 44 and the shield gate electrode 43 in the groove 51. Reference numeral 50 is a resist film.

[0005]

However, in the above-mentioned embedded field shield method, since the silicon substrate 1 is dug down by dry etching, the silicon substrate 1 is formed in the element isolation region due to etching damage caused in the element isolation region. There is a problem that the leak current from the oxide film 44 increases.

On the other hand, in the case of the conventional general field shield method as shown in FIG. 2, unlike the ideal shape shown in FIG. 2, in practice, as shown in FIG. When the silicon thermal oxide film 37 is formed on the side surface of the gate electrode 23, the CVD oxide film 24 is scraped by pre-cleaning, the CVD oxide film 24 is contracted by thermal stress during thermal oxidation, and further,
The growth of the thermal oxide film 37 on the side surface of the shield gate electrode 23 causes the shield gate electrode 23 and the CVD oxide film 2 to grow.
There was a level difference D between No. 4 and No. 4. And in this state,
After that, a CVD oxide film is deposited on the shield gate electrode 23 and the CVD oxide film 24, and anisotropic etching is performed to form the sidewall insulating film 38. Then, as shown by A in FIG. There is a problem that a thin film portion is locally formed at 38 and the leak current increases from that portion.

Therefore, an object of the present invention is to alleviate the height difference between the element formation region and the element isolation region, which has been a problem in the conventional general field shield method, and to eliminate the difference from the oxide film formed in the element isolation region. It is an object of the present invention to provide a semiconductor device capable of reducing a leak current and a manufacturing method thereof.

[0008]

A method of manufacturing a semiconductor device according to the present invention comprises a first step of forming a field oxide film having a predetermined thickness in an element isolation region on a semiconductor substrate, and removing the field oxide film. A second step of forming a recess in the element isolation region of the semiconductor substrate, a third step of forming an oxide film on the surface of the semiconductor substrate in the recess, and polycrystalline silicon on the oxide film. A fourth step of sequentially forming a film and a first insulating film, a fifth step of processing each of the polycrystalline silicon film and the first insulating film into a pattern of a shield gate electrode, and on the element isolation region A sixth step of forming a second insulating film on the first insulating film, and anisotropically etching the second insulating film to process the polycrystalline silicon film and the first insulating film processed into the pattern of the shield gate electrode. The second side of the membrane And a seventh step of forming a side wall made from the edge membrane.

In one aspect of the present invention, after the fifth step,
The method further includes the step of thermally oxidizing both side surfaces of the polycrystalline silicon film processed into the pattern of the shield gate electrode.

The semiconductor device of the present invention is a semiconductor substrate and a recess formed in the surface portion of the semiconductor substrate in the element isolation region, and the side surface extending from the upper edge portion to the bottom surface extends from the bottom surface to the upper edge portion. And a sloping recess to open
A gate oxide film formed on the surface of the semiconductor substrate in the recess, a shield gate electrode formed on the gate oxide film, a cap insulating film formed on the shield gate electrode, the shield gate electrode, and And a sidewall insulating film formed so as to fill the recess from the side surface of the cap insulating film.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described with reference to FIG. 1 according to a preferred embodiment.

First, as shown in FIG. 1A, a normal L
Similar to the case of the OCOS method, selective oxidation is performed in a pyro atmosphere at a temperature of 1000 ° C. to form a field oxide film 2 having a film thickness of about 5000 Å in a portion to be an element isolation region of the silicon substrate 1.

Next, as shown in FIG. 1 (b), 2.5%
The field oxide film 2 is removed by wet etching using HF, and a recess 12 is formed in a portion of the silicon substrate 1 which will be an element isolation region. At this time, plasma damage, which is a problem in dry etching, does not occur on the surface of the silicon substrate 1 after wet etching. Also, the recess 12
Reflecting the shape of the field oxide film 2 having a bird's beak, the cross-sectional shape of is inclined so that the side surface extending from the upper edge portion to the bottom surface is opened from the bottom surface toward the upper edge portion as shown in the figure.

Next, as shown in FIG. 1C, the recess 12 is formed.
After forming a silicon oxide film 5 to be a gate oxide film with a film thickness of about 400Å in a pyro atmosphere at a temperature of 900 ° C. on the surface of the silicon substrate 1 including the inside, CVD (chemical vapor deposition)
By the technique, a polysilicon film 3 doped with impurities at a temperature of 580 ° C. is deposited to about 2000 Å, and further on the polysilicon film 3 by the CVD technique, a temperature of 675 ° C.
Then, a CVD silicon oxide film 4 of about 3000 Å is deposited.

Next, as shown in FIG. 1D, the CVD silicon oxide film 4 is processed into a pattern of the shield gate electrode by using the resist pattern 9 as a mask by the photolithography technique and the anisotropic etching technique. The anisotropic etching process at this time uses, for example, a parallel plate type etching chamber and CF ₄ / CHF ₃ / Ar = 6.
The condition is 0/60/800 sccm, 500 mTorr, and 750 W.

Next, as shown in FIG. 1E, after removing the resist pattern 9, the polysilicon film 3 is anisotropically etched using the CVD silicon oxide film 4 as a mask to shield the polysilicon film 3. Process into the shape of the gate electrode. The anisotropic etching process at this time uses, for example, a parallel plate type etching chamber and He / HBr.
/ Cl ₂ = 400/15 / 200sccm, 425mTo
rr, 225W.

Next, as shown in FIG. 1F, the side surface of the polysilicon film 3 is thermally oxidized for 30 minutes in an O ₂ atmosphere at a temperature of 900 ° C. using a diffusion furnace. At this time, a thermal oxide film 6 having a thickness of about 200Å is formed on the side surface of the polysilicon film 3. At the same time, the patterned CVD as described above
The silicon oxide film 4 contracts in the vertical and horizontal directions due to the thermal stress during the thermal oxidation at this time, and as a result, as shown in the figure, the width between the polysilicon film 3 and the CVD silicon oxide film 4 is about 1 mm.
A step D _{1 of} 50Å occurs.

Next, as shown in FIG. 1G, a CVD silicon oxide film 7 having a thickness of about 2500 Å is deposited on the entire surface by the CVD technique, and then the CVD silicon oxide film 7 is formed by the anisotropic dry etching technique. Etch back, Figure 1
As shown in (h), a sidewall (sidewall insulating film) 8 is formed in which the recess 12 is filled in from the side surface of the polysilicon film 3 which is the shield gate electrode and the CVD silicon oxide film 4 which is the cap insulating film thereof. .

In the above-mentioned example, the same method as the conventional LOCOS (local oxidation of silicon) method was used to form the thick field oxide film 2 in the element isolation region on the silicon substrate 1, but the so-called PBL ( The same method as the modified LOCOS method such as the polybuffered LOCOS method may be used.

[0020]

According to the present invention, the leakage current from the gate oxide film or the side wall of the shield gate electrode formed in the element isolation region is suppressed, and the height between the element formation region surface and the element isolation region surface is reduced. Since the difference can be alleviated, it is possible to facilitate fine processing after forming the element isolation region and reduce the power consumption of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a conventional general field shield element isolation structure.

FIG. 3 is a schematic cross-sectional view showing a problem of a conventional general field shield element isolation structure.

FIG. 4 is a schematic cross-sectional view showing an embedded field shield element isolation structure.

FIG. 5 is a schematic cross-sectional view showing a method for forming a buried field shield element isolation structure.

[Explanation of symbols]

 1 silicon substrate 2 field oxide film 3 polysilicon film (shield gate electrode) 4 CVD silicon oxide film (cap insulating film) 5 silicon oxide film (gate oxide film) 6 thermal oxide film 7 CVD silicon oxide film 8 sidewall (sidewall insulation) Membrane) 12 recess

Claims (3)

[Claims] 1. A first step of forming a field oxide film having a predetermined thickness in an element isolation region on a semiconductor substrate, and removing the field oxide film to form a recess in the element isolation region of the semiconductor substrate. A second step of forming an oxide film on the surface of the semiconductor substrate in the recess, and a fourth step of sequentially forming a polycrystalline silicon film and a first insulating film on the oxide film. A fifth step of processing the polycrystalline silicon film and the first insulating film into a shield gate electrode pattern, and a sixth step of forming a second insulating film on the element isolation region; A sidewall formed of the second insulating film on a side surface of the polycrystalline silicon film and the first insulating film processed into the pattern of the shield gate electrode by anisotropically etching the second insulating film. The seventh to form And a method of manufacturing a semiconductor device. 2. The semiconductor according to claim 1, further comprising a step of thermally oxidizing both side surfaces of the polycrystalline silicon film processed into the pattern of the shield gate electrode after the fifth step. Device manufacturing method. 3. A semiconductor substrate and a concave portion formed in a surface portion of the semiconductor substrate in an element isolation region, the side surface extending from the upper edge portion to the bottom surface is inclined so as to open from the bottom surface toward the upper edge portion. A recess, a gate oxide film formed on the surface of the semiconductor substrate in the recess, a shield gate electrode formed on the gate oxide film, a cap insulating film formed on the shield gate electrode, A semiconductor device comprising: a shield gate electrode and a sidewall insulating film formed so as to fill the concave portion from a side surface of the cap insulating film.