JPH09252172A - Ceramic interconnection board forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an anodic oxide film having a specified thickness and tightly fix by castellation by making a current flow through a plated base layer to apply the anodic forming to a part of a thin film layer exposed through openings of a masking layer to form a dielectric layer. SOLUTION: A current is fed to openings through plating base layers 20 and 22 to form a Cu-Ni plated layer 28 having a dielectric layer to be a lower electrode layer of a capacitor. A potential is applied through a Ti sputtered layer 20 with a Ta sputtered layer 32 set to be positive, to anodic-oxidize specified thickness of the Ta layer 32 exposed through openings 36A of a mask 36 to change to a tantalum oxide, thus forming a dielectric layer 32a. Thus it is possible to form a dielectric layer by the anodic-forming at an accurate thickness and tightly fix it to a ceramic interconnection board.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a ceramic wiring board, and more particularly to a method for forming a ceramic wiring board in which a dielectric layer is formed on a substrate by anodizing.

[0002]

2. Description of the Related Art As shown in FIG. 7, a module substrate 110 such as an amplifier used in the field of information and communication is fixed on a substrate 180 with solder 116 via a semi-cylindrical castellation 112. is there. As shown in FIG. 8, the module substrate 110 is obtained by forming a resistor, an inductance, a capacitor, etc. on a ceramic substrate 90 for multi-cavity in which a through-hole 14 for castellation for forming a castellation is formed. It is manufactured by cutting along the through-hole 14 for castellation along a cutting line C indicated by a chain double-dashed line in the figure.

[0003] In forming a capacitor or the like to the ceramic substrate 90 is, for example, previously formed the Ta film layer, which was oxidized by anodic oxidation or anodic chemical conversion tantalum oxide (TaO, Ta ₂ 0 ₅ ) The dielectric layer of the capacitor is provided by forming a film.

The formation of the dielectric layer by this anodic oxidation method will be described with reference to FIG. FIG. 9 shows each step of forming the dielectric layer. First, as shown in FIG. 9A, a Ti layer 120 and a Cu layer 122, which will be a plating underlayer, are formed on the surface (upper side in the drawing) of the ceramic substrate 90 by sputtering. Next, as shown in FIG. 9B, a resist 124 is applied to the ceramic substrate 90 and then exposed and developed to provide an opening 124A having a desired pattern. After that, the plating base layer (Ti layer) 12 is applied to the opening 124A.
9 (C) by passing a current through 0 and (Cu layer) 122, plating Cu and then Ni.
As shown in FIG. 5, a Cu-Ni plated 128 layer which will be the lower electrode of the capacitor is formed. Then, as shown in FIG. 9D, after removing the resist 124, the Cu sputtered layer 1 is formed.
22 is removed, leaving only the Ti sputtered layer 120.

Subsequently, as shown in FIG. 9 (E), Cu
Forming the Ta sputter layer 132 on the Ni plating layer 128. Thereafter, as shown in FIG. 9F, a resist layer 136 is applied and developed to form an opening 136A on the Ta sputter layer 132. Then, as shown in FIG. 9G, masking 172 is applied to the castellation through-holes 14 and the end portions of the ceramic substrate 90 (not shown),
A sticker 174 is attached to the back surface of the ceramic substrate 90.

After that, the ceramic substrate 90 is dipped in a chemical conversion treatment solution of about 0.01% citric acid, and a potential is applied through the Ti sputter layer 120 so that the Ta layer 132 side becomes positive, and the masking 136 is performed. The Ta layer 132 exposed from the opening 136A is subjected to anodization to change it into a tantalum oxide layer having a desired thickness (not shown).
Then, a Ti-Cu layer is formed on the tantalum oxide layer by sputtering, and then a Cu-Ni-Au plating layer (not shown) is formed on the Ti-Cu layer.
A thin film capacitor is completed by etching the i layer.

When a dielectric layer is formed on a substrate by an anodic oxidation method, if a metal portion is exposed in a portion other than the portion to be the dielectric layer, a current flows in this portion, and the dielectric layer is exposed. Since such a problem that the film thickness becomes thin occurs, the masking 136 is applied as described above with reference to FIG. 9F to prevent this. Also, the castellation through holes 14
Also, by providing the masking 172, the leakage current was prevented.

[0008]

However, even if the castellation through hole 14 is carefully masked, the boundary between the castellation through hole 14 and the masking 172 is not sufficiently insulated.
That is, a portion having low dielectric strength remains. Here, in the chemical conversion treatment, when a voltage of several 100 V is applied, dielectric breakdown occurs in a portion where the insulation is not sufficiently taken,
Leakage current may flow. Further, if the masking is insufficient or peeling occurs, a large leakage current flows. Further, the work of carefully masking the through-holes 14 for castellation is time-consuming, and it also takes time to remove the masking after the anodizing treatment.

Further, as described above, the leakage current (current leakage)
Occurs, the accuracy of the thickness of the dielectric layer (anodized layer) of tantalum oxide becomes unstable, and the desired capacitance cannot be obtained, or when the thickness of the dielectric layer is thin. In some cases, dielectric breakdown occurred in the capacitor.

That is, in the chemical conversion treatment, the current is not applied while measuring the thickness of the anodic oxide layer, but in general, voltage-current is applied according to a preset profile so that a predetermined thickness can be obtained. Because there is. Therefore, if a part of the current that should flow through the anodized layer leaks through another unnecessary portion, the process is terminated when the target amount of current is passed, and the anodized layer is thin. At that point, the process ends. Furthermore, when the leakage current is large, a voltage having a desired value may not be applied depending on the capacity of the power supply device.

Since the oxide film is formed by chemical conversion, the anodized layer has a property that the resistance value increases as the chemical conversion treatment progresses when viewed from the power source side. On the other hand, the unnecessary portion, for example, the exposed portion of the Cu—Ni plating, is not oxidized by the chemical conversion treatment, so that the resistance value remains constant and low.
Therefore, the leakage current, which is not so large at the beginning of the process, becomes a large value because the resistance value of the unnecessary portion becomes relatively low as the chemical conversion process progresses. That is, as described above, in order to accurately control the thickness of the anodized layer by the voltage-current profile, it was necessary to prevent leakage current.

As one of the methods for solving this problem, Japanese Patent Application Laid-Open No. 49-86862 proposes a method for preventing a leakage current when performing a chemical conversion treatment. In the examples of this publication, there is a method in which Ta is sputtered on the entire surface of a substrate such as silicon, the Ta on the peripheral portion of the substrate where leakage current is likely to occur is removed, and then a resist is applied to perform chemical conversion treatment. It is disclosed.

However, when a ceramic substrate having a rough surface is used, it is necessary to form a conductive layer under the Ta layer by plating, and therefore the above method cannot be applied as it is. That is, as in the above-mentioned Japanese Patent Laid-Open No. 49-86862, when a capacitor is provided on a silicon substrate having a smooth surface, Ta for forming a dielectric layer is used.
Although the layer can be disposed directly on the silicon substrate,
When the Ta layer is directly provided on the ceramic substrate having a rough surface, the dielectric layer also has irregularities, so that the dielectric layer cannot maintain insulation between the upper and lower electrode layers. Therefore, as described above with reference to FIGS. 9C and 9D, Cu-Ni is plated by plating so that the Ta layer has a relatively large thickness and the upper surface is flat. Layer 1
It is essential to form 28.

A problem peculiar to a ceramic wiring board occurs when the conductive layer under the Ta layer is formed by this plating. That is, as shown in FIG.
When a Ti layer 120 and a Cu layer 122 to be a plating underlayer are formed on the entire surface of the substrate by sputtering, as shown in the drawing, the end Ti layer 120a and the end Ti layer 120a are formed so as to extend into the castellation through holes 14 as well. Cu layer 122a
Is formed. Here, when a lower electrode layer (Cu-Ni layer) 128 below the Ta layer is formed by plating after forming a resist 124 in a necessary portion as shown in FIG. 9C, the through hole for castellation is formed. Since the resist 124 is not applied to the portion that wraps around the inner surface 14, it is exposed from the resist 124, and the end Ti layers 120a and Cu are exposed.
Plating 176 is formed on layer 122a. Where Cu
To remove the -Ni plating 176, the lower electrode 128 is covered with a resist, and etching is further performed.

By the way, as in the above-mentioned JP-A-49-86862, after the Ta layer 132 shown in FIG. 9E is formed, the Ti around the castellation through-hole 14 which causes a leakage current is generated. By removing the layer 120 and the Cu layer 122, the leakage current in the castellation through-hole 14 can be prevented. However, as described above, the lower electrode layer (Cu—Ni layer) 128 below the Ta layer is used.
When plating is formed by plating, plating 176 is also formed in the castellation through-hole 14. Originally,
After the formation of the dielectric layer, for example, sputtering of Ti—Cu or the like and plating of Cu—Ni—Au or the like are applied to the through holes 14 for castellation, and then the cutting line is formed as shown in FIG. Cut along C and become castellation. Here, as described above with reference to FIG. 7, the module substrate 110 is formed by soldering the castellation 112 to the wiring substrate 180.
It is fixed and the connection is made.

However, if the plating 176 shown in FIG. 9 remains in the through-hole 14 for the castellation forming the castellation 112 as described above, sputtering of Ti--Cu or the like on the plating, and Cu-N
Since i-Au or the like is plated, the sputtered layer and the plated layer cannot have the predetermined adhesive strength to the ceramic substrate 90. Therefore, the wiring board 1
In some cases, the module substrate 110 fixed to 80 was not able to maintain a predetermined fixing strength and was peeled off.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to form an anodic oxide film to a predetermined thickness and to firmly fix it by castellation. It is to provide a method for forming a ceramic wiring board.

[0018]

To achieve the above object, in the method for forming a ceramic wiring board according to claim 1, the surface of the ceramic substrate having at least one of a convex portion, a concave portion and a through hole on the substrate surface. A step of disposing the plating underlayer on the plating underlayer, and a step of removing at least the plating underlayer disposed in the side surface of the convex portion, the side surface of the concave portion or in the through hole; A step of forming a lower electrode layer at a predetermined position by electrolytic plating, a step of disposing a thin film layer of a substance to be a dielectric substance on the lower electrode layer by anodization, and an opening at a predetermined portion of the thin film layer. And a step of forming a dielectric layer by anodizing at least a part of the thin film layer exposed from the opening of the masking layer by passing a current through the plating underlayer. Has, And technical, characterized in that.

Further, in claim 2, in claim 1,
The technical feature is that the through hole is a through hole for castellation, and the ceramic substrate is a ceramic substrate having the through hole for castellation.

[0020]

In the present invention, since the plating underlayer formed on the side surfaces of the projections and depressions on the surface of the substrate and around the inside of the through hole is removed in advance, a current is passed through the plating underlayer to carry out electrolytic plating. Thus, when forming the lower electrode, the side surfaces of the protrusions and recesses and the through holes are not plated. Also,
Since the plating underlayer on the side surfaces of the protrusions and depressions and in the through holes is removed, the substance that forms a thin film by passing an electric current through the thin film layer formed on the lower electrode layer is converted into a dielectric substance by anodizing. In doing so, it is not necessary to mask the convex portions, the concave portions and the through holes.

According to the second aspect of the invention, the through holes for castellation are not plated. Therefore, when the ceramic wiring board is fixed to the substrate by soldering the castellation, the ceramic wiring board can be firmly fixed.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments embodying the present invention will be described below with reference to the drawings. A ceramic wiring board according to an embodiment of the present invention includes a ceramic substrate on which capacitors, resistors, and inductances are formed, and is fixed on a printed circuit board by soldering a castellation formed on a side surface of the ceramic substrate. .

As shown in FIG. 8, the ceramic wiring board 10 has a ceramic substrate 90 (105 mm × 95 mm, thickness 0) having a castellation through hole 14 for forming a castellation. .635m
After forming a resistor, an inductance, a capacitor, etc. on m), it is manufactured by cutting along the castellation through hole 14 along a cutting line C shown by a two-dot chain line in the drawing.

Here, the ceramic substrate 9 according to the embodiment
Fig. 1 shows the process of forming a capacitor to 0
This will be described with reference to FIGS. 1 to 3 show a part of the AA cross section of the ceramic substrate 90 shown in FIG. First, as shown in FIG. 1 (A), a ceramic substrate 90 having a large number of castellation through holes 14 of φ0.5 mm shown in FIG. The Ti layer 20 and the Cu layer 22 are formed by sputtering. This serves as a plating base layer for forming the lower electrode layer of the capacitor by plating, and at the time of this sputtering, the end Ti layers 20a, Cu are also sneak into the through holes 14 for castellation.
A layer 22a is formed.

After that, the photoresist 23 is uniformly applied to the ceramic substrate 90, and then the periphery of the through hole 14 for castellation is exposed and developed to form the opening 23A, as shown in FIG. 1B. Then, by etching with an etching solution, as shown in FIG. 1C, the Ti layers 20, 20a and Cu exposed from the opening 23A are exposed.
The layers 22 and 22a are removed. Subsequently, the photoresist 23 is peeled off as shown in FIG. Next, after the photoresist 24 is uniformly applied to the ceramic substrate 90, a portion where a capacitor is to be formed is exposed and developed to form an opening 24A as shown in FIG. This is because the lower electrode layer of the capacitor is formed by plating.

After that, as shown in FIG. 2F, the plating underlayer (Ti layer) 20 and (Cu layer) 2 are introduced into the opening 24A.
A current is passed through 2 to serve as the lower electrode layer of the capacitor, and Cu (10 μm) -Ni (1 μm) that carries the dielectric layer
m) The plated layer 28 is formed. Then, as shown in FIG. 2G, after removing the resist 24, the Cu layer 22 in a portion other than directly below the Cu—Ni plating layer is removed, and the Ti layer 2 is removed.
Leave only 0.

After that, Ta for forming a dielectric layer by anodic oxidation is partially sputtered on the Cu-Ni plated layer (lower electrode layer) 28 by using a metal mask (not shown). As shown in (H), a Ta sputter layer 32 is formed. Next, in order to electrically separate the periphery and the inside of the ceramic substrate 90, as shown in the plan view of the ceramic substrate 90 shown in FIG. 4, the periphery of the substrate is etched into a frame shape by etching. 90 indicated by halftone dots in the figure
Part A shows a part where the Ti layer 20 is removed by etching and the surface of the ceramic substrate 90 is exposed. This etching is also performed by exposure and development.

Subsequently, after applying the resist layer 36,
As shown in FIG. 2 (I), an opening 36A to be a window for anodic oxidation is formed on the Ta sputter layer 32 by exposure.
Here, the BB cross section after the resist layer 36 is applied to the ceramic substrate 90 shown in FIG.
It shows in (B).

After that, the ceramic substrate 90 is dipped in a chemical conversion treatment solution of about 0.01% citric acid, and the potential is adjusted so that the Ta sputter layer 32 side becomes positive.
0, and anodize the Ta layer 32 exposed from the opening 36A of the masking 36 by a predetermined thickness to change it to tantalum oxide (TaO, Ta ₂ O ₅ ).
As shown in FIG. 2J, the dielectric layer 32a is formed.

The current-voltage control profile during this anodic oxidation will be described with reference to FIG. Note that this profile has a desired thickness of the dielectric layer 32a.
It is created based on the result of the experiment so that First, the chemical conversion treatment is started with the current kept constant.
Initially, the voltage is low because the thickness of the dielectric layer is thin and the resistance value is low, but the voltage gradually increases as the thickness of the dielectric layer increases and the resistance value increases with the passage of time. .

After passing a predetermined amount of current, the constant current control is switched to the constant voltage control. This is for keeping the voltage lower than the maximum allowable voltage of the power supply device for applying the voltage and for suppressing the voltage to be equal to or lower than the withstand voltage of the applied masking 36 shown in FIG. If this voltage constant control is continued, the amount of current gradually decreases as the film thickness of the dielectric layer 32a increases, and when the current is stopped by passing a set amount of current, the desired thickness is obtained. The dielectric layer 32a is formed.

Then, after removing the masking 36 as shown in FIG. 3K, a Ti layer 40 and a Cu layer 42 are provided on the dielectric layer 32a by sputtering as shown in FIG. 3L. Further, a Cu layer 44, a Ni layer 46, and an Au layer 48 are provided as an upper electrode layer by plating, and the Ti layer 20 in an unnecessary portion is etched to complete a thin film capacitor.

Then, as shown in FIG. 3 (M), sputtering is performed from the front surface and the back surface of the ceramic substrate 90 to form Ti in the castellation through holes 14.
A layer 41 and a Cu layer 43 are provided. Then, a Cu layer 45, a Ni layer 47, and an Au layer 49 are provided on the Cu layer 43 in the castellation through hole 14 by plating.
Although detailed description is omitted, the resistance is formed by a known technique together with the capacitor, and the inductance is formed by arranging the wiring. Thereafter, the ceramic wiring board 10 as shown in FIG. 6 is cut into 6 pieces by cutting the ceramic substrate 90 on which the capacitors, resistors, and inductances have been formed along the cutting line C described above with reference to FIG. Complete.

FIG. 6A is a perspective view of the upper surface of the ceramic wiring board 10, and FIG. 6B is a perspective view of the back surface. On the upper surface of the ceramic wiring board 10, an integrated circuit 50, a capacitor 52 formed by the method described above, a resistor 54 formed by a known technique, and an inductance 56 formed by arranging the wiring. , And these elements are sealed by a seal cap 60. On the outer periphery of the ceramic wiring board 10, a castellation 12A that constitutes a signal terminal and a castellation 12B that constitutes a ground terminal are formed by dividing the castellation through hole 14 into two. The ceramic wiring board 10 is fixed to the wiring board on which the ceramic wiring board 10 is mounted by soldering to the castellations 12A and 12B as described above with reference to FIG. At the same time, an electrical connection is made. In addition to the castellations 12A and 12B, electrical connection is made through the via holes 58, which are not described in the above description.

As described above with reference to FIG. 9, in the conventional anodic oxidation method, when the underlayer for plating is formed on the entire surface of the ceramic substrate 90 as shown in FIG. Since the end Ti layer 120a and the Cu layer 122a are formed in the hole 14, when the conductive layer (Cu-Ni layer) 128 below the Ta layer is formed by plating, refer to FIG. As described above, the end Ti layer 120 that wraps around the castellation through hole 14
A plating 176 is formed on the a and Cu layers 122a. With this plating 176 left, castellation 12
In order to form A and 12B, sputtering of Ti-Cu or the like in the through hole 14 for castellation and Cu
When the plating of —Ni—Au or the like is performed, a sputter layer and a plating layer are formed on the plating 176, and the predetermined adhesion strength of the sputter layer and the plating layer to the ceramic substrate 90 cannot be obtained. .

On the other hand, in this embodiment, as shown in FIG.
As described above with reference to FIG. 1, the plating underlayer (Ti layer 20, Cu layer 2) around the through-hole 14 for castellation is formed.
Since 2) is removed by etching, when the lower electrode layer (Cu-Ni layer) 28 under the Ta layer is formed, plating is not formed in the through holes 14 for castellation. Therefore, the Ti layer 41 and the -Cu layer 43 by the sputtering, and the Cu layer 45, the Ni layer 47, A by the plating are formed on the surface of the ceramic substrate 90 in the castellation through hole.
The u layer 49 is firmly fixed. Therefore, as described above, the Ti of the castellations 12A and 12B is applied to the wiring board on which the ceramic wiring board 10 is mounted.
Layer 41 and -Cu layer 43, Cu layer 45, and Ni layer 4
7. By soldering via the Au layer 49, it can be firmly fixed.

Also, in this embodiment, unlike the method of the prior art, it is not necessary to mask the through holes for castellation at the time of anodic oxidation. Further, since the plating underlayer around the through holes for castellation is removed by etching, it is possible to visually confirm whether or not the underlayer is completely removed. Therefore, the leakage current does not occur from the through hole for castellation, and the dielectric film 32a can be formed to an accurate thickness according to the profile described above with reference to FIG. Can be manufactured.

That is, when there is a leakage current from the through hole for castellation, when a current is flown according to the profile described above with reference to FIG. 5A, a current flows as shown in FIG. 5B. . As shown in FIG. 5B, in the constant current process, as the chemical conversion process progresses and the applied voltage increases, the dielectric breakdown of the masking progresses and the leakage current increases. In addition, the control shifts to the constant voltage control earlier by the amount of the leakage current. Here, in the constant voltage control, since the leakage current has a constant value by keeping the voltage constant, the current gradually approaches the constant value. As a result, the leakage current shown by the diagonal lines in the figure does not contribute to the chemical conversion treatment, so the dielectric film 32
Although the film thickness of a becomes thin and the capacitance of the capacitor cannot be manufactured to a preset value, as described above, in the present embodiment, the leakage current does not occur. In the above embodiment, the ceramic substrate 9
Although the castellation through-hole 14 is provided at 0, it is clear that the through-hole may be a through-hole or the like used for inserting leads of other electronic components. .

In addition to the through holes on the surface of the ceramic substrate, when a convex portion is formed by, for example, providing a ring for sealing the cap, the Ti- A sputtered layer of Cu or the like is formed, and similar problems occur, but according to the present invention, the same problem can be solved.

Further, a recess may be provided on the surface of the ceramic substrate for housing a semiconductor chip, for example. Even in such a case, a sputtered layer of Ti—Cu or the like is formed on the side surface of the recess, but the same problem can be solved by the present invention. Therefore, the present invention can be applied not only to the case where the substrate surface has a through hole but also to the case where it has a convex portion or a convex portion.

As the ceramic constituting the ceramic substrate 90 of the above-mentioned embodiment, AlN, glass ceramics, S, in addition to ceramics containing alumina as a main component.
Various ceramic materials such as iC, mullite and glass ceramic can be adopted. The metal forming the plating base layer lower electrode layer, the upper electrode layer and the like can be appropriately selected according to the ceramic material and characteristics.
Further, the plating underlayer such as Ti—Cu may be formed by vapor deposition, ion plating, etc., in addition to sputtering. As a substance that becomes a dielectric by anodizing treatment, T
Although an example using a is shown, other than that, Ti, Al, tantalum nitride (Ta: N), and the like can be given.

[0042]

As described above, in the method for forming a ceramic wiring board according to the present invention, at least the convex side surface portion, the concave side surface portion, or the plating underlayer in the through hole of the ceramic substrate is removed in advance. There is no plating on the side surface or the inside of the through hole. Therefore, when forming the dielectric layer by anodizing, it is not necessary to mask the side surfaces of the protrusions and recesses and the through holes, and leakage current does not occur, so the dielectric layer can be formed to an accurate thickness. can do. Further, even when the through hole is a castellation through hole, plating is not performed in the castellation through hole because the underlayer for plating is removed in advance. Therefore, when forming a dielectric layer by anodizing by passing an electric current, it is not necessary to mask the through holes for the castellation, and since a leakage current does not occur, the dielectric layer has an accurate thickness. Can be formed. Further, since the underlayer for plating around the castellation through hole is removed, when the ceramic wiring board is fixed to the substrate by soldering the castellation, the ceramic wiring board is firmly fixed. be able to.

[Brief description of drawings]

FIG. 1 is a process drawing showing each manufacturing process in a method for forming a ceramic wiring board according to an embodiment of the present invention.

FIG. 2 is a process drawing showing each manufacturing process in the method for forming a ceramic wiring board according to the embodiment.

FIG. 3 is a process drawing showing each manufacturing process in the method for forming a ceramic wiring board according to the embodiment.

FIG. 4 (A) is a plan view of a ceramic substrate,
FIG. 4B is a sectional view taken along line BB.

5 is a graph showing the amount of current according to a voltage-current profile during anodization of a ceramic wiring board.
5A is a graph showing a case where there is no leakage current, and FIG. 5B is a graph showing a case where there is a leakage current.

FIG. 6 (A) is a perspective view of the upper surface side of the ceramic wiring board, and FIG. 6 (B) is a perspective view of the back surface side.

FIG. 7 is a perspective view showing a state in which a ceramic wiring board is fixed on a wiring board.

FIG. 8 is a plan view of a ceramic substrate.

FIG. 9 is a process drawing showing each manufacturing process in the method for forming a ceramic wiring board according to the related art.

[Explanation of symbols]

 10 Ceramic Wiring Board 12 Ti Layer 14 Cu Layer 28 Cu-Ni Plating Layer 32 Ta Sputter Layer 32a Dielectric Layer 36 Masking 36A Opening 90 Ceramic Substrate

Claims (2)

[Claims] 1. A step of disposing a plating base device on the surface of a ceramic substrate having at least one of a convex portion, a concave portion and a through hole on the surface of the substrate, and at least a side surface portion of the convex portion, a side surface portion of the concave portion or A step of removing the plating underlayer disposed in the through hole; a step of forming a lower electrode layer by electrolytic plating at a predetermined position on the plating underlayer; and anodization on the lower electrode layer. A step of disposing a thin film layer of a substance to be a dielectric by a treatment, a step of forming a masking layer having an opening portion at a predetermined portion of the thin film layer, and a current flowing through the plating underlayer to form the masking layer. And a step of forming at least a part of the thin film layer exposed from the opening as a dielectric layer by anodizing treatment, the method for forming a ceramic wiring board. 2. The ceramic wiring board according to claim 1, wherein the through hole is a through hole for castellation, and the ceramic substrate is a ceramic substrate having the through hole for castellation. Forming method.