JPH09247543A - Digital electronic image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display image pickup output even though a VRAM is not provided in the case where the image pickup element of a total picture element reading- out type is provided. SOLUTION: The image pickup element 101 is actuated at a thinning mode, and an image pickup signal is supplied to a liquid crystal display 135, and an image pickup picture is displayed (monitoring mode). The image pickup element is actuated at a total picture element reading-out mode, and data is written in a DRAM 141 (first recording mode). After the finish of write-in, the data compressed by an encoder/decoder 142 is written in a flash memory 143, and also, the image pickup signal is displayed (second recording mode). The data of the flash memory 143 is read out, and is decoded, and is written in the DRAM 141, and also, the image pickup signal is displayed (first reproduction mode). The data is thinned and read out of the DRAM 141, and is displayed (second reproduction mode). The switching of these modes is controlled by a data switcher 130 and a microcomputer 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital electronic image pickup apparatus suitable for use in, for example, a digital recording electronic still camera.

[0002]

2. Description of the Related Art Recently, digital electronic still cameras have become widespread. As a solid-state image pickup device suitable for use in an electronic still camera, for example, a CCD image pickup device, a device having a square lattice and all-pixel reading has been proposed. The square lattice makes the vertical interval and the horizontal interval of adjacent pixels equal to each other, and is used to match an image pickup signal to a monitor for a personal computer. In order to generate an interlaced output signal, a CCD image sensor used in a conventional video camera or the like accumulates 1/60 second (1 field), reads out 2 pixels, and vertically in order to generate an interlaced output signal, as shown in FIG. Interlaced scanning has been realized by mixing two pixels read in the transfer CCD and shifting the positions of the pixels to be mixed in the vertical direction between the odd field and the even field.

Since such a CCD image pickup device has a 1/60 second storage time, it can capture a moving image better than a frame storage system having a 1/30 second storage time. It has the disadvantage of low resolution. Therefore, it is not suitable as an image sensor of an electronic still camera. Therefore, FIG.
As shown in FIG. 2, an all-pixel reading method has been proposed in which all pixels are read by accumulating for 1/30 seconds. According to this method, it is possible to prevent the vertical resolution from deteriorating. However, in order to output an image pickup signal from the image pickup device, when the number of pixels is the same, it takes twice as long as the image pickup device for the video camera described above. Need. More specifically, an image pickup signal with a cycle of 1/30 second is generated.

[0004]

In the case of a digital electronic still camera, a monitor for displaying a picked-up image, such as a liquid crystal monitor, is often provided in order to focus at the time of shooting and adjust the camera angle at the time of shooting. The liquid crystal monitor normally displays a television image by non-interlaced scanning of 1/60 second. Therefore, FIG.
As shown in (3), if the image pickup signal with a cycle of 1/30 second is supplied to the liquid crystal monitor as it is, there is a problem that the display image is distorted. In order to avoid this, as shown in FIG. 24, a VRAM (video RAM) 61 is added to the liquid crystal monitor 62.
(Or frame memory) It is necessary to convert the frame rate. 1/30 for VRAM 61
An image pickup signal having a second cycle is supplied, and a non-interlace signal having a 1/60 second cycle is generated at the output thereof.

As described above, the image pickup device for reading all pixels is
Although it is suitable as an image pickup device of an electronic still camera in terms of high vertical resolution, it requires a VRAM or a frame memory to display a picked-up image on a normal television monitor, which causes a problem of cost increase. Furthermore, since the electronic still camera is equipped with an automatic control device such as an automatic focus control device, an automatic iris control device, and an automatic white balance control device, the fact that the output signal cycle of the image sensor is long means that these automatic control The problem of slowing down occurred. Further, there is a problem that the movement of the image displayed on the monitor is not smooth.

One method of solving the above problem is to increase the data rate of the output signal of the image pickup device. However, it is necessary to provide a sampling rate converter for that purpose, and as the clock frequency becomes higher, there arise problems such as an increase in power consumption, an increase in cost of parts used, and deterioration of S / N. Therefore, a method of increasing the data rate of the image pickup signal is not preferable.

Therefore, an object of the present invention is to provide a digital electronic image pickup device which can output an image pickup signal at high speed without deteriorating the advantage of high vertical resolution, thereby eliminating the need for VRAM. .

Another object of the present invention is to minimize the period during which the display on the monitor disappears when a captured image is being recorded on a recording medium or when data is being read from the recording medium. It is to provide a digital electronic imaging device.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a digital electronic image pickup apparatus which records an image signal generated by a solid-state image pickup element as a digital signal.
A solid-state imaging device capable of selecting a first imaging mode in which the number of pixels is read out and a second imaging mode in which a second number of pixels less than the first pixel is read out; Signal processing means for generating an image signal by processing the output signal of the element, display means for displaying the image signal, storage means for storing the image signal as a digital image signal, signal processing means, display means and storage In the case of generating a data switching means for inputting and outputting a signal to and from the means and an image signal to be stored in the storage means, the image signal is operated in the first imaging mode and is input to the display means. In the second imaging mode, the solid-state imaging device and the control means for controlling the data switching means are operated so as to operate in the second imaging mode.

The solid-state image pickup device is capable of selecting a first image pickup mode in which all pixels are read out and a second image pickup mode in which line thinning-out is read out. Therefore, when the captured image is displayed on the display device, it is controlled to operate in the second image capturing mode. Therefore, VRAM
The image pickup signal can be displayed by the display device without the provision of.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall construction of an embodiment of the present invention. Reference numeral 101 is a solid-state image sensor, for example, a CCD image sensor. The CCD image sensor 101 is a single-plate imager having three primary color filters, complementary color filters, and the like. As will be described in detail later, the CCD image pickup device 101 has a full frame read operation mode in which all pixels are read (first image pickup mode) and a line thinning operation mode in which a signal with a reduced number of lines is output. (Second imaging mode) can be switched. Subject light enters the image sensor 101 via the lens system 100.

The output signal of the image pickup device 101 is supplied to the sample hold and AGC circuit 102. In the full frame read mode, the time for reading one image is 1/30 second, and in the line thinning mode, this is 1/60 second. The sample and hold is configured as a correlated double sampling circuit, and performs noise removal, waveform shaping, and compensation for defective pixels. The AGC controls the gain according to the brightness of the subject, and the gain is also controlled for automatic aperture adjustment. Sample and hold, AGC circuit 10
The two output signals are supplied to the A / D converter 103. A /
From the D converter 103, a digital image pickup signal in which one sample has 10 bits is generated.

The digitized image pickup signal is supplied to a camera signal processing circuit 104 having an IC circuit configuration. The signal processing circuit 104 includes a digital clamp circuit, a luminance signal processing circuit, a color signal processing circuit, a contour correction circuit, a defect compensation circuit, an automatic aperture control circuit, an automatic focus control circuit, an automatic white balance correction circuit, and a component signal (Y: A multiplexer of a luminance signal, a digital video signal obtained by sampling a Cr, Cb: color difference signal at a sampling frequency of 4: 1: 1), a synchronizing signal generating circuit, a timing generator, an interface with a microcomputer, and the like are included. A more specific configuration of the signal processing circuit 104 will be described later. The multiplexer converts the component signal into multiplexed data.

Reference numeral 105 denotes a microcomputer for controlling signal processing. A control signal from the microcomputer 105 is supplied to the lens system 100, the electronic volume 106, the camera signal processing circuit 104, and the timing controller 107. Timing controller 1
Reference numeral 07 includes a timing generator 108 and a CCD drive circuit 109. The electronic volume 106 generates a sample and hold and a gain control signal for the AGC circuit 102.

A clock 3MCK having a frequency three times as high as the clock MCK is supplied to the camera signal processing circuit 104 and the timing controller 107. As an example,
The number of horizontal pixels of the image sensor 101 is 780, and MCK =
780fh (fh: horizontal scanning frequency of the image sensor 101) =
It is 12.3 MHz. Further, the horizontal synchronization signal H and the vertical synchronization signal V generated in the camera signal processing circuit 104 are supplied to the timing controller 107.
CCD drive circuit 109 of timing controller 107
Are supplied to the image sensor 101.
The drive pulse includes a vertical drive pulse, a horizontal drive pulse, a read pulse, and the like.

FIG. 2 shows an example of the camera signal processing circuit 104. Here, a configuration including an automatic aperture control circuit is shown. For simplicity, illustration of a defect compensation circuit, an automatic focus control circuit, and an automatic white balance correction circuit is omitted. A 10-bit digital imaging signal from the A / D converter 103 is supplied to the arithmetic circuit 112 via the digital clamp circuit 111. When the image sensor has three primary color filters, the arithmetic circuit 112 adds or subtracts the three primary color signals to generate a luminance signal component and a color difference signal component.

The luminance signal component is supplied to the luminance signal processing circuit 113 and the contour correction circuit 114, and the color difference signal component is supplied to the color signal processing circuit 116. Luminance signal processing circuit 1
13 includes a gamma correction circuit and the like. Contour correction circuit 11
4 is a luminance signal processing circuit 1
13 are added by the adding circuit 115 to the 13 output signals. The luminance signal Y is obtained from the adding circuit 115. The color signal processing circuit 113 includes a γ correction circuit, a white balance correction circuit, and the like. The color signal processing circuit 113 generates color difference signals Cr and Cb. A component signal including Y, Cr, and Cb is supplied to the multiplexer 117.
The multiplexer 117 combines these signals as described below, and generates a multiplexed component signal at the output.

A timing / synchronization signal generation circuit 118 is provided, and a horizontal synchronization signal H, a vertical synchronization signal V, a clock, and a timing signal are generated from this circuit 118 from a clock of 3MCK. 119 is a serial IO for interface between the microcomputer 109 and the camera signal processing circuit 104, and 120 is a detection,
It is an accumulation circuit. The luminance signal component formed by the arithmetic circuit 112 is supplied to the detection and accumulation circuit 120. In the case of aperture control, the imaging screen is divided into a plurality of areas, and imaging signals are accumulated for each area. Then, the accumulated data of each area is detected and output from the accumulation circuit 120 to the serial IO 119.

The microcomputer 109 receives the accumulated data through the serial IO 119, and the microcomputer 109 performs a weighting operation on the accumulated data, an operation for obtaining the sum of the weighted area data, an aperture control signal, and the like. The drive motor of the aperture control ring of the lens system 100 is driven by the generated aperture control signal, and the timing controller 107 and the electronic volume 105 are controlled. An electronic shutter (exposure time) is controlled by the timing controller 107,
The gain is controlled by the electronic volume 105. Further, a control signal is supplied from the microcomputer 109 to the accumulating circuit 120 through the serial I / O 119, and the pattern of area division and the like are controlled.

The multiplexer 117 for multiplexing the component signal of the (411) system will be described in more detail. As shown in FIG.
Receives an 8-bit width luminance signal Y and a color difference signal C synchronized with the clock MCK, and receives 3/2 MCK (clock M
A multiplexed component signal having an 8-bit width synchronized with a clock having a frequency 3/2 times the frequency of CK is generated. FIG.
The structure of an example of the multiplexer 117 is shown. The multiplexer 117 includes an input selector 121 that selects one of the luminance signal Y and the color signal C, a shift register 122 to which the input selector 121 is supplied as a serial input, and a register 12 to which a parallel output of the shift register 122 is loaded.
3, an output selector 124 for sequentially selecting the data loaded in the register 123, and a register 125 connected to the output selector 124. Each register is 8 bits wide.

FIG. 5 is a timing chart showing the operation of the multiplexer 117 described above. 3MCK is a clock three times the frequency of the clock MCK. The luminance data Y and the color signal C are synchronized with the clock MCK. Since it is a (411) system component signal,
Four samples of luminance data (for example, Y ₀ , Y ₁ , Y ₂ , Y
₃ ), one sample of red color difference data (for example, C
r ₀ ) and one sample of blue color difference data (for example, Cb ₀ )
And correspond.

The input selector 121 is controlled so that the luminance data is selected at the high level of the select pulse and the color data is selected at the low level. The shift register 122 is supplied with 3/2 WCK as a clock, takes in the data selected by the input selector 121, and shifts in series. The output Q ₀ of the first stage register of the shift register 122 is, as shown in the figure, Y ₋₁ ,
Y ₀ , Cr ₀ , Y ₁ , Y ₂ , Cb ₀ , Y ₃ ,...

With respect to the register 123, the shift register 122 has a clock timing of 1/4 MCK.
Are loaded in parallel. The cycle of the 1/4 MCK clock is six times the cycle of the 3/2 MCK. Also, 1
The clock phase of the / 4MCK is selected so that a total of 6 samples of the luminance data and the color difference data related to each other are transferred from the shift register 122 to the register 123.

The output selector 124 has a clock (3/2).
MCK), sequentially selecting the earliest sample in the register 123, and selecting the selected sample in the register 125.
Captures. Therefore, from the register 125, (Y, C
r, Y, Y, Cb, Y) so that the multiplexed component signals are generated.

The above-mentioned multiplexer 117 converts the sampling clock frequency of data from MCK to 3/2 MCK which is 1.5 times the frequency, thereby converting the data into an 8-bit width multiplexed component signal. When the multiplexer 117 is not provided, the camera signal processing circuit 104 outputs data (luminance signal Y and color signal C) having a width of (8 × 2 = 16 bits). In that case, crosstalk between the two data buses occurs, crosstalk increases due to an increase in the board wiring area, and the memory size increases due to an increase in the memory data width. Various problems such as an increase in power consumption of the memory occur. Multiplexer 1 described above
By providing 17 on the output side of the signal processing circuit 104, it is possible to prevent these problems from occurring.

Returning to FIG. 1, one embodiment of the present invention will be further described. The component signals multiplexed as described above from the camera signal processing circuit 104 are supplied to the data switcher 130. Data switcher 13
0 is an output point a connected to the output of the camera signal processing circuit 104, an input point b connected to a conversion circuit 134 for converting a component signal into three primary color signals, and an input / output connected to the recording / reproducing data bus 140. With point c and. The state of the data switcher 130 is the mode switching signals 131, 132, 1 generated based on the user's key operation or the like.
Controlled by 33. The microcomputer 105 in FIG. 1 is provided mainly for controlling the camera unit. Although not shown, microcomputers are provided for controlling recording / reproducing operations and controlling the entire apparatus, respectively. Communication between the microcomputers is performed.

The three primary color signals R, G, B generated by the conversion circuit 134 are supplied to a television display device such as a liquid crystal display 135, and a liquid crystal display 135 displays a picked-up image. The liquid crystal display 135 has 1
A color image is displayed by a non-interlace method with a period of / 60 seconds. For the recording / reproducing data bus 140,
Randomly accessible memory such as DRAM (dynamic
Random access memory (141) and encoder / decoder for data compression such as JPEG (Joint Photographi)
c Experts Group) encoder / decoder 142 is connected. High-efficiency coding other than JPEG may be used. A recording medium such as a flash memory 143 and an interface 1 for the encoder / decoder 142;
44 are connected. The operation of the DRAM 141 is controlled by an address signal and a control signal supplied from the memory controller 145.

The encoder / decoder 142 is a JPE
G, that is, adaptive DCT (Discrete Cosine Transfor
The data amount is reduced to about 1/10 by the encoding of m).
For processing such as blocking in JPEG, DRA
M141 is provided. The flash memory 143 is
The semiconductor memory retains its stored contents even when the power is turned off, and can be electrically erased and rewritten collectively for the entire memory or for each divided area. As a recording medium, a medium such as a semiconductor memory other than the flash memory may be used. Further, an interface may be provided to supply the compressed still image data to a personal computer as needed. In one embodiment of the present invention,
The recording means that the flash memory 143 is obtained by encoding the image pickup signal.
Is to write to, and the reproduction is the flash memory 143.
It is to read the data in and decrypt the read data.

The above-described embodiment of the present invention will be described in more detail. In this embodiment, five types of operations are possible depending on the connection state of the data switcher 130. This consists of a monitoring mode, a first recording mode, a second recording mode, a first reproduction mode, and a second reproduction mode. These modes are set by the mode switching signals 131, 132, 133. The mode switching signals 131, 132, and 133 are generated from a recording / reproducing system control microcomputer (not shown). A mode switching signal may be generated by the microcomputer 105. In monitoring mode,
The image pickup screen is displayed on the liquid crystal display 135. In the first recording mode, a desired captured image is written to the DRAM 141. In the second recording mode, image data stored in the DRAM 141 is compressed and written to the flash memory 143. In the first reproduction mode, the flash memory 143
The data stored in the memory is read, the read data is decoded and written in the DRAM 141. In the second playback mode, DR
Liquid crystal display 135 by reading data of AM 141
To be displayed.

FIG. 6 shows the connection in the monitoring mode in which the output point a and the input point b of the data switcher 130 are connected. Monitoring mode is mode switching signal 1
It is set by 31 becoming active. In the monitoring mode, the microcomputer 105
CCD drive circuit 109 of timing controller 107
Is controlled to operate the image sensor 101 in the line thinning mode. A line from which no reading is performed occurs from the imaging element 101, and an imaging signal is read in a 1/60 second cycle.

In the monitoring mode, the signal processing circuit 1
The output signal of 04 is supplied to the conversion circuit 134 via the data switcher 130, and the three primary color signals output from the conversion circuit 134 are supplied to the liquid crystal display 135 for display. Since the image sensor 101 operates in the line thinning mode, the liquid crystal display 135 can perform non-interlaced display with a 1/60 second cycle. The still image to be recorded can be determined by adjusting the angle of view while viewing the display on the liquid crystal display 135. Although the vertical resolution is degraded due to the line thinning mode, this is not a problem for the purpose of monitoring captured images. In the line thinning mode, the followability to the movement is improved due to the high speed reading. Therefore, the response of automatic control such as automatic focus adjustment and automatic aperture adjustment is improved, and it becomes easy to monitor a moving image.

In the monitoring mode, the DRAM 141, the encoder / decoder 142, and the flash memory 143 connected to the data bus indicated by the broken line are inoperative. In order to save power consumption, it is preferable to turn off the power supply to these inactive circuits or stop the supply of the clock required for operation. Similarly, in other modes described below, the bus for the circuit that does not operate is shown by a broken line, and the power supply to the circuit that does not operate is turned off.

FIG. 7 shows a mode for recording a still image, that is, a first recording mode in which the output point a of the data switcher 130 and the input / output point c are connected. The first recording mode is set when the mode switching signal 132 becomes active. In the monitoring mode, the microcomputer 105 controls the CCD drive circuit 109 of the timing controller 107 to operate the image sensor 101 in the full frame read mode. From the image sensor 101, all pixels, for example, 320,000 pixels are read, and an image signal is read in a 1/30 second cycle.

The image pickup signal is processed in the camera signal processing circuit 104 and written in the DRAM 141 through the output point a and the input / output point c of the data switcher 130 and the recording / reproducing data bus 140. Memory controller 1
Numeral 45 sets the DRAM 141 in a write state, and supplies a write address to the DRAM 141. The memory controller 145 is controlled by a microcomputer (not shown) for controlling a recording / reproducing system. One still image data is written into the DRAM 141. In the first recording mode in which image data of 1/30 second is written, an image cannot be displayed on the liquid crystal display 135. In order to minimize the time during which an image is not displayed, when writing is completed, the process shifts to the next second recording mode.

When the writing of one sheet of image data to the DRAM 141 is completed, the data switcher 130 enters the second recording mode in which the output point a and the input point b are connected as shown in FIG. The second recording mode is set when the mode switching signal 131 becomes active. In this mode, image data is read from DRAM 141. The read data is supplied to the encoder / decoder 142 via the bus 140. The encoder / decoder 142 compresses data read from the DRAM 141 by, for example, JPEG. Further, the compressed data is written to the flash memory 143. In this way, the captured image is compressed and recorded.

In the second recording mode, the image pickup device 1
01 operates in the line thinning mode, and similarly to the monitoring mode, a signal read from the image sensor 101 at high speed is processed by the camera signal processing circuit 104, and the image signal is transmitted through the data switcher 130 and the conversion circuit 134. Is supplied to the liquid crystal display 135 to display an image. Thereby, the time during which the display of the image disappears during recording can be minimized.

In the reproduction mode, the image data written in the flash memory 143 is reproduced and displayed on the liquid crystal display 135. FIG. 9 shows the data switcher 1
The output point a and the input point b of 30 are connected, and the state of the first reproduction mode in which the image pickup signal is displayed on the liquid crystal display 135 is shown. The first reproduction mode is set when the mode switching signal 131 becomes active.
In this mode, data is read from the flash memory 143, and the read data is the encoder / decoder 142.
Is supplied to.

The encoder / decoder 142 decodes the data to generate image data. The DRAM 141 is controlled to write the image data. In this case, the memory controller 145 controls the write address of the DRAM 141 so that the decoded data is written to the DRAM 141 with the same data arrangement as in the first recording mode. A similar data arrangement may be realized by address control at the time of reading. This relationship is
The conversion circuit 134 converts the digital image signal read from the
Is necessary to use the same configuration as that used in the monitoring mode when the image data is supplied to the liquid crystal display 135 via the liquid crystal display 135 and displayed on the liquid crystal display 135. In the first reproduction mode, the image sensor 101 is driven in the line thinning mode, and a captured image of the image sensor 101 is displayed on the liquid crystal display 135.

When the decoded data is written in the DRAM 141, the second reproduction mode shown in FIG. 10 is entered. Second
In the reproduction mode, the input / output point c and the input point b of the data switcher 130 are connected. The second reproduction mode is set when the mode switching signal 133 becomes active. DRAM 141 is set to the read state.
Then, the read data of the DRAM 141 is supplied to the liquid crystal display 135 via the recording / reproducing data bus 140, the data switcher 130, and the conversion circuit 134. Therefore, the image corresponding to the data recorded in the flash memory 143 can be viewed on the liquid crystal display 135. In this case, the data recorded in the flash memory 143 is not line thinning data,
It is full frame data. Therefore, the image sensor 10 is controlled by the address control by the memory controller 145.
1 realizes line thinning similar to the case where 1 is driven in the line thinning mode. Thereby, the read data of the DRAM 141 can be reproduced by the liquid crystal display 135.

In this way, the still image data stored in the flash memory 143 is stored in the liquid crystal display 1.
It can be reproduced and viewed by the 35. The number of still images that can be recorded is determined by the storage capacity of the flash memory 143, the data compression method, and the like. The flash memory 143 is preferably configured as an IC card. Of course, a recording medium other than the flash memory may be used. Further, the record data may be transmitted to an external personal computer via an interface provided as necessary, or the record data may be stored in an external storage device.

An example of the above-mentioned solid-state image pickup device 101 will be described below. FIG. 11 shows a solid-state image sensor such as CC.
An outline of an example of the D image pickup device 1 is shown. In this example, an interline system is adopted, and a photosensor (for example, a photodiode) 2 two-dimensionally arranged in an image area is provided between the photosensors 2 and signal charges from the photosensor 2 are transferred to a horizontal CCD (horizontal CCD). It has a vertical CCD (vertical transfer unit) 3 for transferring data to a transfer unit 4, and a buffer amplifier 5 connected to the horizontal CCD 4. Imaging light that has passed through a color filter having an array as described below enters the photosensor 2. 1 photo sensor 2 and 1 in vertical CCD 3
Bits correspond to each other, and the signal charges from the photosensor 2 can be read out to the vertical CCD 3 without being mixed, and the signals of all pixels can be sequentially transferred to the horizontal CCD 4. Then, by driving the horizontal CCD 4, the signal is transferred to the floating diffusion area and sequentially converted into a voltage, and the buffer amplifier 5
Output through

FIG. 12 shows a plan view of a unit pixel of the image pickup device 1, and FIG. 13 shows a structure of the vertical CCD 3. Vertical CCD
3 has a structure of, for example, three-layer electrode three-phase driving. In FIG. 12, 6 is a transfer channel of the vertical CCD 3,
7 is a channel stopper for separating pixels and between pixels and transfer channels, 8, 9 and 10.
Are transfer gates of the vertical CCD 3 respectively. The transfer gate 9 also serves as a read gate. FIG.
Here, illustration of a light shielding film and the like is omitted. The transfer gates 8, 9 and 10 are formed by processing the first, second and third polycrystalline silicon electrodes as shown in FIG. Vertical drive pulses φV ₁ , φV ₂ and φV ₃ are applied to these transfer gates 8, 9 and 10, respectively.

When a signal is read from the photosensor 2 to the vertical CCD 3, a transfer gate adjacent to the photosensor 2, that is, a transfer gate 9 which also serves as a read gate, is read.
A bias voltage (referred to as a read pulse) higher than the high level of the vertical transfer clock φV ₂ is applied. When a read pulse is supplied to the gate 9, one pixel is connected to the vertical CCD 3
Since it corresponds to 1 bit of all photo sensors 2
Signal charges are read out to the vertical CCD 3. Horizontal CCD
Reference numeral 5 outputs data for one line in response to the transfer clocks φH ₁ and φH ₂ . In addition, as the horizontal CCD 5,
For example, a multi-channel horizontal CCD structure can be adopted. In that case, the output unit has a two-channel configuration.

Since the CCD image pickup device described above can sequentially output the signals of all pixels, an electronic still camera,
Suitable for capturing images. However, the output time of one screen (from the upper end to the lower end of the screen) is twice as long as that of a video camera image sensor having the same number of pixels that performs interlaced output. In this example, as described above, the image signal for one screen is output at high speed by reducing the number of horizontal lines as a signal for monitoring and an image signal for automatic control such as automatic focus control. In addition, in the case of this line thinning, the vertical color sequence defined by the arrangement of the color filters is not broken. On the other hand, when capturing a captured image into the flash memory, a full-frame imaging signal (an imaging signal in which the number of lines is not thinned out) is output. Even in the case of line thinning, since the color sequence is the same as in the case of full frame, the problem that the signal processing circuit becomes complicated can be avoided.

In the above-mentioned image pickup device capable of reading all pixels, in order to thin out the number of lines, the wiring for the transfer gate (second polycrystalline silicon) 9 which contributes to the reading of the signal charges from the photosensor 2 is provided. It is possible by dividing into two. The repetition period of the color sequence is represented by N. FIG. 14 is an example of the case of (N = 2).

As the color filter array of the single-plate CCD image pickup device, R (red pass filter), G (green pass filter), and B (blue pass filter) are arranged as shown in FIG. 15A. (Bayer method) is known. A high-sensitivity G filter is arranged in half of the pixels. A color filter having a complementary checkered pattern shown in FIG. 15B is also known. In FIG. 15B, Ye, Cy, Mg
Are yellow, cyan, and magenta filters, respectively. The complementary color filter shown in FIG. 15B can improve the resolution as compared with the primary color filter, and is therefore often used in video cameras. On the other hand, the primary color filter shown in FIG. 15A is excellent in color reproducibility and is often used in electronic still cameras.

As the image pickup device in the present invention, either a single plate type image pickup device having a primary color filter or a single plate type image pickup device having a complementary color filter may be used. Further, although not shown, an image sensor having a G filter,
An image sensor having an array of R and B filters, wherein the positional relationship between the two image sensors is shifted in the horizontal direction or in the horizontal and vertical directions by half the pixel pitch (so-called space Picture element shifting method) may be used.

In the arrangement of FIG. 15A, the repetition cycle N of the vertical color sequence is (N = 2), and in the arrangement of FIG. 15B, (N = 4). FIG. 14 is (N = 2), and is a schematic diagram showing one row of the photosensor 2, the vertical CCD 3, and the bus wiring of the gates of the vertical CCD 3 in the vertical direction. Among the photosensors 2, the one provided with a diagonal line at the upper left corner corresponds to one color filter, for example, a G filter, and the one without the diagonal line corresponds to another color filter, for example, a B filter. The vertical CCD 3 is of a three-layer electrode three-phase drive type as described above, and has a 3-bit gate adjacent to the aperture pixel of the image sensor. The vertical CCD 3 has a repeating unit A,
Contains repeating unit B. Repeating unit A is gate 2
1, 22, and 23, and the repeating unit B is a gate 3
1, 32, and 33. Gates 22 and 32 are transfer / read gates. 41, 42, 42 'and 43 are
Drive pulses for vertical transfer φV ₁ , φV ₂ , φV ₂ ′, φ
V ₃ is a bus wiring to which each is supplied.

Gates 21 and 31 are connected to bus line 41, and gates 23 and 33 are connected to bus line 43. Drive pulses φV ₁ and φV ₃ are supplied to these bus lines 41 and 43, respectively. Drive pulse φV ₂
, Two buses 42 and 42 'are provided.
The repeating unit A means that the transfer / read gate 22 is the bus 4
2 and the repeating unit B means that the transfer / read gate 32 is connected to the bus 42 '. Note that, in FIG. 14, the bus line is drawn on only one side for simplification, but it is common to arrange the bus lines on both sides to drive both sides.

In the above-mentioned image pickup device, in order to thin out the lines, a repeating unit A is arranged in m (m = 1, 2, 3, ...) A × m (bit) range and a repeating unit B is N. ×
A range of B × N × a (bits) is alternately formed in the vertical direction. In the example shown in FIG. 14, (N = 2, m =
3, a = 2). Although the values of m and a can be arbitrarily selected, it is necessary that (m + N × a) is smaller than the number of vertical pixels of the number of effective pixels even if m and a are large values.

In the above-described image pickup device, in the first operation mode, that is, in the full-frame operation in which the signals of all pixels are read out, signals are read out from the photosensor 2 into both the repeating units A and B of the vertical CCD 3. It To that end, a read pulse is applied to both gates 22 and 32 through bus lines 42 and 42 '. In this case, the color filter array order and the corresponding color sequence,
For example, color signals are output in the sequence of G, B, G, B, ....

On the other hand, in the second operation mode, that is, in the line thinning operation, the read pulse is applied only to the gate 22 of the repeating unit A through the bus wiring 42. Therefore, a signal is read from the range of A × m (bit), and B is read.
No signal is read from the range of × N × a (bit). In the example of FIG. 14, a signal is generated from the (m = 3) line and no signal is generated from the (N × a = 4) line. Since the number of lines to be thinned out is an integer multiple of N, the color sequence corresponding to the order of the color signals of the imaging output in the case of line thinning out is kept in the same relationship as in full frame reading.

FIG. 16 shows the timing when the image sensor is driven, and FIG. 16A shows the timing when the full frame is read. In each horizontal blanking period, three-phase drive pulses φV ₁ , φV ₂ , φV ₂ ′, φ
V ₃ is the gate 21, 2 of the repeating unit A of the vertical CCD _3.
2 and 23 and the gates 31, 32 and 33 of repeating unit B, respectively. Read pulses are also applied to both gates 22 and 32. As a result, the signal charge from all the photosensors becomes vertical C
It is read for CD3. As shown in the detailed timing chart of FIG. 16B, the drive pulses φV ₁ , φV ₂ , φV ₂ ′, and φV ₃ generated in the horizontal blanking period are of three phases, and one line shift is performed depending on the line shift period. Done. When reading a full frame, one line shift is performed within each horizontal blanking period.

On the other hand, in the case of line thinning-out reading,
As shown in FIG. 16C, the read pulse is applied only to the gate 22 of the repeating unit A. Thereby, the signal charges are read out only from the photosensor adjacent to the repeating unit A. In the case of thinning out lines, no signal charges are read out from the thinned lines, resulting in no signal. This non-signal period can be removed by repeating the line shift operation a plurality of times, as described later.

FIG. 17A is a schematic diagram of the potential of the channel 6 of the vertical CCD 3 in the case of (m = 1, a = 1). The direction from the right side toward the left horizontal CCD 4 in the drawing is the vertical transfer direction. The channel 6 includes a packet 51 including the signal charge Qs during the line thinning operation.
And an empty packet 52 exist. In order to output the signal charge Qs from each line, the number of line shifts is increased by the empty packet 52, whereby the signal charge and the no signal are mixed in the horizontal CCD 4 and the no signal period is removed. The number of line shifts performed in each horizontal blanking period may be selected so as to satisfy the following relationship.

1 (: the number of packets including the signal charge Qs to be output) + X (the number of packets not including the preceding signal charge Qs) and 1 + X + (N × a) (: Therefore, in the case of (X = 0), only the signal charges are transferred to the horizontal CCD 4, and in the case of (X ≠ 0),
A packet containing signal charges and one or more packets not containing signal charges are transferred to the horizontal CCD 4.

According to the above conditions, the signal charge is transferred to the horizontal CC.
It is possible to transfer to D4 and also to compress the line of no signal. Actually, the charge of the empty packet is not 0, but the unnecessary signal charge Qn such as smear signal or dark signal is included. If the number of line shifts performed in each horizontal blanking period is different, the number of unnecessary signal charges Qn added is different, and thus the amount of unnecessary signals included varies from line to line. As a result, there is a possibility that image quality deterioration such as line crawl and color shift may occur.

To solve this problem, the number of line shifts performed in each horizontal blanking period may be made constant. Limited conditions, ie (m = 1, or m
= 2), the number of line shifts of the vertical CCD 3 is set to ((N × a / m) +1), so that the packet including the signal charge Qs added to the signal charge Qs of each line is not included. The number can be constant. As a result, it is possible to prevent the above-described image quality deterioration.

FIG. 17B shows (N = 2, m = 1, a = 1).
6 is a schematic diagram of the potential of the channel 6 of the vertical CCD 3 in the case of FIG. In this example, (N × a / m = 2), and by setting the number of line shifts to three, the number of packets that do not include the signal charge Qs to be added in each line can be made constant. Also, FIG. 17C
Indicates the case of (N = 2, m = 2, a = 1). In this case, (N × a / m = 1), and the number of line shifts should be two. Further, even in the case of m> 2, if the level of the smear signal or the dark signal can be sufficiently reduced, no problem will occur.

Since the number of lines can be reduced in the CCD image pickup device described above, the number of lines m in which the repeating units A are arranged in the vertical CCD 3 and the number N × a in which the repeating units B are arranged are selected for one field. The number of lines of the output image pickup signal can be suppressed to be equal to or less than the number of horizontal scanning lines of the television. Like a Bayer color filter array (N = 2)
Taking the case of as an example, some examples of the number of output lines will be described.

As shown in FIG. 18, a VGA (Video Graphic) having an effective pixel count (: vertical × horizontal) of (480 × 640).
In the case where the present invention is applied to an imaging device compatible with (s Array), (a = 1, m = 2). Therefore, in the line thinning mode, the number of output lines can be halved to 240 lines. As shown in FIG. 19, the number of effective pixels is (768
In the (× 1024) image pickup device, the number of output lines can be set to 256 by setting (m = 1, a = 1). As shown in FIG. 20, the number of effective pixels is (1024 × 1
In the image sensor of 280), (m = 1, a ₁ = 1 and a ₂ =
By setting 2), the number of output lines can be 256. a ₁ and a ₂ are used alternately.

In any of the cases shown in FIGS. 18, 19 and 20, the number of output lines can be made smaller than the number of lines in one field of the NTSC system (262.5). Therefore, the color sequence and the angle of view can be maintained in the same relationship as in the full frame read mode, and the image pickup signal in the line thinning mode can be output at a higher speed. Thereby, the imaging screen can be displayed on the liquid crystal monitor without using the VRAM or the frame memory. It should be noted that the angle of view is the angle at which the range reflected on the image sensor when the image is captured is stretched around the optical axis of the lens.

The specific structure of the image pickup device in the above-described embodiment is an example, and the present invention can use other solid-state image pickup devices. Vertical C for example
The CD may have a two-layer electrode four-phase drive structure, or may be an image pickup device of a system other than the interline system, or a solid-state image pickup device using a device other than the CCD. Further, as a mode for driving the solid-state image sensor, a read pulse φV
It is also possible to set the third operation mode in which ₂ ′ is applied and the read pulse φV ₂ is not applied.

Further, the present invention is not limited to the image pickup device having the above-mentioned structure, and an image pickup device capable of selecting the all-pixel reading mode or the mode in which the number of read pixels is reduced can be used.

[0065]

As described above, according to the present invention, a still image having a good vertical resolution can be obtained in a full frame image pickup mode in which all pixels are read out, and the still image can be used for display on a liquid crystal display or the like. In such a case, the imaging signal can be output at high speed depending on the imaging mode of the line thinning. Therefore, the image pickup signal can be displayed on the monitor without providing the VRAM. Further, since the image pickup signal can be output at high speed, the response of the automatic control device such as autofocus can be speeded up. Further, since the number of frames increases, there is an advantage that the movement of the monitor image becomes smooth.

Further, according to the present invention, the image pickup signal is displayed during recording except the period during which the image signal is written in the memory (DRAM), so that the period during which the display disappears can be minimized. Furthermore, during reproduction, since the image pickup signal is supplied to the display device while the data is being read from the recording medium,
The period during which the display disappears can be minimized as with recording.

Further, according to the present invention, the component signal output from the camera signal processing circuit can be multiplexed by changing the clock frequency, and the bit of the data bus arranged for signal processing of the subsequent stage. The width can be reduced. As a result, signal deterioration such as crosstalk can be suppressed, the size of the memory can be reduced, and the power consumption of the memory can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a camera signal processing circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a multiplexer portion in the camera signal processing circuit.

FIG. 4 is a block diagram of an example of a multiplexer.

FIG. 5 is a timing chart showing the operation of the multiplexer.

FIG. 6 is a block diagram showing a connection relationship in a monitoring mode according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a connection relationship in a first recording mode according to an embodiment of the present invention.

FIG. 8 is a block diagram showing a connection relationship in a second recording mode of an embodiment of the present invention.

FIG. 9 is a block diagram showing a connection relationship in a first reproduction mode according to an embodiment of the present invention.

FIG. 10 is a block diagram showing a connection relationship in a second reproduction mode according to an embodiment of the present invention.

FIG. 11 is a schematic diagram showing a schematic configuration of an example of an image pickup element that can be used in the present invention.

FIG. 12 is an enlarged plan view of one pixel portion of an example of an image sensor.

FIG. 13 is a schematic diagram showing a structure of a vertical CCD as an example of an image sensor.

FIG. 14 is a schematic diagram showing vertical one-row bus wirings of an example of an image sensor.

FIG. 15 is a schematic diagram illustrating an example of an array of color filters used in an example of an image sensor and another example.

FIG. 16 is a timing chart of drive pulses for driving an example of an image sensor.

FIG. 17 is a schematic diagram schematically showing the potential of a vertical CCD in an example of an image sensor.

FIG. 18 is a schematic diagram illustrating a specific example of an image sensor.

FIG. 19 is a schematic diagram illustrating another specific example of the image sensor.

FIG. 20 is a schematic diagram showing still another specific example of the image sensor.

FIG. 21 is a schematic diagram used to describe a conventional image sensor.

FIG. 22 is a schematic diagram used to describe the previously proposed image sensor.

FIG. 23 is a schematic diagram showing the relationship between the output of the image sensor and the display on the liquid crystal monitor.

FIG. 24 is a block diagram showing a configuration when an image pickup signal generated from an image pickup element is supplied to a liquid crystal monitor.

[Explanation of symbols]

2 ... Photo sensor, 3 ... Vertical CCD, 4 ...
Horizontal CCD, 6 ... Channel of vertical CCD, 101
... image sensor, 104 ... camera signal processing circuit, 1
05: microcomputer, 107: timing controller, 130: data switcher, 1
35: liquid crystal display, 141: DRAM,
142: encoder / decoder, 143: flash memory

Claims (6)

[Claims] 1. A digital electronic image pickup apparatus, wherein an image signal generated by a solid-state image pickup device is recorded as a digital signal, in a first image pickup mode for reading a first pixel number, and the first pixel number. A solid-state image sensor capable of selecting a second image-capturing mode in which a smaller number of second pixels are read out, and by processing an output signal of the solid-state image sensor,
Between the signal processing means for generating an image signal, the display means for displaying the image signal, the storage means for storing the image signal as a digital image signal, the signal processing means, the display means and the storage means. , A data switching means for inputting and outputting a signal and an image signal to be stored in the storage means,
When operating in the first imaging mode and generating an image signal to be input to the display means, the solid-state imaging device and the data switching means are controlled so as to operate in the second imaging mode. A digital electronic image pickup device comprising: 2. The digital electronic image pickup apparatus according to claim 1, wherein the storage unit includes a memory unit for compressing and encoding image data, and a recording medium for storing the compressed data. A mode for recording an image captured by the image sensor is divided into a first recording mode and a second recording mode. In the first recording mode, the digital image signal from the signal processing means is transferred to the memory via the data switching means. The digital electronic image pickup device is characterized in that in the second recording mode, the digital image signal read from the memory means is compression-encoded and recorded in the recording medium. 3. The digital electronic image pickup apparatus according to claim 2, wherein in the second recording mode, the digital image signal from the signal processing means is displayed by the display means via the data switching means. A digital electronic image pickup device characterized by the above. 4. The digital electronic image pickup apparatus according to claim 1, wherein the storage unit includes a memory unit for compressing and encoding image data, and a recording medium for storing the compressed data. A mode for reproducing an image recorded on a medium is divided into a first reproduction mode and a second reproduction mode. In the first reproduction mode, data read from the recording medium is decoded and a decoded digital image signal is read. Is written in the memory means, and in the second reproduction mode, the digital image signal read from the memory means is displayed by the display means via the data switching means. apparatus. 5. The digital electronic image pickup apparatus according to claim 4, wherein in the second reproduction mode, by controlling the address of the memory means, the digital image signal with the number of pixels thinned out is stored in the memory means. A digital electronic image pickup device characterized by being read out from the digital electronic image pickup device. 6. The digital electronic image pickup apparatus according to claim 1, wherein the signal processing means converts the luminance signal and the chrominance signal synchronized with the first clock signal into a multiplexed component signal, and the multiplexed component. A digital electronic image pickup apparatus comprising means for outputting a signal in synchronization with a second clock signal having a frequency of (3/2) times the first clock signal.