JPH09247537A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the reduction of power consumption and the extension of a working range in configuration using an amplification type MOS sensor. SOLUTION: This device is constituted so as to be provided with an image pickup area in which a photosensitive cell consisting of a photodiode 1, an amplifying transistor 2, a vertical selecting transistor 3 and a resetting transistor is arranged in two-dimensional shape, plural vertical signal lines 8 to read out the output of the amplifying transistor 2, load transistors 14 installed at one ends of the vertical signal lines 8, amplification signal accumulation capacitance 11 connected to the other ends of the vertical signal lines 8 through signal fetching transistors 10, and horizontal selecting transistors 12 to connect the line signal accumulation capacitance 11 and a horizontal signal line 50. In this case, a current is allowed to flow in the load transistor 14 when the signal of the photodiode 1 is taken out to the vertical signal line 8, and when the signal is not taken out to the vertical signal line 8, the current is not allowed to flow.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device using an amplification type MOS sensor.

[0002]

2. Description of the Related Art In recent years, a solid-state imaging device using an amplification type MOS sensor has been proposed as one of the solid-state imaging devices. This solid-state imaging device amplifies the signal detected by the photodiode for each cell with a transistor,
It has the characteristic of high sensitivity.

FIG. 51 is a circuit diagram showing a conventional example of this type of solid-state image pickup device. Photodiode 1-1-
Amplification transistors 2-1-1, 2-1-2, ..., 2-2- for amplifying signals of 1, 1-1-2, ..., 1-2-2
2, vertical selection transistors 3-1-1, 3-1-2, ..., 3-2-2 for selecting a line for reading a signal, reset transistors 4-1-1, 4 for resetting a signal charge
About 2 × 2 unit cells each including -1-2, ..., 4-2-2 are two-dimensionally arranged. Actually, more unit cells are arranged.

The horizontal address lines 6-1 and 6-2 wired in the horizontal direction from the vertical shift register 5 are connected to the gates of the vertical selection transistors to determine the lines from which signals are read. The reset lines 7-1 and 7-2 are connected to the gate of the reset transistor. The source of the amplification transistor is connected to the vertical signal lines 8-1 and 8-2, and the load transistors 9-1 and 9-2 are provided at one end thereof. The other ends of the vertical signal lines 8-1 and 8-2 are 1
1 line (1 row) via the signal capturing transistors 10-1 and 10-2 that captures signals for 1 line (1 row)
Minute signal storage capacitors 11-1 and 11- for storing minute signals
2 as shown in the drawing, and is connected to the horizontal signal line 50 via the horizontal selection transistors 12-1 and 12-2 selected by the selection pulse supplied from the horizontal shift register 13.

FIG. 52 is a timing diagram of pulse signals for driving this device. When the address pulse 101 for setting the horizontal address line 6-1 to the high level is applied, only the selection transistors 3-1-1 and 3-1-2 of this line are turned on, and the amplification transistors 2-1-1 and 2-1-1 of this row are provided. −
A source follower circuit is composed of 1-2 and the load transistors 9-1 and 9-2, and a gate voltage of the amplification transistor, that is, a voltage substantially equal to the voltage of the photodiode appears on the vertical signal lines 8-1 and 8-2. At this time, the signal capture pulse 103 is applied to the common gate 49 of the signal capture transistors 10-1 and 10-2, and the amplified signal storage capacitor 11
The amplified signal charge of the product of the voltage appearing on the vertical signal line and its capacitance is stored in -1, 11-2.

After the signals are stored in the amplified signal storage capacitors 11-1 and 11-2, the reset transistors 4-1-1 and
Applying the signal reset pulse 102-1 to 4-1-2,
The signal charges accumulated in the photodiodes 1-1-1, 1-1-2 are reset.

Next, horizontal selection pulses 104-1 and 104-2 are sequentially applied from the horizontal shift register 13 to the horizontal selection transistors 12-1 and 12-2, and the output signal 105- for one row is output from the horizontal signal line 50. 1, 105-2 are sequentially taken out.

By continuing this operation sequentially for the next line and the next line, all two-dimensional signals can be read.

However, this type of solid-state image pickup device has the following problems. One is 9 in FIG.
This means that the current is constantly flowing through the source follower circuit using -1, 9-2 as load transistors, resulting in high power consumption. Considering application to a television camera, since the number of cells in the horizontal direction is at least 600 or more, even if the current flowing through one cell is small, the total current becomes very large.

The current of the source follower is the vertical signal line 8-
1, 8-2 capacity and amplified signal storage capacity 10-1, 10-
It is used to drive 2 but a normal sensor requires a current of at least 50 microamps to fully drive the vertical signal line and the amplified signal storage capacitance of about 1 pF. Therefore, a total current of at least 30 milliamperes is required, and if the power supply voltage is 3.3V, at least 100 milliwatts of power will be consumed. In the future, considering the application of a video camera, since it is desired to reduce the total sensor to 100 milliwatts or less, the power consumption of 100 milliwatts only with the imaging device is not an acceptable value.

The other is that the source follower operation causes a voltage drop in the load transistor / amplification transistor, which narrows the range in which a signal can be handled. When a current of 100 microamperes is passed, the source-gate channel voltage is about 0.
6V and a gate-channel / drain voltage of about 0.6V are required. Since these voltages are required for the load transistor and the amplification transistor respectively, 3.3-2 ×
There is only an operating range of (0.6 + 0.6) = 0.9V. This state is shown in FIG. 53 using a potential diagram. Manufacturing variation of threshold voltage of each transistor is ± 0.2V
Then, the operable range becomes only 0.1V.

If there is a manufacturing variation of the threshold voltage of ± 0.2V with respect to the source-gate channel voltage of 0.6V of the load transistor, the current of the source follower circuit becomes 4V.
It cannot be used as a product design because it fluctuates about twice. In order to suppress this variation, in practice, the gate width / gate length ratio (W / L ratio) of the load transistor is made small (0.5 or less, 0.2 or less) to reduce the influence of this variation. This further increases the source-gate channel voltage of the load transistor and reduces the operating range.

[0013]

As described above, in the conventional amplification type solid-state image pickup device, since current always flows in the source follower circuit formed by the amplification transistor and the load transistor of the unit cell, power consumption is reduced. large. Further, when the source follower operation is performed, there is a voltage drop between the load transistor and the amplification transistor, which causes a problem that the operating range is narrowed.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a solid-state image pickup capable of reducing power consumption and expanding an operation range in a configuration using an amplification type MOS sensor. To provide a device.

[0015]

[Means for Solving the Problems]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, according to the present invention (Claim 1), photosensitive cells comprising photoelectric conversion means, signal charge storage means, signal charge discharge means, row selection means, and amplification means are two-dimensionally arranged on a semiconductor substrate. Imaging area, a plurality of vertical selection lines arranged in the imaging area in the row direction, vertical selection means for driving these vertical selection lines, and a plurality of vertical signals arranged in the column direction for reading the output of the amplification means. Lines, a plurality of vertical signal line drive assisting means provided in these vertical signal lines, row signal accumulating means provided at the ends of the vertical signal lines, and signals of the vertical signal lines are transmitted to the row signal accumulating means. A signal fetching means, a horizontal signal line arranged in the row direction adjacent to the row signal accumulating means, a horizontal reading means connecting the horizontal signal line and the row signal accumulating means, and a horizontal selecting means for driving the horizontal reading means. And with Type solid-state imaging device, there is a first horizontal period during which a signal is read out to the horizontal signal line through the horizontal readout means, and a second horizontal period other than that, within the second horizontal period or the second horizontal period. The current flowing through the vertical signal line drive assisting means is changed at the boundary between the first and second horizontal periods.

Here, as a preferred embodiment of the present invention, in addition to the features described in claims 2 to 6, the vertical signal line drive assisting means is a vertical signal line reset transistor.

Further, according to the present invention (claim 7), photosensitive cells comprising photoelectric conversion means, signal charge storage means, signal charge discharging means, row selecting means and amplifying means are two-dimensionally arranged on a semiconductor substrate. Imaging area, a plurality of vertical selection lines arranged in the imaging area in the row direction, vertical selection means for driving these vertical selection lines, and a plurality of vertical signals arranged in the column direction for reading the output of the amplification means. Line, a plurality of vertical signal line drive assisting means provided in these vertical signal lines, noise suppressing means provided at the end of the vertical signal line and capturing and subtracting noise and signals appearing with a time difference in the vertical signal line, A horizontal signal line arranged in the row direction adjacent to the noise suppressing unit, a horizontal reading unit connecting the horizontal signal line and the output of the noise suppressing unit, and a horizontal selecting unit driving the horizontal reading unit. Increased Type solid-state image pickup device, there is a first horizontal period during which a signal is read out through the horizontal read-out means to the horizontal signal line and a second horizontal period other than that, and the second horizontal line from the vertical selection means is present. Address pulse that is generated during the period, is transmitted through the vertical selection line and is applied to the row selection means, and activates the amplification means of the selected row or rows, and the vertical signal that is applied to the vertical signal line driving auxiliary means. Before the signal charge discharging means discharges the signal charge accumulated in the signal charge accumulating means of the selected row, there is a period where the vertical signal line driving pulse for supplying a current to the line assisting means overlaps. After the first noise suppression pulse that captures the signal applied to the noise suppression means and generated in the vertical signal line and holds the state in the overlap period of the address pulse and the vertical signal line drive pulse And after the signal charge accumulated in the signal charge accumulating means of the selected row is discharged by the signal charge discharging means of the selected row, and within the overlap period of the address pulse and the vertical signal line drive pulse. In addition, there is a trailing edge of a second noise suppression pulse which is applied to the noise suppression means and which takes in noise generated in the vertical signal line and generates a difference signal from the signal.

Here, as a preferred embodiment of the present invention, in addition to what is stated in claims 8 and 9, the vertical signal line drive assisting means is a load MOS transistor.

According to the present invention (claim 10), a photosensitive cell comprising photoelectric conversion means, signal charge storage means, signal charge discharging means, row selecting means and amplifying means is provided on a semiconductor substrate.
An image pickup area arranged in a dimension, a plurality of vertical selection lines arranged in the row direction in the image pickup area, vertical selection means for driving these vertical selection lines, and arranged in the column direction for reading the output of the amplification means. A plurality of vertical signal lines, a plurality of vertical signal line drive assisting means provided on these vertical signal lines, and noise and signals appearing with a time lag on the vertical signal lines provided at the ends of the vertical signal lines and subtracted Noise suppressing means and a horizontal signal line arranged in the row direction adjacent to the noise suppressing means,
In an amplification type solid-state imaging device provided with a horizontal read-out means for connecting the horizontal select line and the output of the noise suppression means, and a horizontal select means for driving the horizontal read-out means, in the horizontal signal line via the horizontal read-out means. There is a first horizontal period during which a signal is being read and a second horizontal period other than that, and there is a first vertical signal line drive applied to the vertical signal line drive assisting means and flowing a current through the vertical signal line assisting means. The trailing edge of the pulse is generated in the second horizontal period from the vertical selection means before the signal charges accumulated in the signal charge accumulation means of the selected row are discharged by the signal charge discharge means, and the vertical selection line is generated. The signal which is transmitted via the row selecting means and is in the address pulse for activating the amplifying means of the selected row or rows and which is applied to the noise suppressing means and which is generated in the vertical signal line is taken in and its state is changed. The trailing edge of the first noise suppression pulse held is in the period in which the address pulse is ON and the first vertical signal line drive pulse is OFF, and the trailing edge of the second vertical signal line drive pulse is selected. After the signal charges accumulated in the signal charge accumulating means of the other row are discharged by the signal charge discharging means and within the address pulse, the address pulse is ON and the second vertical signal line drive pulse is OFF. In addition, there is a trailing edge of a second noise suppression pulse which is applied to the noise suppression means and which takes in noise generated in the vertical signal line and generates a difference signal from the signal.

Here, as a preferred embodiment of the present invention, in addition to what is stated in claims 11 and 12, the vertical signal line drive assisting means is a vertical signal line reset transistor.

Further, the present invention (claim 13) is a charge transfer means for transferring a signal charge from the photoelectric conversion means, the signal charge storage means, the charge voltage conversion means, the signal charge storage means to the charge voltage conversion means on the semiconductor substrate. An image pickup area in which photosensitive cells including a signal charge discharging means for discharging charges from a charge-voltage converting means, a row selecting means, and an amplifying means are arranged in a secondary shape, and a plurality of vertical lines arranged in the image pickup area in a row direction. A select line, a vertical select means for driving the vertical select line, a plurality of vertical signal lines arranged in the column direction for reading the output of the amplifying means, and a plurality of vertical signal line driving assistants provided on the plurality of vertical signal lines. Means, noise suppressing means provided at the end of the vertical signal line for capturing and subtracting noise and signals that appear with a time difference in the vertical signal line, and a horizontal signal line arranged in the row direction adjacent to the noise suppressing means, This horizontal In an amplification type image pickup device including a horizontal read-out means for connecting a selection line and an output of a noise suppression means, and a horizontal selection means for driving the horizontal read-out means, a signal is read out to a horizontal signal line through the horizontal read-out means. There is a first horizontal period and a second horizontal period other than the above, which occurs in the second horizontal period from the vertical selection means, is transmitted through the vertical selection line, is applied to the row selection means, and is selected. The period in which the address pulse for activating the amplifying means of one or a plurality of rows and the vertical signal line driving pulse applied to the vertical signal line auxiliary means and flowing a current to the vertical signal line auxiliary means overlap each other Before the signal charge existing in the selected row and accumulated in the signal charge accumulating means is transferred to the charge-voltage converting means by the charge transferring means, and the address pulse and the vertical signal line driving pulse are exceeded. Within the lap period, there is a trailing edge of a third noise suppression pulse that is applied to the noise suppression means and that takes in the noise generated in the vertical signal line and holds that state, and is accumulated in the signal charge accumulation means of the selected row. After the signal charge is transferred to the charge-voltage conversion means by the charge transfer means, and within the overlap period of the address pulse and the vertical signal line drive pulse, the signal applied to the noise suppression means and generated in the vertical signal line is taken in and noise is taken in. And a trailing edge of a fourth noise suppression pulse that produces a difference signal between the and.

Here, as a preferred embodiment of the present invention, in addition to what is stated in claims 14 and 15, the vertical signal line drive assisting means is a load MOS transistor.

According to the present invention (claim 16), a photoelectric transfer means, a signal charge storage means, a charge voltage conversion means, and a charge transfer means for transferring the signal charge from the signal charge storage means to the charge voltage conversion means on the semiconductor substrate. , An image pickup area in which photosensitive cells including a signal charge discharging means for discharging charges from a charge-voltage converting means, a row selecting means, and an amplifying means are two-dimensionally arranged, and a plurality of vertical selections arranged in the row direction in the image pickup area Line, vertical selection means for driving the vertical selection line, a plurality of vertical signal lines arranged in the column direction for reading the output of the amplification means, and a plurality of vertical signal line driving auxiliary means provided in the plurality of vertical signal lines A noise suppressing means provided at an end of the vertical signal line for capturing and subtracting noise and a signal appearing with a time difference in the vertical signal line, and a horizontal signal line arranged in the row direction adjacent to the noise suppressing means, Horizontal In an amplification type image pickup device including a horizontal read-out means for connecting a selection line and an output of a noise suppression means, and a horizontal selection means for driving the horizontal read-out means, a signal is read out to a horizontal signal line through the horizontal read-out means. There is a first horizontal period and a second horizontal period other than the above, which occurs in the second horizontal period from the vertical selection means, is transmitted through the vertical selection line, is applied to the row selection means, and is selected. The period in which the address pulse for activating the amplifying means of one or a plurality of rows and the vertical signal line driving pulse applied to the vertical signal line auxiliary means and flowing a current to the vertical signal line auxiliary means overlap each other After the first transfer operation in which the signal charges stored in the signal charge storage means of the selected row are transferred to the charge voltage conversion means by the charge transfer means,
Within the overlap period of the address pulse and the vertical signal line drive pulse, there is a trailing edge of the first noise suppression pulse that receives the signal applied to the noise suppression means and is generated in the vertical signal line and holds the state, and the charge voltage After the signal charge of the converting means is discharged through the charge discharging means, a signal applied to the noise suppressing means and generated in the vertical signal line is captured within the overlap period of the address pulse and the vertical signal line driving pulse. It is characterized in that there is a trailing edge of a second noise suppression pulse which produces a difference signal.

Here, as a preferred embodiment of the present invention, in addition to those described in claims 17 to 20, the vertical signal line drive assisting means is a load MOS transistor.

Further, the present invention (claim 21) is a charge transfer means for transferring a signal charge from the photoelectric conversion means, the signal charge storage means, the charge voltage conversion means, the signal charge storage means to the charge voltage conversion means on the semiconductor substrate. , An image pickup area in which photosensitive cells including a signal charge discharging means for discharging charges from a charge-voltage converting means, a row selecting means, and an amplifying means are two-dimensionally arranged, and a plurality of vertical selections arranged in the row direction in the image pickup area Line, vertical selection means for driving the vertical selection line, a plurality of vertical signal lines arranged in the column direction for reading the output of the amplification means, and a plurality of vertical signal line driving auxiliary means provided in the plurality of vertical signal lines A noise suppressing means provided at an end of the vertical signal line for capturing and subtracting noise and a signal appearing with a time difference in the vertical signal line, and a horizontal signal line arranged in the row direction adjacent to the noise suppressing means, Horizontal In an amplification type image pickup device including a horizontal read-out means for connecting a selection line and an output of a noise suppression means, and a horizontal selection means for driving the horizontal read-out means, a signal is read out to a horizontal signal line through the horizontal read-out means. There is a first horizontal period and a second horizontal period other than that, and the trailing edge of the first vertical signal line driving pulse applied to the vertical signal line driving auxiliary means and flowing a current through the vertical signal line auxiliary means. However, before the signal charges accumulated in the signal charge accumulating means of the selected row are transferred to the charge voltage converting means by the charge transferring means, the vertical selecting lines are generated from the vertical selecting means within the second horizontal period. It is in the address pulse transmitted through the line selection means and applied to the row selection means to activate the amplification means of the selected row or rows, and the noise applied to the noise suppression means and generated in the vertical signal line is taken in and the state is maintained. Third trailing edge noise suppression pulse, and the address pulse is ON for the first
Of the vertical signal line drive pulse is OFF, and the trailing edge of the second vertical signal line drive pulse is the charge-voltage conversion of the signal charge accumulated in the signal charge accumulation means of the selected row by the charge transfer means. Signal which is applied to the noise suppressing means and is generated in the vertical signal line after being transferred to the means and within the address pulse, while the address pulse is ON and the second vertical signal line drive pulse is OFF, And a trailing edge of a fourth noise suppression pulse that produces a difference signal between the and.

Here, as a preferred embodiment of the present invention, the vertical signal line drive assisting means is a vertical signal line reset transistor in addition to those described in claims 22 and 23.

According to the present invention (claim 24), photoelectric transfer means, signal charge storage means, charge voltage conversion means, charge transfer means for transferring signal charges from the signal charge storage means to the charge voltage conversion means on a semiconductor substrate. , An image pickup area in which photosensitive cells including a signal charge discharging means for discharging charges from a charge-voltage converting means, a row selecting means, and an amplifying means are two-dimensionally arranged, and a plurality of vertical selections arranged in the row direction in the image pickup area Line, vertical selection means for driving the vertical selection line, a plurality of vertical signal lines arranged in the column direction for reading the output of the amplification means, and a plurality of vertical signal line driving auxiliary means provided in the plurality of vertical signal lines A noise suppressing means provided at an end of the vertical signal line for capturing and subtracting noise and a signal appearing with a time difference in the vertical signal line, and a horizontal signal line arranged in the row direction adjacent to the noise suppressing means, Horizontal In an amplification type image pickup device including a horizontal read-out means for connecting a selection line and an output of a noise suppression means, and a horizontal selection means for driving the horizontal read-out means, a signal is read out to a horizontal signal line through the horizontal read-out means. There is a first horizontal period and a second horizontal period other than that, and the trailing edge of the first vertical signal line driving pulse applied to the vertical signal line driving auxiliary means and flowing a current through the vertical signal line auxiliary means. However, after the first transfer operation in which the signal charge accumulated in the signal charge accumulating means of the selected row is transferred to the charge-voltage converting means by the charge transferring means, it is generated in the second horizontal period from the vertical selecting means. Then, the signal which is transmitted through the vertical selection line and applied to the row selection means and which activates the amplification means of the selected row or rows is included in the address pulse, which is applied to the noise suppression means and is generated on the vertical signal line. Capture The trailing edge of the first noise suppression pulse that holds that state is in the period in which the address pulse is ON and the first vertical signal line drive pulse is OFF, and the trailing edge of the second vertical signal line drive pulse is , After the signal charge of the charge-voltage converting means is discharged through the charge discharging means and within the address pulse, and the address pulse is ON and the second vertical signal line drive pulse is OFF, the noise suppressing means operates. It is characterized in that there is a trailing edge of a second noise suppression pulse for generating a difference signal from the signal which is loaded with the noise generated in the vertical signal line.

Here, as preferred embodiments of the present invention, in addition to those described in claims 25 to 32, the following ones can be mentioned.

(1) The vertical signal line drive assisting means is a vertical signal line reset transistor. (2) The noise suppression means is of a type that subtracts noise and signal in the voltage domain.

(3) The noise suppressing means is of a type that subtracts noise and signal in the charge region.

(4) The signal charge is discharged by the signal charge discharging means when the address pulse is at a low level.

(Operation) The above-mentioned problem is that a relatively large current for driving the vertical signal line is flowing in the source follower circuit which is composed of the load transistor and the amplifying transistor.

There are two ways to solve this problem. One is a method in which a current is passed through the load transistor when the signal of the photodiode is taken out to the vertical signal line, and a current is not passed or a small current is passed when the signal is not taken out to the vertical signal line. Although this method solves the problem of power consumption, it does not solve the problem of signal handling range.

To solve the two problems of power consumption and signal handling range at the same time, the following measures should be taken.

The problem is solved by making the load transistor a vertical signal line reset transistor capable of injecting charges into the vertical signal line and resetting its potential. The gate width / gate length ratio (W / L ratio) of the load transistor used in the amplification type image pickup device is generally set to be small in order to stabilize a small current flowing. As described above, at about 50 microamperes, W / L = 0.2 or less is designed in consideration of manufacturing variations as described above.

On the other hand, since the vertical signal line reset transistor wants to reset the capacitance of the vertical signal line to about 1 pF to the source voltage as fast as possible (preferably 50 nanoseconds or less), W
If the / L ratio can be 1 or more, design with 3 or more. In order to reduce the variation in the threshold voltage of the load transistor, W
The design is the reverse of reducing the / L ratio.

The high level voltage of the pulse is applied to the gate of the vertical signal line reset transistor during the period in which the amplification transistor corresponding to the vertical selection line is activated during the period of reading the signal of the cell corresponding to one vertical selection line. Are driven in a divided manner into a vertical signal line drive period when a low voltage is applied and a signal voltage detection period when a low level is applied. Basically, a signal is taken out when a low level is applied to the vertical signal line reset transistor, that is, when almost no current flows in the amplification transistor, so that two problems of power consumption and signal handling range can be solved.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

Here, the pulse drive of the load transistor that solves only the problem of power consumption and the vertical signal line reset drive that solves both the problems of power consumption and signal handling range will be described in detail.

[Embodiment 1] An embodiment of the present invention will be described. When a current is passed through the load transistor when the signal of the photodiode is taken out to the vertical signal line and a current is not passed or when the signal is not taken out or when the current is made small, as shown in FIG.
-2, the gate electrode 51 is independently taken out, and FIG.
Drive with the timing chart shown in. During the period 201 in which the signal of the photodiode is taken out from the vertical signal line to the amplified signal storage capacitor, the load transistors 14-1, 14-
A load transistor activation pulse 106 is applied to the second common gate electrode 51, and a current is passed through the load transistor. In the other period 202, the gate voltage of the load transistor is reduced and the current thereof is reduced.

By doing so, the power consumption can be reduced. However, this method solves the problem of power consumption,
The problem of signal coverage cannot be solved.

FIG. 3 shows an embodiment in which the two problems of power consumption and signal handling range are solved. Vertical signal line reset transistors 15-1 and 15-2 different in W / L from the conventional load transistor are connected to the vertical signal line.
The reason why the vertical signal line reset transistor is provided on the horizontal signal line 50 side of the vertical signal line is that there is an advantage that the vertical signal line is reliably reset when the resistance of the vertical signal line is high. There is also a method of providing vertical signal line reset transistors above and below the vertical signal line in order to further quickly reset the vertical signal line having high resistance. The load transistor of the source follower circuit has no advantage provided at the upper and lower ends.

FIG. 4 shows an operation timing chart in the apparatus of FIG.

Vertical signal line reset transistor 15-
Charge injection pulse 1 to common gate electrode 52 of 1, 15-2
07 is applied. At this time, the vertical signal lines 8-1, 8-2
Electric charges are injected from the common source 53 of the vertical signal line reset transistor to the preset signal and are almost preset to the source potential. When the charge injection pulse is turned off, a part of the injected charge is discharged through the amplification transistor of the addressed row, the potential of the vertical signal line changes, and the potential of the vertical signal line almost matches the gate potential of the amplification transistor. .

The situation is shown in FIG. 5 (b). That is, the signal of the gate voltage of the amplification transistor, which receives the signal voltage of the photodiode, is transmitted to the vertical signal line. The phase relationship between the charge injection pulse 107 and the signal acquisition pulse 103 is important for accurately transmitting a voltage equivalent to this voltage to the amplified signal storage capacitor. Charge injection pulse 107
Since the voltage corresponding to the signal charge appears on the vertical signal line after the power is turned off, finally the amplified signal storage capacitors 11-1 and 11
The trailing edge of the signal acquisition pulse 103 that determines the −2 potential is later than the trailing edge of the charge injection pulse 107 in time.

This is completely different from the load transistor pulse driving described with reference to FIGS. In the case of load transistor pulse driving, when the load transistor activation pulse is ON, the source follower circuit that constitutes the amplification transistor operates, so at this time, the signal is on the vertical signal line,
This is because it is necessary to turn off the signal capture pulse 103 while the load transistor activation pulse is on.

Regarding the leading edge of the signal capturing pulse 103, the signal capturing pulse is turned off and the potential of the vertical signal line becomes substantially equal to the gate potential of the amplifying transistor, that is, after the amplifying transistor is in the weak inversion state. When the pulse is applied, the charge accumulated in the vertical signal line is divided by the ratio of the capacitance of the vertical signal line and the capacitance of the amplified signal storage capacitor, so that the voltage of the amplified signal storage capacitor becomes smaller than the signal voltage that should originally appear. Therefore, the leading edge of the signal acquisition pulse 103 must precede the trailing edge of the charge injection pulse 107 in time.

More specifically, the period A in FIG. 5A immediately after the charge injection pulse 107 is turned off is shown in FIG.
As indicated by A in (b), since the current in the strong inversion region still flows in the amplification transistor and has the capacity drive capacity, even if there is the leading edge 108 of the signal acquisition pulse 103 in this period, the amplification signal The original signal can be stored in the storage capacitor.

In this operation, it is easy to understand that the power consumption is small because the period for supplying the current to the vertical signal line reset transistor is short.

The fact that the signal handling range is widened by the vertical signal line resetting operation will be described with reference to the drawings. 6 (a) to 6 (c) are potential diagrams of a circuit composed of a cell amplification transistor and a vertical signal line reset transistor.

When the charge injection pulse is applied, as shown in FIG.
As shown in (a), the potential of the vertical signal line becomes almost the source potential of the vertical signal line reset transistor. In order to quickly reach this state, the vertical signal line reset transistor has a large W / L ratio as described above. Immediately after the charge injection pulse is turned off, a part of the charges injected into the vertical signal line flows into the amplification transistor as shown in FIG. 6B, and then the vertical signal line as shown in FIG. 6C. Becomes almost the same as the potential of the gate of the amplification transistor.

The state of FIG. 6C is a potential diagram when the signal is actually taken into the amplified signal storage capacitor. As can be seen from this figure, almost no current flows in the amplification transistor or the vertical signal line reset transistor.
It can be seen that there is no voltage drop there and the signal handling range is 2.7 V, which is very wide when the power supply voltage is 3.3 V.

[Embodiment 2] The amplification type solid-state imaging device described above has amplification transistors 2-1-1 to 2-2-.
Since the variation of the threshold voltage of 2 is superimposed on the signal, when the reproduced image is reproduced, it becomes fixed pattern noise which is fixed in place. Therefore, this noise is present in the signal capturing transistor and the amplified signal storage capacitor portion of FIG. A noise canceller that suppresses noise is provided. As the noise canceller, a correlated double sampling type that takes the difference between the signal and noise in the voltage domain and a slice type that takes the difference in the charge domain will be taken up here. The noise canceller is not limited to this type.

FIG. 7 shows the one using the correlated double sampling type and the load transistor, FIG. 11 shows the one using the slice type and the load transistor, and FIG. 15 shows the one using the correlated double sampling type and the vertical signal line reset transistor. FIG. 19 is a circuit configuration diagram of one using a slice type and a vertical signal line reset transistor.

The configuration and principle of the noise canceller will be briefly described. In the correlated double sampling type, as shown in FIG. 7, a clamp capacitor 16-is provided on the vertical signal lines 8-1, 8-2.
1, 16-2, clamp transistors 17-1, 17-
2. Sample and hold transistors 18-1, 18-
2. Hold capacitors 19-1 and 19-2 are provided.

As shown in the timing chart of FIG.
When the address pulse 101 is applied from the horizontal address line 6-1, the vertical selection transistors 3-1-1 and 3-1-2 are turned on, the amplification transistors 2-1-1 and 2-1-2 are activated, and the vertical signal is generated. A signal voltage corresponding to the voltage of the photodiode appears on the lines 8-1 and 8-2. At this time, the clamp pulse 10 is applied to the common gate 55 of the clamp transistor.
9 is applied to the clamp transistors 17-1 and 17-2.
Is turned on, the voltage on the clamp transistor side of the clamp capacitors 16-1 and 16-2 is fixed to the voltage of the common source 54 of the clamp transistor, and then turned off.

Next, the signal reset pulse 102-1 is applied from the reset line 7-1 to the reset transistors 4-1-1 and 4-1-1.
When it is applied to 4-1-2 and the signal charges of the photodiode are discharged, a noise voltage appears on the vertical signal lines 8-1 and 8-2 due to the threshold variation of the amplification transistor.

At this time, the clamp capacitors 16-1, 16-
The voltage on the side of the clamp transistor 2 is the amount of change in the voltage of the vertical signal line, that is, the noise-free signal voltage obtained by subtracting the noise voltage from the signal voltage is the common source 54 of the clamp transistor.
It appears superimposed on the voltage of. The common source voltage also has no noise.

A sample-hold pulse 110 is applied to the common gate 56 of the sample-hold transistor, and this noise-free signal voltage is applied to the sample-hold transistor 1.
8-1, 18-2 via the hold capacitors 19-1, 19
-Tell it to 2.

Then, the horizontal selection transistor 12-
Signals without noise are read out sequentially through 1 and 12-2.

The important pulses in this type of noise canceller are clamp pulse 109 and sample hold pulse 11.
0, the trailing edges of these pulses are in the period during which the load transistor activation pulse 106, which activates the load transistor, is imprinted. The first noise suppression pulse described in the claims corresponds to the clamp pulse, and the second noise suppression pulse corresponds to the sample hold pulse.

FIG. 9 shows a modification of the drive timing shown in FIG. 2 of important clamp pulse 109 and sample hold pulse 110 that determine noise and signal acquisition
For each trailing edge time so that the cell states at the two trailing edge times are as similar as possible, the first
Address pulse 111-1 (111-2) and second address pulse 112-1 (112-2) are separately generated. Similarly, the first load transistor activation pulse 113
And the second load transistor activation pulse 114 are generated separately.

Further, the time between the trailing edge of the clamp pulse 109 and the leading edge of the first address pulse 111-1 (111-2), the trailing edge of the sample and hold pulse 110 and the second address pulse 112-. 1 (112-2) leading edge to be approximately equal. Similarly, the trailing edge of the clamp pulse 109 and the first load transistor activation pulse 1
13 and leading edge of sample hold pulse 1
10 trailing edge and second load transistor activation pulse 114
Make the time between the leading edge of and almost equal.

Further improvement is as shown in FIG.
The state of the cell at the time of the trailing edge of the sample-hold pulse is affected not only by the leading edge of the second address pulse but also by the first address pulse. In order to make the state of the cell at the time of the trailing edge of the clamp pulse equal to that of the trailing edge of the sample and hold pulse, a dummy address pulse 115-1 (115-2) is generated before the first address pulse. . Similarly, for the load transistor activation pulse, a dummy load transistor activation pulse 116 is generated before the first load transistor activation pulse 113.

Further, the dummy address pulse 115-
1 (115-2) A dummy clamp pulse 117 is generated before the clamp pulse 109 in synchronization with the dummy load transistor activation pulse 116. It is not necessary to use three of these dummy pulses together, and only one is effective.

On the other hand, the configuration and principle of another noise canceller, which is a slice type noise canceller, will be briefly described. As shown in FIG. 11, the vertical signal line 8-
Slice transistors 20-1 and 20-2 in
Gates are connected. Slice capacitors 21-1 and 21-2 and slice source reset transistors 22-1 and 22-2 are connected to the sources of the slice transistors. The drain has a slice charge storage capacitor 24.
-1,4-2-2 and the slice drain reset transistors 23-1, 23-2 are connected.

As shown in the timing chart of FIG. 12, when the address pulse 101 is applied from the horizontal address line 6-1, the vertical selection transistors 3-1-1, 3-1-
2 is turned on and the amplification transistors 2-1-1, 2-1-2
Are activated, and a signal voltage appears on the vertical signal lines 8-1 and 8-2.

At this time, the slice source reset pulse 118 is applied to the common gate 58 of the slice source reset transistors 22-1 and 22-2, and the slice capacitors 21-1 and 21-2 in which sufficient charges have been injected in advance. The first slice pulse 119 is applied to the common terminal 57,
Excess charges are discharged to the drain of the slice transistor through the gate channels of the slice transistors 20-1 and 20-2. The extra charge is applied to the common gate 61 of the slice drain reset transistors 23-1 and 23-2 by applying the slice charge reset pulse 121 to the slice drain reset transistor 23.
-1, 23-2 are discharged to the common drain 60.

Next, the signal reset pulse 102-1 is applied from the reset line 7-1 to the reset transistors 4-1-1 and 4-1.
When it is applied to 4-1-2 and the signal charges of the photodiode are discharged, a noise voltage appears on the vertical signal lines 8-1 and 8-2 due to the threshold variation of the amplification transistor.

At this time, the slice capacities 21-1, 21-
When the second slice pulse 120 is applied to the second common terminal 57, the change amount of the voltage of the vertical signal lines 8-1 and 8-2 connected to the gates of the slice transistors 20-1 and 20-2, that is, the signal is changed. The amplified signal charges obtained by multiplying the slice-capacitance by the noise-free signal voltage having no noise component are transferred to the slice charge storage capacitors 24-1, 24-2.

Then, the horizontal selection transistor 12-
1, 12-2 are sequentially turned on to read out a signal without noise.

The important pulses in this type of noise canceller are the first slice pulse 119 for presetting the charge of the slice capacitance and the second slice pulse for transferring the charge proportional to the difference between the signal and noise to the drain of the slice transistor. is there. The trailing edges of these pulses are the load transistor activation pulse 106 that activates the load transistor.
Is in the imprinted period. The first noise suppression pulse described in the claims corresponds to the first slice pulse, and the second noise suppression pulse corresponds to the second slice pulse.

When a p-type channel transistor is used as the slice transistor, it is necessary to invert the polarity of the slice pulse.

At this time, the third noise suppression pulse described in the claims is converted into the first slice pulse,
The fourth noise suppression pulse corresponds to the second slice pulse. FIG. 13 shows an improvement of the drive timing shown in FIG. In order that the states of the cells at the time points of the two trailing edges of the important first slice pulse 119 and the second slice pulse 120, which determine the noise and signal capture, are as close to the same condition as possible, at the time when each trailing edge is present. On the other hand, the first
Address pulse 111-1 (111-2) and second address pulse 112-1 (112-2) are separately generated. Similarly, the first load transistor activation pulse 113
And the second load transistor activation pulse 114 are generated separately.

Further, the time between the trailing edge of the first slice pulse 119 and the leading edge of the first address pulse 111-1 (111-2) and the trailing edge of the second slice pulse 120 and the second And the leading edge of the address pulse 112-1 (112-2) of the. Similarly, the time between the trailing edge of the first slice pulse 119 and the leading edge of the first load transistor activation pulse 113 and the trailing edge of the second slice pulse 120 and the second load transistor activation pulse 114. Make the time to the leading edge approximately equal.

When further improved, it becomes as shown in FIG.
The state of the cell at the time of the trailing edge of the second slice pulse is affected not only by the leading edge of the second address pulse but also by the first address pulse. In order to make the state of the cell at the time of the trailing edge of the first slice pulse equal to that of the trailing edge of the second slice pulse, the dummy address pulse 115-1 (115-2) is placed before the first address pulse.
Has occurred. Similarly, for the load transistor activation pulse, a dummy load transistor activation pulse 116 is generated before the first load transistor activation pulse 113.

Further, the dummy address pulse 115-
1 (115-2) A dummy slice pulse 122 is generated before the first slice pulse 119 in synchronization with the dummy load transistor activation pulse 116. It is also possible to generate the dummy slice charge reset pulse 123 before the slice charge reset pulse 121. It is not necessary to use four of these dummy pulses together and only one is effective.

FIG. 16 is an operation timing chart of the sensor of FIG.

As shown in the timing chart of FIG.
When the address pulse 101 is applied from the horizontal address line 6-1, the vertical selection transistors 3-1-1 and 3-1-2 are turned on and the amplification transistors 2-1-1 and 2-1-2 are activated. Here, the charge injection pulse 107 is applied to the common gate 52 of the vertical signal line reset transistor to inject charges into the vertical signal line and then turn off.

A part of the injected charge is discharged through the gate channel of the activated amplification transistor, and the vertical signal line 8
A signal voltage corresponding to the voltage of the photodiode appears at -1 and 8-2. At this time, the clamp pulse 109 is applied to the common gate 55 of the clamp transistors, the clamp transistors 17-1 and 17-2 are turned on, and the voltage on the clamp transistor side of the clamp capacitors 16-1 and 16-2 is shared by the clamp transistors. It is fixed to the voltage of the source 54 and then turned off.

Next, the signal reset pulse 102-1 is applied from the reset line 7-1 to the reset transistors 4-1-1 and 4-1-1.
It is applied to 4-1-2 to discharge the signal charge of the photodiode, and the noise detection charge injection pulse 124 is applied to the common gate 52 of the vertical signal line reset transistor to inject charges into the vertical signal line and then turn off. . Then, a noise voltage appears on the vertical signal lines 8-1 and 8-2 due to the threshold variation of the amplification transistor.

At this time, the clamp capacitors 16-1, 16-
The voltage on the side of the clamp transistor 2 is the amount of change in the voltage of the vertical signal line, that is, the noise-free signal voltage obtained by subtracting the noise voltage from the signal voltage is the common source 54 of the clamp transistor.
It appears superimposed on the voltage of. The common source voltage also has no noise.

A sample and hold pulse 110 is applied to the common gate 56 of the sample and hold transistor, and this noise-free signal voltage is applied to the sample and hold transistor 1.
8-1, 18-2 via the hold capacitors 19-1, 19
-Tell it to 2.

Then, the horizontal selection transistor 12-
Signals without noise are read out sequentially through 1 and 12-2.

The trailing edges of the clamp pulse 109 and the sample hold pulse 110, which are important pulses in this type of noise canceller, are in the period after the charge injection pulse 107 and the noise detection charge injection pulse 124 are turned off. The reason is as described above in the description of FIG.

The leading edge of the clamp pulse 109 is the same as that described with reference to FIG.
Either before the trailing edge or immediately after the trailing edge, the amplifying transistors in the addressed row are in the strong inversion state. The same is required for the leading edge of the sample-hold pulse 110 and the trailing edge of the noise detection charge injection pulse 124.

FIG. 17 is an improved version of FIG. 16, in which the address pulse is divided into two parts according to the detection of signal and noise. FIG. 18 shows a dummy address pulse 115-1 (115-
2), a dummy charge injection pulse 125 and a dummy clamp pulse 117 are added. As described above, these methods ensure that the states of the cells at the two trailing edges of the important clamp pulse 109 and sample hold pulse 110 that determine the noise and signal capture are in the same condition as much as possible.

FIG. 20 is an operation timing chart of the sensor of FIG.

As shown in the timing chart of FIG. 12, when the address pulse 101 is applied from the horizontal address line 6-1, the vertical selection transistors 3-1-1 and 3-1-.
2 is turned on and the amplification transistors 2-1-1, 2-1-2
Is activated. Here, the charge injection pulse 107 is applied to the common gate 52 of the vertical signal line reset transistor to inject charges into the vertical signal line and then turned off. A part of the injected charges is discharged through the gate channel of the activated amplification transistor, and a signal voltage corresponding to the voltage of the photodiode appears on the vertical signal lines 8-1 and 8-2.

At this time, the slice source reset pulse 118 is applied to the common gate 58 of the slice source reset transistors 22-1 and 22-2, and the slice capacitors 21-1 and 21-2 in which sufficient charges have been injected in advance. The first slice pulse 119 is applied to the common terminal 57,
Excess charges are discharged to the drain of the slice transistor through the gate channels of the slice transistors 20-1 and 20-2. The extra charge is applied to the common gate 61 of the slice drain reset transistors 23-1 and 23-2 by applying the slice charge reset pulse 121 to the slice drain reset transistor 23.
-1, 23-2 are discharged to the common drain 60.

Next, the signal reset pulse 102-1 is applied from the reset line 7-1 to the reset transistors 4-1-1 and 4-1-1.
It is applied to 4-1-2 to discharge the signal charge of the photodiode, and the noise detection charge injection pulse 124 is applied to the common gate 52 of the vertical signal line reset transistor to inject charges into the vertical signal line and then turn off. . Then, a noise voltage appears on the vertical signal lines 8-1 and 8-2 due to the threshold variation of the amplification transistor.

At this time, the slice capacities 21-1, 21-
When the second slice pulse 120 is applied to the second common terminal 57, the change amount of the voltage of the vertical signal lines 8-1 and 8-2 connected to the gates of the slice transistors 20-1 and 20-2, that is, the signal is changed. The amplified signal charges obtained by multiplying the slice-capacitance by the noise-free signal voltage having no noise component are transferred to the slice charge storage capacitors 24-1, 24-2.

Then, the horizontal selection transistor 12-
1, 12-2 are sequentially turned on to read out a signal without noise.

The important pulse in this type of noise canceller is the first slice pulse 119 for presetting the charge of the slice capacitance and the second slice pulse for transferring the charge proportional to the difference between the signal and noise to the drain of the slice transistor. is there. The trailing edges of these pulses are the load transistor activation pulse 106 that activates the load transistor.
Is in the imprinted period. The first noise suppression pulse described in the claims corresponds to the first slice pulse, and the second noise suppression pulse corresponds to the second slice pulse.

The leading edge of the first slice pulse 119 is not limited to the charge injection pulse 107, unlike the clamp pulse of the correlated double sampling type noise canceller.
The reason is that the vertical signal lines 8-1 and 8-2 are connected to the gates of the slice transistors 20-1 and 20-2, and it is not necessary to supply the charges that become amplified signals from the vertical signal lines. That is, the slice pulse 119 may be first applied after the charge injection pulse 107 is turned off. The same holds true for the relationship between the second slice pulse 120 and the noise detection charge injection pulse 124.

FIG. 21 is an improved version of FIG. The address pulse is divided into two. FIG. 22 shows a further improvement. A dummy address pulse 115-1 (115-2) is generated before the first address pulse. Similarly, a dummy charge injection pulse 125 is generated before the charge injection pulse 107. Further, the dummy address injection pulse 115-1 (115-2) and dummy charge injection pulse 1
In synchronism with 25, a dummy slice pulse 122 is generated before the first slice pulse 119. It is also possible to generate the dummy slice charge reset pulse 123 before the slice charge reset pulse 121.

[Embodiment 3] FIG. 23 shows the configuration of FIG. 7 with photodiodes 1-1-1, ...
Between the gates of 1-1, ...
1-1, 25-1-2, ..., 25-2-2 are inserted, and the gates thereof are connected to the transfer control lines 26-1 and 26-2 output from the vertical shift register 5.

Driving a sensor having this type of cell is shown in FIG.
4 (having a load transistor and a correlated double sampling type noise canceller), the reset transistor 4-1 of the addressed row (here, the first row).
The detection capacitance reset pulse 128-1 is applied to the 1, 4-1-2 from the reset line 7-1 to reset the charge detection node. At this time, the amplification transistors 2-1-1 and 2-1
A noise voltage including a threshold variation of −2 appears on the vertical signal lines 8-1 and 8-2.

Next, the charge transfer pulse 127-1 is transferred from the transfer control line 26-1 to the charge transfer transistors 25-1-1,
When applied to 25-1-2 and the signal charges of the photodiodes 1-1-1 and 1-1-2 are transferred to the charge detection node, a signal voltage appears on the vertical signal lines 8-1 and 8-2. Thus, the difference between the noise voltage and the signal voltage appearing in time series is extracted and output by the correlated double sampling type noise canceller, as in FIG. The next line operates and can be read in almost the same manner.

Again, the common gate 5 of the load transistors
1, the load transistor activation pulse 106 is applied only when noise and a signal are taken out to the vertical signal line. The difference between the noise canceller part and FIG. 8 is that the order in which noise and signals come is opposite, the operation is exactly the same, and the polarities of the output signals are opposite.

FIG. 25 is an improved version of the drive timing of FIG. 24, much like FIG. 9 modified from FIG. 10 important clamp pulses that determine noise and signal capture
9. The first address pulse 111-1 (111-2) is set for each time when there are trailing edges so that the states of the cells at the two trailing edges of the sample-hold pulse 110 are as similar as possible. Second address pulse 1
12-1 (112-2) is generated separately. Similarly, the first load transistor activation pulse 113 and the second load transistor activation pulse 114 are separately generated.

Furthermore, the time between the trailing edge of the clamp pulse 109 and the leading edge of the first address pulse 111-1 (111-2), the trailing edge of the sample and hold pulse 110 and the second address pulse 112-. 1 (112-2) leading edge to be approximately equal. Similarly, the trailing edge of the clamp pulse 109 and the first load transistor activation pulse 1
13 and leading edge of sample hold pulse 1
10 trailing edge and second load transistor activation pulse 114
Make the time between the leading edge of and almost equal.

FIG. 26 shows an improved drive timing of FIG. 25, which is similar to FIG. 10 obtained by improving FIG.
The state of the cell at the time of the trailing edge of the sample-hold pulse is affected not only by the leading edge of the second address pulse but also by the first address pulse. In order to make the state of the cell at the time of the trailing edge of the clamp pulse equal to that of the trailing edge of the sample and hold pulse, a dummy address pulse 115-1 (115-2) is generated before the first address pulse. . Similarly, for the load transistor activation pulse, a dummy load transistor activation pulse 116 is generated before the first load transistor activation pulse 113.

Further, the dummy address pulse 115-
1 (115-2) A dummy clamp pulse 117 is generated before the clamp pulse 109 in synchronization with the dummy load transistor activation pulse 116. It is the same as in the case of FIG. 10 that these dummy pulses do not have to be used together and only one is effective.

FIG. 27 shows the cell structure of FIG.
The load transistor / slice type noise canceller of No. 1 is combined. 28, 29, and 30 also show driving of the cells of FIGS. 24, 25, and 26, and FIG.
This is almost the same as the combination of the driving of the load transistor and the noise canceller of FIGS. 13 and 14.

Since the signal and the noise come in the opposite order, the channel type of the slice transistor is set as shown in FIGS.
It is better to reverse the one in FIG. Therefore, the polarities of the pulses applied to the common terminal 57 of the slice capacitors are reversed. Therefore, instead of the first slice pulse 119, the second slice pulse 120, and the dummy slice pulse 122, the third slice pulse 129 having the opposite polarity and the fourth slice pulse 129 are used.
Slice pulse 130 and dummy inversion slice pulse 131 are used.

FIG. 31 shows the cell structure of FIG.
5 is a combination of a vertical signal line reset transistor 5 and a correlated double sampling type noise canceller.
32, 33, and 34 are substantially the same as those obtained by combining the driving of the cells of FIGS. 24, 25, and 26 and the driving of the vertical signal line reset transistor / noise canceller of FIGS. 16, 17, and 18, respectively. .

FIG. 35 shows the cell structure of FIG.
9 is a combination of vertical signal line reset transistor / slice type noise canceller. 36 and 3
7 and 38 are substantially the same as those obtained by combining the driving of the cells of FIGS. 24, 25 and 26 with the driving of the vertical signal line reset transistor / noise canceller of FIGS. 20, 21 and 22, respectively. 27, 28, 29, and 30.
Similarly, the channel type of the slice transistor and the polarity of the slice pulse are opposite.

FIG. 39 is an operation diagram of the sensor of the circuit shown in FIG. 24 is different from the operation method of FIG. 24 in that the charge transfer pulse 127-1 is applied immediately after the charge detection capacitance reset pulse 128-1 is applied, the signal charge is transferred to the charge detection node, and the signal voltage is applied to the vertical signal line 8. -1,8-
2. Next, the second detection capacitance reset pulse 133-1 is applied to discharge the signal charge at the charge detection node. Immediately thereafter, the second charge transfer pulse 132-1 is applied. At this time, almost no electric charge is transferred, so
Noise voltage is induced in the vertical signal lines 8-1 and 8-2.

The difference between the noise voltage and the signal voltage appearing in time series in this way is extracted and output by the correlated double sampling type noise canceller as in FIG. The next line operates and can be read in almost the same manner. Here again, the load transistor activation pulse 106 is applied to the common gate 51 of the load transistor only when noise and a signal are taken out to the vertical signal line.

In this operating method, the detection capacitance reset pulse 128-1
Application of charge transfer pulse 127-1 and second detection capacitance reset pulse 133-1 and second charge transfer pulse 132-
Since the application of 1 is equivalent, the signal and noise can be extracted under conditions close to the same condition.

In FIG. 40, the address pulse and load transistor activation pulse are separated into two. FIG.
Are dummy address pulses 115-1, 115-2 ...
In addition to the dummy load transistor activation pulse 116 and the dummy clamp pulse 117, dummy detection capacitance reset pulses 134-1 and 134-2 are applied before the detection capacitance reset pulses 128-1 and 128-2.

FIG. 42 is an operation timing chart of the sensor shown in FIG. The operation of the cell is almost the same as that of FIG. 39, and the operation of the noise canceller is almost the same as that of FIG. Since the order of signal and noise generation is opposite to that of the operation of FIG. 28, the polarity of the slice pulse of the noise canceller is opposite, and the sensor of FIG.
It becomes the same as when moved at the operation timing of 2. A dummy slice charge reset pulse 123 can also be applied.

In FIG. 43, the address pulse / load transistor activation pulse is generated twice. FIG.
In addition to the dummy address pulse, the dummy load transistor activation pulse, and the dummy slice pulse, the second dummy slice charge reset pulse 135 is applied.

FIG. 45 is an operation diagram of the sensor shown in FIG. The cell is a combination of the operations in FIG. 39, and the noise canceller is a combination of the operations in FIG. In FIG. 46, the address pulse is divided into two. FIG. 47 is a combination of the operation of the cell of FIG. 41 and the operation of the noise canceller of FIG. 34.

FIG. 48 is an operation diagram of the sensor shown in FIG. This is almost the same as the combination of the operation of the cell of FIG. 39 and the operation of the noise canceller of FIG. That is, the polarities of the slice pulses are reversed and a dummy slice charge reset pulse may be generated. In FIG. 49, the address pulse is divided into two. 50 is almost the same as a combination of the operation of the cell of FIG. 41 and the operation of the noise canceller of FIG. The difference is that the second dummy slice charge reset pulse 135 can be generated and the polarity of the slice pulse is reversed.

The present invention is not limited to each of the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0119]

As described above in detail, according to the present invention, the current is passed through the load transistor only during the period in which the signal of the photodiode is amplified and transmitted to the vertical signal line and the amplified signal storage capacitor, and otherwise the current is passed. Power consumption can be reduced by reducing the amount of current.

Further, the vertical signal line reset transistor resets the vertical signal line in a short time, and the final signal is taken in when no current flows through the vertical signal line reset transistor. Both can be improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an amplification type solid-state imaging device in which a load transistor is pulse-driven.

FIG. 2 is an operation timing chart in pulse driving of the load transistor of FIG.

FIG. 3 is a circuit configuration diagram showing an amplification type solid-state imaging device that performs pulse driving of a load transistor and reset driving of a vertical signal line.

4 is an operation timing chart in the reset drive of FIG.

FIG. 5 is a diagram illustrating a phase relationship between a charge injection pulse and a signal acquisition pulse.

FIG. 6 is a diagram illustrating that the signal handling range is wide in the vertical signal line reset drive.

FIG. 7 is a circuit configuration diagram of a solid-state imaging device using a correlated double sampling type noise canceller and a load transistor.

8 is a driving timing chart of FIG. 7, in which one address pulse and one load transistor activation pulse are used for reading a signal and noise.

9 is a driving timing chart of FIG. 7, in which separate address pulses and load transistor activation pulses are used for reading signals and noise.

10 is a drive timing chart of FIG. 7, in which a dummy address pulse, a dummy load transistor activation pulse, and a dummy clamp pulse are used.

FIG. 11 is a circuit configuration diagram showing an amplification type solid-state imaging device using a slice type noise canceller and a load transistor.

FIG. 12 is a driving timing chart of FIG. 11, in which one address pulse and one load transistor activation pulse are used for reading a signal and noise.

FIG. 13 is a driving timing chart of FIG. 11, in which separate address pulses and load transistor activation pulses are used for reading signals and noise.

FIG. 14 is a driving timing chart of FIG. 11, in which a dummy address pulse, a dummy load transistor activation pulse, a dummy slice pulse, and a dummy slice charge reset pulse are used.

FIG. 15 is a circuit configuration diagram showing an amplification type solid-state imaging device using a correlated double sampling type noise canceller and a vertical signal line reset transistor.

FIG. 16 is a driving timing chart of FIG. 15, in which one address pulse is used for reading a signal and noise.

FIG. 17 is a driving timing chart of FIG. 15, in which different address pulses are used for reading a signal and noise.

FIG. 18 is a driving timing chart of FIG. 15, in which a dummy address pulse, a dummy charge injection pulse, and a dummy clamp pulse are used.

FIG. 19 is a circuit configuration diagram showing an amplification type solid-state imaging device using a slice type noise canceller and a vertical signal line reset transistor.

FIG. 20 is a driving timing chart of FIG. 19, in which one address pulse is used for reading a signal and noise.

FIG. 21 is a driving timing chart of FIG. 19, in which separate address pulses are used for reading a signal and noise.

FIG. 22 is a driving timing chart of FIG. 19, which uses a dummy address pulse, a dummy charge injection pulse, a dummy slice pulse, and a dummy slice charge reset pulse.

FIG. 23 is a circuit configuration diagram showing a solid-state imaging device using a correlated double sampling type noise canceller and a load transistor in a cell having a charge transfer transistor.

FIG. 24 is a driving timing chart of FIG. 23, in which one address pulse and one load transistor activation pulse are used for reading a signal and noise.

FIG. 25 is a driving timing chart of FIG. 23, in which separate address pulses and load transistor activation pulses are used for reading signals and noise.

FIG. 26 is a driving timing chart of FIG. 23, in which a dummy address pulse, a dummy load transistor activation pulse, and a dummy clamp pulse are used.

FIG. 27 is a circuit configuration diagram showing a solid-state imaging device using a slice noise canceller and a load transistor in a cell having a charge transfer transistor gate.

FIG. 28 is a driving timing chart of FIG. 27, in which one address pulse and one load transistor activation pulse are used for reading a signal and noise.

FIG. 29 is a driving timing chart of FIG. 27, in which separate address pulses and load transistor activation pulses are used for reading signals and noise.

30 is a driving timing chart of FIG. 27, in which a dummy address pulse, a dummy load transistor activation pulse, a dummy slice pulse, and a dummy slice charge reset pulse are used.

FIG. 31 is a circuit configuration diagram showing an amplification type solid-state imaging device using a correlated double sampling type noise canceller and a vertical signal line reset transistor in a cell having a charge transfer transistor.

32 is a driving timing chart of FIG. 31, in which one address pulse is used for reading a signal and noise.

FIG. 33 is a driving timing chart of FIG. 31, in which different address pulses are used for reading a signal and noise.

FIG. 34 is a drive timing chart of FIG. 31, using a dummy address pulse, a dummy charge injection pulse, and a dummy clamp pulse.

FIG. 35 is a circuit configuration diagram showing an amplification type solid-state imaging device using a slice type noise canceller and a vertical signal line reset transistor in a cell having a charge transfer transistor.

FIG. 36 is a driving timing chart of FIG. 35, in which one address pulse is used for reading a signal and noise.

FIG. 37 is a driving timing chart of FIG. 35, in which separate address pulses are used for reading a signal and noise.

38 is a drive timing chart of FIG. 35, in which a dummy address pulse, a dummy charge injection pulse, a dummy slice pulse, and a dummy slice charge reset pulse are used.

FIG. 39 is a drive timing chart for detecting a signal and noise in order in FIG. 23, which uses one address pulse and one load transistor activation pulse for reading a signal and noise.

FIG. 40 is a driving timing chart for detecting a signal and noise in order in FIG. 23, in which separate address pulses and load transistor activation pulses are used for reading signals and noise.

41 is a drive timing chart for detecting signals and noise in order in FIG. 23, using a dummy address pulse, a dummy load transistor activation pulse, and a dummy clamp pulse.

FIG. 42 is a drive timing chart for detecting a signal and noise in order in FIG. 27, using one address pulse and one load transistor activation pulse for signal and noise reading.

FIG. 43 is a drive timing chart for detecting a signal and a noise in order in FIG. 27, in which separate address pulses and load transistor activation pulses are used for reading signals and noise.

FIG. 44 is a driving timing chart for detecting signals and noises in order in FIG. 27, using a dummy address pulse, a dummy load transistor activation pulse, a dummy slice pulse, and a dummy slice charge reset pulse.

FIG. 45 is a drive timing chart for detecting a signal and noise in order in FIG. 31, which uses one address pulse for reading a signal and noise.

FIG. 46 is a drive timing chart for detecting a signal and a noise in order in FIG. 31, using different address pulses for reading a signal and a noise.

FIG. 47 is a driving timing chart for detecting a signal and a noise in order in FIG. 31, using a dummy address pulse, a dummy charge injection pulse, and a dummy clamp pulse.

FIG. 48 is a drive timing chart for detecting a signal and a noise in order in FIG. 35, which uses one address pulse for reading the signal and the noise.

FIG. 49 is a driving timing chart for detecting a signal and a noise in order in FIG. 35, in which separate address pulses are used for reading a signal and a noise.

FIG. 50 is a drive timing chart for detecting signals and noise in order in FIG. 35, using a dummy address pulse, a dummy charge injection pulse, a dummy slice pulse, and a dummy slice charge reset pulse.

FIG. 51 is a circuit configuration diagram showing an example of a conventional amplification type solid-state imaging device.

52 is an operation timing chart of the solid-state imaging device of FIG. 51.

FIG. 53 is a diagram illustrating that a signal handling range of a circuit including an amplification transistor and a load transistor is narrow.

[Explanation of symbols]

1-1-1, 1-1-2, ~, 1-2-2: Photodiode 2-1-1, 2-1-2, ~, 2-2-2: Amplifying transistor 3-1-1, 3-1-2, ~, 3-2-2: vertical selection transistor 4-1-1, 4-1-2, ~, 4-2-2: reset transistor 5: vertical shift register 6-1, 6- 2: Horizontal address lines 7-1, 7-2: Reset line 8-1, 8-2: Vertical signal line 9-1, 9-2: Load transistor 10-1, 10-2: Signal acquisition transistor 11-1 , 11-2: Amplified signal storage capacitors 12-1, 12-2: Horizontal selection transistor 13: Horizontal shift register 14-1, 14-2: Load transistor 15-1, 15-2: Vertical signal line reset transistor 16- 1, 16-2: Clamping capacity 17-1, 17-2: Clan Transistors 18-1, 18-2: Sample and hold transistors 19-1, 19-2: Hold capacitors 20-1, 20-2: Slice transistors 21-1, 21-2: Slice capacitors 22-1, 22-2 : Slice Source Reset Transistors 23-1, 23-2: Slice Drain Reset Transistors 24-1, 24-2: Slice Charge Storage Capacitors 25-1-1, 25-1-2, ~, 25-2-2: Charge Transfer transistors 26-1 and 26-2: Transfer control line 49: Common gate of signal acquisition transistor 50: Horizontal signal line 51: Common gate electrode of pulse-driven load transistor 52: Common gate electrode of vertical signal line reset transistor 53: Common source of vertical signal line reset transistor 54: Common source of clamp transistor Reference numeral 55: common gate of clamp transistor 56: common gate of sample hold transistor 57: common terminal of slice capacitance 58: common gate of slice source reset transistor 60: common drain of slice drain reset transistor 61: common gate of slice drain reset transistor 101-1, 101-2: Address pulse 102-1, 102-2: Signal reset pulse 103: Signal capture pulse 104-1, 104-2: Horizontal selection pulse 105-1, 105-2: Output signal 106: Load Transistor activation pulse 107: Charge injection pulse 108: Leading edge of signal capture pulse 103 109: Clamp pulse 110: Sample hold pulse 111-1, 111-2: First address pulse 112-1 112-2: second address pulse 113: first load transistor activation pulse 114: second load transistor activation pulse 115-1, 115-2: dummy address pulse 116: dummy load transistor activation pulse 117: dummy Clamp pulse 118: Slice source reset pulse 119: First slice pulse 120: Second slice pulse 121: Slice charge reset pulse 122: Dummy slice pulse 123: Dummy slice charge reset pulse 124: Noise detection charge injection Pulse 125: Dummy charge injection pulse 126: Dummy clamp pulse 127-1, 127-2: Charge transfer pulse 128-1, 128-2: Detection capacitance reset pulse 129: Third slice pulse 130: Fourth slice Pulse 131: Dummy inversion slice pulse 132-1 and 132-2: Second charge transfer pulse 133-1 and 133-2: Second detection capacitance reset pulse 134-1 and 134-2: Dummy detection capacitance reset Pulse 135: Second dummy slice charge reset pulse 201: Period of extracting detection signal to vertical signal line / amplified signal storage capacitor 202: Period other than period 201

Claims (32)

[Claims] 1. An image pickup area in which photosensitive cells each comprising a photoelectric conversion means, a signal charge storage means, a signal charge discharge means, a row selection means, and an amplification means are two-dimensionally arranged on a semiconductor substrate, and a row is formed in this image pickup area. Direction, a plurality of vertical selection lines, vertical selection means for driving these vertical selection lines, a plurality of vertical signal lines arranged in the column direction for reading the output of the amplification means, and these vertical signal lines. A plurality of vertical signal line drive assisting means provided, a row signal accumulating means provided at an end of the vertical signal line, a signal fetching means for transmitting a signal of the vertical signal line to the row signal accumulating means, and a row signal accumulating means. An amplification type solid state equipped with a horizontal signal line arranged adjacent to each other in the row direction, a horizontal reading means for connecting the horizontal signal line and the row signal accumulating means, and a horizontal selecting means for driving the horizontal reading means. In the imaging device, There is a first horizontal period during which a signal is read out to the horizontal signal line through the horizontal read-out means and a second horizontal period other than that, within the second horizontal period or within the first and second horizontal periods. A solid-state imaging device, characterized in that the current flowing through the vertical signal line drive assisting means is changed at the boundary of the. 2. An address pulse generated in the second horizontal period from the vertical selection means, transmitted through the vertical selection line, applied to the row selection means, and activating the amplification means of the selected row or rows. And a vertical signal line driving pulse applied to the vertical signal line driving auxiliary means and causing a current to flow through the vertical signal line auxiliary means overlap each other, and a signal of the vertical signal line is taken into the row signal storage means. 2. The solid-state imaging device according to claim 1, wherein the trailing edge of the signal capturing pulse applied to the signal capturing means is in the overlap period of the address pulse and the vertical signal line driving pulse. 3. The solid-state image pickup device according to claim 2, wherein the vertical signal line drive assisting means is a load MOS transistor. 4. An address pulse generated in the second horizontal period from the vertical selection means, transmitted through the vertical selection line, applied to the row selection means, and activating the amplification means of the selected row or rows. And a vertical signal line driving pulse applied to the vertical signal line driving auxiliary means and flowing a current to the vertical signal line auxiliary means overlap each other, and when the signal of the vertical signal line is taken into the row signal accumulating means. 2. The solid-state imaging device according to claim 1, wherein the trailing edge of the signal capture pulse applied to the signal capture means is in a period in which the address pulse is ON and the vertical signal line drive pulse is OFF. 5. The solid-state imaging device according to claim 4, wherein the leading edge of the signal capture pulse is within the ON period of the vertical signal line drive pulse or before the OFF period. 6. The amplifying means is a MOS transistor, and the leading edge of the signal capture pulse is a vertical signal line drive pulse OF.
5. The solid-state imaging device according to claim 4, wherein after F, the amplification transistors in the selected row are in a period in which they are in a strong inversion state. 7. An image pickup area in which photosensitive cells each comprising a photoelectric conversion means, a signal charge storage means, a signal charge discharge means, a row selection means, and an amplification means are two-dimensionally arranged on a semiconductor substrate, and a row is formed in this image pickup area. Direction, a plurality of vertical selection lines, vertical selection means for driving these vertical selection lines, a plurality of vertical signal lines arranged in the column direction for reading the output of the amplification means, and these vertical signal lines. A plurality of vertical signal line drive assisting means provided, a noise suppressing means which is provided at the end of the vertical signal line and takes in and subtracts noise and signals appearing with a time difference in the vertical signal line, and a line adjacent to the noise suppressing means. In the amplification type solid-state imaging device, which includes a horizontal signal line arranged in a direction, a horizontal reading unit that connects the horizontal signal line and the output of the noise suppressing unit, and a horizontal selecting unit that drives the horizontal reading unit, There is a first horizontal period during which a signal is read out through the horizontal reading means through the horizontal signal line and a second horizontal period other than that, and the vertical selection means generates the second horizontal period and the vertical selection. An address pulse transmitted via a line and applied to the row selecting means to activate the amplifying means of the selected row or rows, and a current applied to the vertical signal line driving auxiliary means to flow a current through the vertical signal line auxiliary means. There is a period in which the vertical signal line drive pulse overlaps, before the signal charge accumulated in the signal charge accumulation means of the selected row is discharged by the signal charge discharge means, and at the same time as the address pulse and the vertical signal. Within the overlap period of the line drive pulse, there is a trailing edge of the first noise suppression pulse that receives the signal applied to the noise suppression means and is generated in the vertical signal line and holds the state, and the signal of the selected row is detected. After the signal charge accumulated in the charge accumulating means is discharged by the signal charge discharging means of the selected row, and within the overlap period of the address pulse and the vertical signal line drive pulse, the vertical signal applied to the noise suppressing means is applied. A solid-state imaging device having a trailing edge of a second noise suppression pulse for generating a difference signal from a signal for capturing noise generated in a line. 8. A first address pulse generated in a second horizontal period before the signal charge accumulated in the signal charge accumulation means of the selected row is discharged by the signal charge discharge means of the selected row. And the first vertical signal line drive pulse overlap with the trailing edge of the first noise suppression pulse, and the signal charge stored in the signal charge storage means of the selected row is the signal of the selected row. After being discharged by the charge discharging means, there is a trailing edge of the second noise suppression pulse within the overlap period of the second address pulse and the second vertical signal line drive pulse generated in the second horizontal period. The solid-state imaging device according to claim 7, wherein 9. A single or a plurality of dummy address pulses, a single or a plurality of dummy vertical signal line drive pulses, and a first address pulse, a first vertical signal line drive pulse and a first noise suppression pulse. 9. The solid-state imaging device according to claim 8, wherein one or a plurality of dummy noise suppression pulses are present. 10. An image pickup area in which photosensitive cells, which are composed of photoelectric conversion means, signal charge storage means, signal charge discharge means, row selection means, and amplification means, are two-dimensionally arranged on a semiconductor substrate.
A plurality of vertical selection lines arranged in the row direction in this imaging region,
Vertical selection means for driving these vertical selection lines, a plurality of vertical signal lines arranged in the column direction for reading the output of the amplification means, and a plurality of vertical signal line drive auxiliary means provided for these vertical signal lines. , Noise suppression means provided at the end of the vertical signal line for capturing and subtracting noise and signals appearing in the vertical signal line with a time difference, horizontal signal lines arranged in the row direction adjacent to the noise suppression means, and the horizontal signal line In an amplification type solid-state imaging device equipped with a horizontal readout means for connecting a selection line and an output of the noise suppression means, and a horizontal selection means for driving the horizontal readout means, a signal is transmitted to the horizontal signal line via the horizontal readout means. There is a first horizontal period being read and a second horizontal period other than that, and a first vertical signal line drive pulse is applied to the vertical signal line drive assisting means and a current is passed through the vertical signal line assisting means. The trailing edge is generated in the second horizontal period from the vertical selection unit before the signal charges stored in the signal charge storage unit of the selected row are discharged by the signal charge discharging unit, and is generated via the vertical selection line. A signal which is transmitted and applied to the row selecting means and which is in an address pulse for activating the amplifying means of the selected row or rows, and which receives the signal applied to the noise suppressing means and is generated in the vertical signal line and holds the state; The trailing edge of the noise suppression pulse of 1 is in the period in which the address pulse is ON and the first vertical signal line drive pulse is OFF, and the trailing edge of the second vertical signal line drive pulse is in the selected row. After the signal charge accumulated in the signal charge accumulating unit is discharged by the signal charge discharging unit and within the address pulse, the noise is generated during the period when the address pulse is ON and the second vertical signal line drive pulse is OFF. A solid-state image pickup device, characterized in that there is a trailing edge of a second noise suppression pulse for generating a difference signal from a signal which is loaded with noise generated in a vertical signal line and applied to the suppression means. 11. A signal stored in the signal charge storage means of a selected row at the trailing edge of a first vertical signal line drive pulse applied to the vertical signal line drive auxiliary means and causing a current to flow through the vertical signal line auxiliary means. Before the charges are discharged by the signal charge discharging means, the single or a plurality of rows which are generated from the vertical selecting means within the second horizontal period, are transmitted through the vertical selecting lines and are applied to the row selecting means are selected. The trailing edge of the first noise suppression pulse, which is in the first address pulse for activating the means and takes in the signal applied to the noise suppression means and generated in the vertical signal line and holds the state, is the first address pulse. Is ON and the first vertical signal line drive pulse is OFF, and the trailing edge of the second vertical signal line drive pulse is the signal charge stored in the signal charge storage means of the selected row. By charge discharging means After being issued and within the second address pulse, while the second address pulse is ON and the second vertical signal line drive pulse is OFF, it is applied to the noise suppressing means and is generated in the vertical signal line. 11. The solid-state imaging device according to claim 10, wherein there is a trailing edge of a second noise suppression pulse that generates a difference signal from a signal that captures noise. 12. A single or a plurality of dummy address pulses, a single or a plurality of dummy vertical signal line drive pulses, and a first address pulse, a first vertical signal line drive pulse, and a first noise suppression pulse. The solid-state imaging device according to claim 11, wherein one or more dummy noise suppression pulses are present. 13. A photoelectric conversion means, a signal charge storage means, a charge voltage conversion means, a charge transfer means for transferring a signal charge from the signal charge storage means to the charge voltage conversion means, and a charge discharged from the charge voltage conversion means on a semiconductor substrate. Means for discharging the signal charge,
An image pickup area in which photosensitive cells each composed of a row selection means and an amplification means are arranged in a secondary shape; a plurality of vertical selection lines arranged in the row direction in the image pickup area; and a vertical selection means for driving the vertical selection lines, A plurality of vertical signal lines arranged in the column direction for reading the output of the amplification means, a plurality of vertical signal line drive assisting means provided on the plurality of vertical signal lines, and a vertical signal line provided at the end of the vertical signal line. Noise suppression means for capturing and subtracting noise and signals appearing with a time difference, horizontal signal lines arranged in the row direction adjacent to the noise suppression means, and horizontal readout means for connecting the horizontal selection line and the output of the noise suppression means. In the amplification type image pickup apparatus including: and a horizontal selection unit that drives the horizontal readout unit, a first horizontal period in which a signal is read out to the horizontal signal line through the horizontal readout unit, and a first horizontal period other than that. 2 horizontal periods And an address pulse generated in the second horizontal period from the vertical selection means, transmitted through the vertical selection line, applied to the row selection means, and activating the amplification means of the selected row or rows. , The signal accumulated in the signal charge accumulating means of the selected row has a period in which the vertical signal line driving pulse applied to the vertical signal line auxiliary means overlaps with the vertical signal line driving pulse for supplying a current to the vertical signal line auxiliary means. Before the charge is transferred to the charge-voltage conversion means by the charge transfer means, and within the overlap period of the address pulse and the vertical signal line drive pulse, the noise generated in the vertical signal line is applied to the noise suppressing means and the state is taken in. After the signal charge stored in the signal charge storage means of the selected row is transferred to the charge-voltage conversion means by the charge transfer means. Further, in the overlap period of the address pulse and the vertical signal line drive pulse, the trailing edge of the fourth noise suppression pulse for generating the difference signal from the noise which is applied to the noise suppression means and takes in the signal generated in the vertical signal line is generated. A solid-state imaging device characterized by the following. 14. A first means which is generated from a vertical selection means in a second horizontal period, is transmitted through a vertical selection line, is applied to a row selection means, and activates the amplification means of the selected row or rows. Of the selected row, there is a period in which the address pulse of 1) and the first vertical signal line driving pulse applied to the vertical signal line driving auxiliary means and causing a current to flow through the vertical signal line auxiliary means overlap each other. Before the signal charge accumulated in the accumulating means is transferred to the charge-voltage converting means by the charge transferring means, and within the overlap period of the first address pulse and the first vertical signal line driving pulse, the noise suppressing means operates. There is a trailing edge of the third noise suppression pulse that captures the noise generated in the vertical signal line and holds the state thereof, and the signal charge accumulated in the signal charge accumulation means of the selected row is charged by the charge transfer means. After being transferred to the voltage conversion means, a pulse of the second address pulse and a pulse of the second vertical signal line drive pulse is generated, and a signal applied to the noise suppression means and generated on the vertical signal line is generated within the overlap period. 14. The solid-state image pickup device according to claim 13, wherein there is a trailing edge of a fourth noise suppression pulse that generates a difference signal with respect to captured noise. 15. A dummy address pulse or a plurality of dummy address pulses, a dummy vertical signal line drive pulse or a plurality of dummy address pulses before the first address pulse, the first vertical signal line drive pulse and the third noise suppression pulse. 15. The solid-state imaging device according to claim 14, wherein one or a plurality of dummy noise suppression pulses are present. 16. A photoelectric conversion means, a signal charge storage means, a charge voltage conversion means, a charge transfer means for transferring a signal charge from the signal charge storage means to the charge voltage conversion means, and a charge discharged from the charge voltage conversion means on a semiconductor substrate. Means for discharging the signal charge,
An image pickup area in which photosensitive cells composed of row selection means and amplification means are two-dimensionally arranged, a plurality of vertical selection lines arranged in the image pickup area in the row direction, vertical selection means for driving the vertical selection lines, and amplification. A plurality of vertical signal lines arranged in the column direction for reading the output of the means, a plurality of vertical signal line drive assisting means provided on the plurality of vertical signal lines, and a time difference between the vertical signal lines provided at the ends of the vertical signal lines. Noise suppression means for taking in and subtracting noise and signals appearing with, horizontal signal lines arranged in the row direction adjacent to the noise suppression means, and horizontal readout means for connecting the horizontal selection line and the output of the noise suppression means A first horizontal period during which a signal is read out to the horizontal signal line through the horizontal reading means, and a second horizontal portion other than the above. Horizontal period of And an address pulse generated in the second horizontal period from the vertical selection means, transmitted through the vertical selection line, applied to the row selection means, and activating the amplification means of the selected row or rows. , The signal accumulated in the signal charge accumulating means of the selected row has a period in which the vertical signal line driving pulse applied to the vertical signal line auxiliary means overlaps with the vertical signal line driving pulse for supplying a current to the vertical signal line auxiliary means. After the first transfer operation in which the charge is transferred to the charge-voltage conversion unit by the charge transfer unit, it is applied to the noise suppression unit and generated in the vertical signal line within the overlap period of the address pulse and the vertical signal line drive pulse. There is a trailing edge of the first noise suppression pulse that takes in the signal and holds the state, and after the signal charge of the charge-voltage conversion means is discharged through the charge discharging means, the address pulse and the vertical signal line driving are performed. Solid-state imaging, characterized in that there is a trailing edge of a second noise suppression pulse which takes in a signal applied to a noise suppression means and which is generated in a vertical signal line and generates a difference signal with noise within an overlap period with the pulse. apparatus. 17. A second transfer operation in which the signal charge of the charge-voltage converting means is discharged through the charge discharging means, and the signal transfer means performs the idle transfer with almost no signal to the charge-voltage converting means by the charge transfer means, In the overlap period of the address pulse and the vertical signal line drive pulse, there is a trailing edge of the second noise suppression pulse that is applied to the noise suppression means and takes in the signal generated in the vertical signal line to generate a difference signal with noise. The solid-state imaging device according to claim 16, which is characterized in that. 18. A first horizontal period in which a signal is read out to the horizontal signal line through the horizontal reading means and a second horizontal period other than that exist, and the vertical selection means changes the second horizontal period to the second horizontal period. A first address pulse that is generated, transmitted through the vertical selection line and applied to the row selection means, and activates the amplification means of the selected row or rows, and a vertical signal line that is applied to the vertical signal line driving auxiliary means. There is a period in which the first vertical signal line drive pulse for supplying a current to the signal line auxiliary means overlaps, and the signal charge accumulated in the signal charge accumulating means in the selected row is charged by the charge transfer means. After the first transfer operation transferred to the conversion means, the signal applied to the noise suppression means and generated on the vertical signal line is captured within the overlap period of the first address pulse and the first vertical signal line drive pulse. The state There is a trailing edge of the first noise suppression pulse that holds, and the second address pulse and the second vertical signal line drive pulse are generated after the signal charge of the charge-voltage converting means is discharged through the charge discharging means. 18. The trailing edge of a second noise suppression pulse, which is included in the overlap period and generates a difference signal from the noise that is applied to the noise suppression means and takes in the signal generated in the vertical signal line, 18. Solid-state imaging device. 19. A second transfer operation, in which the signal charge of the charge-voltage conversion means is discharged through the charge discharging means, and the signal transfer means performs the empty transfer with almost no signal to the charge-voltage conversion means by the charge transfer means, Second noise that generates a second address pulse and a second vertical signal line drive pulse, takes in a signal that is applied to the noise suppression means within the overlap period thereof, and that is generated in the vertical signal line, and generates a difference signal from noise. 19. The solid-state imaging device according to claim 18, wherein there is a trailing edge of the suppression pulse. 20. A single or a plurality of dummy address pulses, a single or a plurality of dummy vertical signal line drive pulses, before the first address pulse, the first vertical signal line drive pulse and the first noise suppression pulse. 20. The solid-state imaging device according to claim 18, wherein one or more dummy noise suppression pulses are present. 21. A photoelectric conversion means, a signal charge storage means, a charge voltage conversion means, a charge transfer means for transferring a signal charge from the signal charge storage means to the charge voltage conversion means, and a charge discharged from the charge voltage conversion means on a semiconductor substrate. Means for discharging the signal charge,
An image pickup area in which photosensitive cells composed of row selection means and amplification means are two-dimensionally arranged, a plurality of vertical selection lines arranged in the image pickup area in the row direction, vertical selection means for driving the vertical selection lines, and amplification. A plurality of vertical signal lines arranged in the column direction for reading the output of the means, a plurality of vertical signal line drive assisting means provided on the plurality of vertical signal lines, and a time difference between the vertical signal lines provided at the ends of the vertical signal lines. Noise suppression means for taking in and subtracting noise and signals appearing with, horizontal signal lines arranged in the row direction adjacent to the noise suppression means, and horizontal readout means for connecting the horizontal selection line and the output of the noise suppression means A first horizontal period during which a signal is read out to the horizontal signal line through the horizontal reading means, and a second horizontal portion other than the above. Horizontal period of And the trailing edge of the first vertical signal line drive pulse applied to the vertical signal line drive assisting means and flowing a current through the vertical signal line assisting means is the signal charge accumulated in the signal charge accumulating means of the selected row. Before being transferred to the charge-voltage conversion means by the charge transfer means, the single or plural selected ones generated from the vertical selection means within the second horizontal period and transmitted through the vertical selection line and applied to the row selection means. When the address pulse is ON, the trailing edge of the third noise suppression pulse that is in the address pulse that activates the amplification means of the row and that captures the noise that is applied to the noise suppression means and that is generated in the vertical signal line and holds that state Further, the first vertical signal line drive pulse is in the OFF period, and the trailing edge of the second vertical signal line drive pulse is such that the signal charge stored in the signal charge storage means of the selected row is transferred by the charge transfer means. Electric charge After being transferred to the conversion means and within the address pulse, while the address pulse is ON and the second vertical signal line drive pulse is OFF, the signal applied to the noise suppressing means and generated on the vertical signal line is taken in. A solid-state imaging device having a trailing edge of a fourth noise suppression pulse for generating a difference signal from the signal. 22. A signal, wherein the trailing edge of a first vertical signal line drive pulse applied to the vertical signal line drive assisting means and causing a current to flow through the vertical signal line assisting means, is stored in the signal charge storage means of the selected row. Before the charge is transferred to the charge-voltage conversion means by the charge transfer means, a single or a plurality of charges which are generated from the vertical selection means within the second horizontal period and transmitted through the vertical selection lines and applied to the row selection means are selected. In the first address pulse for activating the amplifying means of the row, and the trailing edge of the third noise suppressing pulse that captures and holds the noise applied to the noise suppressing means and generated in the vertical signal line is 1 address pulse is ON and the first vertical signal line drive pulse is OFF, and the trailing edge of the second vertical signal line drive pulse is stored in the signal charge storage means of the selected row. Signal charge transfer After it has been transferred to the charge-voltage converting means by the step and the second
Signal within the address pulse, the second address pulse is ON and the second vertical signal line drive pulse is OFF, the signal applied to the noise suppressing means and generated on the vertical signal line is a difference signal from the captured signal. 22. The solid-state imaging device according to claim 21, wherein there is a trailing edge of the fourth noise suppression pulse that generates the noise. 23. A single or a plurality of dummy address pulses, a single or a plurality of dummy vertical signal line drive pulses, and a first address pulse, a first vertical signal line drive pulse and a first noise suppression pulse. 23. The solid-state imaging device according to claim 22, wherein one or a plurality of dummy noise suppression pulses are present. 24. A photoelectric conversion means, a signal charge storage means, a charge voltage conversion means, a charge transfer means for transferring a signal charge from the signal charge storage means to the charge voltage conversion means, and a charge discharged from the charge voltage conversion means on a semiconductor substrate. Means for discharging the signal charge,
An image pickup area in which photosensitive cells composed of row selection means and amplification means are two-dimensionally arranged, a plurality of vertical selection lines arranged in the image pickup area in the row direction, vertical selection means for driving the vertical selection lines, and amplification. A plurality of vertical signal lines arranged in the column direction for reading the output of the means, a plurality of vertical signal line drive assisting means provided on the plurality of vertical signal lines, and a time difference between the vertical signal lines provided at the ends of the vertical signal lines. Noise suppression means for capturing and subtracting noise and signals appearing with, horizontal signal lines arranged in the row direction adjacent to the noise suppression means, and horizontal readout means for connecting the horizontal selection line and the output of the noise suppression means A first horizontal period during which a signal is read out to the horizontal signal line through the horizontal reading means, and a second horizontal portion other than the above. Horizontal period of And the trailing edge of the first vertical signal line drive pulse applied to the vertical signal line drive assisting means and flowing a current through the vertical signal line assisting means is the signal charge accumulated in the signal charge accumulating means of the selected row. Is transferred to the charge-voltage conversion means by the charge transfer means.
After the transfer operation, the address pulse which is generated from the vertical selection means within the second horizontal period, is transmitted through the vertical selection line, is applied to the row selection means, and activates the amplification means of the selected row or rows. And the trailing edge of the first noise suppression pulse that receives the signal that is applied to the noise suppression means and that is generated in the vertical signal line and holds the state is that the address pulse is ON and the first vertical signal line drive pulse is In the OFF period, the trailing edge of the second vertical signal line drive pulse is in the address pulse after discharging the signal charge of the charge-voltage converting means through the charge discharging means, and the address pulse is ON. Further, while the second vertical signal line drive pulse is OFF, there is a trailing edge of the second noise suppression pulse which generates a difference signal from the signal which is applied to the noise suppression means and takes in the noise generated in the vertical signal line. The solid-state imaging device according to claim. 25. The trailing edge of the second vertical signal line drive pulse is
After the second transfer operation in which the signal charge of the charge-voltage converting means is discharged through the charge discharging means, and the signal transfer means performs the empty transfer with almost no signal to the charge-voltage converting means by the charge transfer means, and within the address pulse. In the period in which the address pulse is ON and the second vertical signal line drive pulse is OFF, the first noise which is applied to the noise suppressing means and which takes in the noise generated in the vertical signal line and generates a difference signal from the signal is generated. 25. The solid-state imaging device according to claim 24, wherein there is a trailing edge of the suppression pulse. 26. A signal, wherein the trailing edge of a first vertical signal line drive pulse applied to the vertical signal line drive assisting means and causing a current to flow through the vertical signal line assisting means, is stored in the signal charge storage means of the selected row. After the first transfer operation in which the charge is transferred to the charge-voltage conversion means by the charge transfer means, the charge is transferred from the vertical selection means to the second transfer operation.
Within a first address pulse that is generated during the horizontal period of time, transmitted through the vertical selection line, applied to the row selection means and activating the amplification means of the selected row or rows, and is applied to the noise suppression means. The trailing edge of the first noise suppression pulse that takes in the signal generated in the vertical signal line and holds the state is in the period in which the first address pulse is ON and the first vertical signal line drive pulse is OFF, The trailing edge of the second vertical signal line driving pulse is after the signal charge of the charge-voltage converting means is discharged through the charge discharging means and within the second address pulse, and the second address pulse is ON. In the period in which the second vertical signal line drive pulse is OFF, there is a trailing edge of the second noise suppression pulse that generates a difference signal from the signal that is applied to the noise suppression means and takes in the noise generated in the vertical signal line. Characterized by The solid-state imaging device according to claim 25, wherein that. 27. The trailing edge of the second vertical signal line drive pulse is
After the second transfer operation in which the signal charge of the charge-voltage converting means is discharged through the charge discharging means, and the signal transfer means performs the empty transfer with almost no signal to the charge-voltage converting means by the charge transfer means, and after the second transfer operation. Within the address pulse, while the second address pulse is ON and the second vertical signal line drive pulse is OFF, noise generated in the vertical signal line applied to the noise suppressing means is taken in and a difference signal from the signal is obtained. 27. The solid-state imaging device according to claim 26, wherein there is a trailing edge of the generated second noise suppression pulse. 28. A single or a plurality of dummy address pulses, a single or a plurality of dummy vertical signal line drive pulses, and a first address pulse, a first vertical signal line drive pulse and a first noise suppression pulse. 25. One or more dummy noise suppression pulses are present.
27. The solid-state imaging device according to any one of 27. 29. The noise suppressing means is of a type that produces a difference signal between noise and a signal in the voltage domain, and the leading edge of the first noise suppressing pulse is within or before the first vertical signal line drive pulse, 11. The leading edge of the second noise suppression pulse is within or before the second vertical signal line suppression pulse.
To 12, 24 to 27. The solid-state imaging device according to any one of. 30. The noise suppressing means is of a type that produces a difference signal between noise and a signal in the voltage domain, and the leading edge of the third noise suppressing pulse is in or before the first vertical signal line drive pulse, 22. The leading edge of the fourth noise suppression pulse is within or before the second vertical signal line suppression pulse.
23. The solid-state imaging device according to any one of to 23. 31. The amplifying means is a MOS transistor,
The noise suppression means is of a type that produces a difference signal between noise and a signal in the voltage domain, and the leading edge of the first noise suppression pulse is a strong inversion of the amplification transistor addressed after the first vertical signal line drive pulse is turned off. 28. The solid-state image pickup device according to claim 10, wherein the solid-state image pickup device is in a state of being in a state. 32. The amplifying means is a MOS transistor,
The noise suppression means is of a type that produces a difference signal between noise and a signal in the voltage domain, and the leading edge of the third noise suppression pulse is a strong inversion of the amplification transistor addressed after the first vertical signal line drive pulse is turned off. 24. The solid-state imaging device according to claim 21, wherein the solid-state imaging device is in a state of being in a state.