JPH09247401A - Picture processor and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the reduction of a gate array scale, the erasion of a local memory and flexible configuration by providing a control means for reading stored data, writing it in a storing means after a picture processing and controlling the reading and writing. SOLUTION: CPU 101 executes the control of a whole processor. A memory 102 stores picture data and binary difference. A difference extending part (ED) 103 binalizes multilevel (one picture element:eight-bit) picture data by a difference diffusion method. A DMA controller 104 controls picture data transfer with the memory 102. An I/O port 105 inputs picture data together with a scanner/printer 106 (or both by configuration). Then, I/F 107 transfers picture data to another device connected to this processor. CPU 101 performs access to the difference diffusion part (ED) 103 and executes management in output picture data being the result and a binary difference buffer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method for image processing multivalued data read by a scanner device or CG image data synthesized by a computer by using, for example, an error diffusion method. is there.

[0002]

2. Description of the Related Art In a conventional image processing apparatus, when the image data is binarized by an error diffusion method in a scanner or the like, the image data is binarized by hardware, and the image data is stored in the memory of the apparatus by using DMA. Take it in or just use another I /
Only data is transferred by F. Similarly, in the printer device, the same data transfer is performed after the binarization processing is performed on the input side. The reason is 2
This is because it is unrealistic to perform the binarization processing by the CPU in view of the processing speed of the CPU.

[0003]

However, the above-mentioned conventional example has the following problems.

Since the image data taken in by the CPU is binary data, it is difficult for the CPU to perform image processing such as changing the brightness of the image data. It is necessary to design a gate array which has a complicated structure due to cost increase.

Further, the binarization processing unit needs a local memory for accumulating the binarization error, and if other image processing such as changing the brightness is performed, the memory is required in addition to the above, which further increases the cost. It takes.

The present invention has been made to solve the above-mentioned problems, and uses a simple hardware capable of high-speed processing even if binarization processing is performed by using a CPU, thereby reducing the scale of the gate array and performing local processing. An object of the present invention is to provide an image processing apparatus and method capable of realizing a flexible configuration in memory deletion and image processing.

[0007]

In order to achieve the above object, the image processing apparatus of the present invention has the following configuration.

That is, storage means for storing image data,
The reading means for reading the image data accumulated in the accumulating means, the image processing means for performing a predetermined image processing on the image data read by the reading means, and the image data image-processed by the image processing means are A writing unit that writes data in the storage unit and a control unit that controls reading or writing in the storage unit are provided.

In order to achieve the above object, the image processing method according to the present invention has the following steps.

That is, the image data accumulated in the accumulating means is read, the read image data is subjected to predetermined image processing, the image-processed image data is written in the accumulating means, and read out to the accumulating means. Each step of controlling writing is included.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of an image processing apparatus according to this embodiment. In the figure, 101 is a CPU, which controls the entire apparatus. A memory 102 stores image data and binarization error. 103
Is an error diffusion unit (ED), which binarizes multivalued (1 pixel: 8 bits) image data by an error diffusion method. 104 is D
The MA controller controls transfer of image data to and from the memory 102. 105 is an I / O port,
Scanner / Printer 106 (or both depending on configuration)
And input and output image data. An I / F 107 transfers image data to another device connected to this device. Further, the CPU 101 accesses the ED 103, and manages the resulting output image data and a binarization error buffer.

FIG. 2 is a diagram showing the configuration of the error diffusion unit (ED). The part indicated by the dotted line in the figure is the part configured by hardware, and the input image buffer, output image buffer, and error buffer in the upper part are placed on the memory 102, and the memory 1
The CPU directly accesses and reads and writes 02 and registers. The error diffusion matrix is configured as shown in FIG. 2 and diffuses the binarization error of the pixel of interest (indicated by the symbol “*”) to the peripheral pixels by the coefficient distribution of K1 to K6.

Based on this principle, the operation of the hardware portion of the ED 103 will be described. First, the CPU adds the sum of the input pixel data and the error diffused from the previous line, and sets it in the register I-reg 201. Next, the adder 20
In 3, the output of the I-reg 201 and the value of the register A11-Reg 215 that stores the diffusion error of the previous pixel and the pixel before the previous pixel are added. Therefore, the output of this adder 203 (AD
3) is the sum of the input pixel data and the diffused error. Then, the comparator 205 binarizes the pixel of interest.

In this embodiment, since the input data is 8 bits, the comparison value will be described as "128". If the output (AD3) of the adder 203 is larger than the comparison value 128, the binarized output (OGE) is "1", and if it is smaller, it is "0".

Next, the binarized data is byte-backed (8 bits) in the shift register 207 so that the CPU 101 can process it easily. Here, if an 8-bit CPU is used, an 8-stage shift register may be used. The byte-packed data is stored in the enable buffer 209 for the CPU 101 to access.

Up to this point, the flow of input and output has been described. Next, the operation of the part for diffusing and adding the error will be described. FIG.
Among them, Err1 to Err6 are outputs of a portion that creates a diffusion error described later. Further, Err1 to Err6 represent the errors distributed by the diffusion matrix described above.

The register A12-Reg211 stores Err1 corresponding to the diffusion error of the pixel before the pixel. The output and Err2 corresponding to the diffusion error of the previous pixel are added by the adder 21.
3 and the result is added to the register A11-Reg21.
5 Here, Pix-In, which is a latch signal of each register, corresponds to a pixel clock, and is 1 for each pixel.
Each register is configured to be latched once. As described above, in this embodiment, the pixel clock is supplied to the register I-
It is also used as the Reg write signal, because the CPU does not need to output the pixel clock again, and the processing speed is increased. Register All-Reg 215
As described above, the output of is the sum of the diffusion errors of the previous pixel and the previous pixel.

Registers All-Reg 215, A12-
Registers A21-Reg to A in the same manner as Reg211
23 to Reg are for adding the diffusion error of the next line. That is, the diffusion error Err3 is stored in the register A23-Reg 217, and the adder 21 is delayed by one pixel.
At 9, the diffusion error Err4 is added. The added output is stored in the register A22-Reg221 and further delayed by one pixel. Perform such operation up to A21-Reg225,
Err6 is added by the adder 227 with a delay of one pixel.

The Out signal, which is the output of the adder 227 thus obtained, becomes an intermediate result of the error diffused to each pixel on the next line. Here, since Err6 is diffused two pixels before the target pixel on the next line, the output of Out is two pixels before the target pixel. The CPU reads the Out signal through the enable buffer 229 and accumulates it two pixels before the error buffer.

Next, the remaining part of the hardware of the ED 103 is a part for creating the diffusion errors Err1 to Err6. First, the adder 2 is operated by the binarized output OGE in the selector 233.
03 output AD3, or adder 231 outputs “-3
It is selected whether "255" is added. Specifically, when OGE is “0”, AD3 is, and when it is “1”, AD3
-255 is selected. Then, the output of the selector 233 is sent to the multiplier to obtain the diffusion error, and the register K
It is multiplied by the coefficients 1 to K6. For example, Err1 diffused into pixels one after another is the result of multiplying the output of the selector 233 by the coefficient of the register 237 by the multiplier 235. Similarly, Err2 to Err6 are obtained. This Err
1 to Err6 are sent to the adders and registers described above.

FIG. 3 is a diagram for explaining the processing flow of the CPU in this embodiment. Here, the initialization of the loop and the like are omitted, and the processing for one pixel will be described.

First, in step S1, image data is taken out from the input image buffer. Here, the pointer to the memory is R3. Next, in step S2, an intermediate error result is retrieved from the error buffer. Similarly, the pointer is R4. Then, in step S3, the two data are added, and in the subsequent step S4, the data is output to the I-reg 201 of the error diffusion unit (ED). As a result, the error diffusion process is executed, and the buffer Pix-Out 209, the buffer Err-Out 229, and the internal registers are updated. Next, in step S5, the intermediate result of the error two pixels before in the next line is input from the buffer Err-Out 229. In the subsequent step S6, the data is written to the address (R4-2) two pixels before in the error buffer. After this processing is performed for 8 pixels, the buffer Pix- is processed in step S7.
Output pixels are input from Out209. Then, in step S8, the data is written in the output image buffer, and the subsequent step S8
9 to S11 increment the pointer to each buffer.

As described above, in this embodiment, eight steps per pixel (that is, S7 and S out of S1 to S11) are performed.
Since 8 and S11 are once for every 8 pixels, they can be processed in 11-3 steps). Some CPUs automatically increment the address by reading from the memory. If such a CPU is used, the number of steps can be further reduced.

[Other Embodiments] Hereinafter, other embodiments will be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing the arrangement of an image processing apparatus according to another embodiment. In this embodiment,
An external DMA controller for controlling the address of the memory 102 is provided instead of the CPU 101. As a result, the bus will be monopolized, but it will be delayed to some extent.
It has the advantage that U can perform other processing. Especially for inkjet printers that do not require high-speed operation,
The processing efficiency of the CPU can be improved by opening the DMA interval.

As shown in FIG. 4, the main part of the other embodiment is almost the same as the above-described embodiment, and
A control unit 401 for address generation and bus control for MA is added. Further, the part for creating the diffusion coefficient is the same as in the above-described embodiment, and is omitted in FIG.

FIG. 5 is a diagram showing the internal structure of the control unit 401. As shown in the drawing, a counter 501 that indicates the number of pixels inside, a command unit 502 that repeats processing until the end, address generation units 503a to 503d that generate four addresses, and each address generation unit 503a.
Selector 504 for selecting an address from ~ 503d
And a comparator 5 for comparing the read address of the image data
05 and a bus control unit 506 that controls the bus and performs read / write with the memory 102.
Then, the command unit 502 controls the interrupt (INT) notified to the CPU 101, and the bus control unit 506.
Controls BUSREQ / BUSACK of DMA.

FIG. 6 is a timing chart showing bus control in another embodiment. In the configuration described above, the control unit 401 performs the following processing.

1. A bus request is issued to the CPU 101 to control the bus.

2. Generate a read address for image data and read the data.

3. Generate a memory address for error data and read the error data.

4. Execute the binarization process, generate the memory address of the error data, and store it in the error memory.

5. Generate an address for output data and store that data in memory (once every 8 pixels).

6. The bus is released and control is passed to the CPU 101.

7. The above 1 until the counter 501 becomes 0
Repeat steps 6 to 6 and when it reaches 0, INT the CPU 101.

In the above embodiments, the error diffusion processing was described as an example of the image processing, but the present invention is not limited to this and can be applied to other image processing. For example, it goes without saying that it can be applied to resolution conversion and encoding.

Even when the present invention is applied to a system composed of a plurality of devices (eg, host computer, interface device, reader, printer, etc.), a device composed of one device (eg, copier, facsimile) Device).

Further, the object of the present invention is to supply a storage medium having a program code of software for realizing the functions of the above-described embodiments to a system or apparatus, and to supply the computer (CPU or MP) of the system or apparatus.
It goes without saying that U) is also achieved by reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

A storage medium for supplying the program code is, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD.
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

Further, by executing the program code read by the computer, not only the functions of the above-described embodiment are realized, but also the OS (operating system) running on the computer based on the instruction of the program code. It is needless to say that this also includes a case where the above) performs a part or all of the actual processing and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion board inserted into the computer or the function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that a case where the CPU provided in the function expansion board or the function expansion unit performs a part or all of the actual processing and the processing realizes the functions of the above-described embodiments is also included.

[0044]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment.

FIG. 2 is a block diagram showing a configuration of an error diffusion unit that performs binarization processing.

FIG. 3 is a diagram showing a flow of processing of a CPU and its operation in the embodiment.

FIG. 4 is a block diagram showing a configuration of an image processing apparatus according to another embodiment.

FIG. 5 is a block diagram showing an internal configuration of a control unit in another embodiment.

FIG. 6 is a timing chart showing control of a bus in another embodiment.

[Explanation of symbols]

 101 CPU 102 Memory 103 Error Diffusion Unit (ED) 104 DMA Controller 105 I / O Port 106 Scanner / Printer 107 I / F 201 Register I-reg 203 Adder 205 Comparator 207 Shift Register 209 Enable Buffer 211 Register A12-Reg 213 adder 215 register A11-Reg 217 register A23-Reg 219 adder 221 register A22-Reg 223 adder 225 register A21-Reg 227 adder 229 enable buffer 231 adder 233 selector 235 multiplier 237 register K1 239 multiplier 241 register K2 243 multiplier 245 register K3 247 multiplier 249 register K4 251 multiplier 253 register K5 255 Adder 257 register K6

Claims (9)

[Claims] 1. A storage unit for storing image data, a reading unit for reading out the image data stored in the storage unit, and an image processing unit for subjecting the image data read by the reading unit to predetermined image processing. An image processing apparatus comprising: a writing unit that writes image data image-processed by the image processing unit into the storage unit; and a control unit that controls reading or writing into the storage unit. 2. The image processing apparatus according to claim 1, wherein the image processing means performs error diffusion processing on the image data. 3. The image processing apparatus according to claim 1, wherein the control unit is a CPU connected to the image processing unit by a bus. 4. The image processing apparatus according to claim 3, wherein the control unit controls a read or write address. 5. The DM is externally connected to the control means.
The image processing apparatus according to claim 1, wherein the image processing apparatus is controlled using A. 6. The image data stored in the storage means is read, the read image data is subjected to predetermined image processing, the image-processed image data is written in the storage means, and the image data is read out to the storage means. Control writing,
An image processing method comprising each step. 7. The image processing method according to claim 6, wherein in the image processing step, error diffusion processing is performed on the image data. 8. The image processing method according to claim 6, wherein the control step controls a read or write address by a CPU. 9. The control step is a DM connected to the outside.
The image processing method according to claim 6, wherein control is performed using A.