JPH09246924A - Multiplier circuit - Google Patents

Abstract

(57) Abstract: It is impossible to avoid the occurrence of jitter due to a PLL circuit in a multiplication circuit. An input clock signal 150 having a predetermined frequency.
Is a multiplication circuit that multiplies the signal 160 into a signal 160 having a frequency of n (n = 2, 3 ...), and a ring oscillator is configured by the ring oscillator control unit 103 and the variable delay circuit 104, and a pulse passes n times. Then, the oscillation is stopped, and the phase comparison circuit 106 and the delay time control unit 105 match the oscillation timings of the input clock signal 150 and the n-multiplied signal 160 to cause the ring oscillator to oscillate in a substantially constant cycle. A signal 160 having an n-fold frequency is output during one cycle of the clock signal 150.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for multiplying a periodically changing signal, and more particularly, to stably supply a high frequency clock signal required for information processing equipment such as a high speed computer. The present invention relates to a suitable multiplication circuit.

[0002]

2. Description of the Related Art As a multiplication circuit for stably supplying a high-frequency clock signal to an information processing device such as a computer, a PLL (Phase Lock) using a voltage controlled oscillator is used.
ed Loop, phase locked loop)
1994 Custom Integrated Circuits Conferenc
In the lecture number 25.1 in e), "A 1.5% jitter PLL c
lock generation systemfor a 500MHz RISC processo
In addition to the example presented under the title "r", the example presented at the same lecture number 25.2, or the presentation at the 1992 conference number 24.1, 42.2, 25.1 For example, in addition to the 1992 International Solid State Circuits Conference
d-State Circuits Conference) lecture number WP3.3
It is introduced in the example announced in.

However, since the PLL has a structure in which a voltage controlled oscillator is built in and an oscillation output of a desired phase is obtained while controlling the oscillation frequency thereof, a reference signal for adding the phase of the oscillation output from external means. It is essential to have a means for constantly controlling while comparing with the phase. For this reason, if erroneous control is received due to the influence of noise or the like, the phase of the oscillation output is rather deviated, which causes a phenomenon called jitter in which the phase of the oscillation output changes due to further control to correct this. . Depending on the cycle in which noise is generated, jitter that is several times the phase shift caused by this noise may occur.

[0004]

The problem to be solved by the present invention is that in the conventional technique relating to the multiplication circuit using the PLL,
The point is that it is not possible to avoid the occurrence of jitter due to the phase shift caused by noise. An object of the present invention is to solve these problems of the prior art and to provide a high-performance multiplier circuit that does not cause a large phase difference.

[0005]

In order to achieve the above object, the multiplier circuit according to the present invention (1) inputs a first repetitive signal (input clock signal 150) having a predetermined frequency, and inputs the input clock signal 150. Is a multiplication circuit that outputs a second repetitive signal (signal 160) having a frequency n times (n = 2, 3 ...) times, and a third repetitive signal (signal 153) having a frequency corresponding to this signal 160. ), Which is capable of adjusting the oscillation cycle and the rising edge (or the falling edge) of the input clock signal 150: If one circuit is determined, either the rising edge reference or the falling edge reference is determined. ) To start the oscillation circuit 2 (oscillation starting unit 3) and the oscillation of the signal 153 is continued for n cycles until the next rising (or falling) of the input clock signal 150. Means for stopping the After (oscillation stop portion 4) at least has an input clock signal 15
It is characterized in that the time of one cycle of 0 and the time of n cycles of the signal 153 are aligned and the signal 153 is output as the signal 160. In the multiplying circuit described in (1) above, the rising (or falling) timing of the signal 154 that activates the (n + 1) th cycle of the signal 153 and the rising (or falling) timing of the input clock signal 150 match. As described above, a unit (cycle adjusting unit 5) for expanding / contracting the cycle of the signal 153 is provided, and the timings of rising (or falling) of the input clock signal 150 and the rising edge (or falling edge) of the signal 154 are matched with each other.
53 is output as the signal 160. Also, (2) the first repetitive signal (input clock signal 15
0) is input and n (n = n) of this input clock signal 150 is input.
2, 3 ...), which is a multiplication circuit that outputs a second repetitive signal (signal 160) having a frequency that is a ring oscillator control unit 103, a variable delay circuit 104, a phase comparison circuit 106, and a delay time. A ring oscillator control unit 103 and a variable delay circuit 10 having at least a control unit 105.
4 forms a ring oscillator by connecting one output (signals 153, 154) to the other input, and the ring oscillator control unit 103 causes the input clock signal 150 (signal 152) to rise (or fall). Of the input clock signal 150 and starts oscillating at a frequency n times as high as the input clock signal 150.
The phase comparison circuit 106 is stopped after being continued for a period.
Is the rising (or falling) timing of the output 154 of the variable delay circuit 104 and the input clock signal 1
The rising (or falling) timing of 50 (signal 152) is compared, the comparison result 155 is output to the delay time control unit 105, and the delay time control unit 105
Based on the comparison result 155 of the phase comparison circuit 106, the n-th rising (or falling) timing of the output (signal 154) of the variable delay circuit 104 and the rising (or falling) of the input clock signal 150 (signal 152). The delay time of the variable delay circuit 104 is controlled so that the timings of 1 and 2 match. Then, the output (signal 154) of the variable delay circuit 104 after the control by the delay time control unit 105 is completed or the ring oscillator control unit 1
The output of No. 03 (signal 153) is output as a second repetitive signal (signal 160). Also,
(3) In the multiplication circuit described in (2) above, the ring oscillator control unit 103 selects either the output signal 154 of the variable delay circuit 104 or the first repetitive signal 152 to select the variable delay circuit 104. Output to the selector circuit (gate circuits 401 and 402) or the rising edge (or the falling edge) of the input clock signal 150 (signal 152).
Of the input clock signal 150 (signal 15) after the oscillation of the ring oscillator is started by selecting the output signal 154 of
It is characterized by having at least switching means (flip-flops 403 and 404, inverter circuits 405 to 407, NAND circuit 408) for selecting 2) and stopping the oscillation of the ring oscillator. (4) In the multiplication circuit according to (2) or (3), the delay time control unit 105 gradually increases the delay time of the variable delay circuit 104 from a predetermined minimum value. The variable delay circuit 104 having means (counter 707)
It is characterized in that the timing of the rising (or the falling) of the output of the variable delay circuit 104 and the timing of the rising (or the falling) of the input clock signal 150 (the signal 152) are matched while increasing the delay time.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, the generation and output of the second repetitive signal are started with either the rising or the falling of the first repetitive signal applied from the outside as a trigger, and a predetermined number of repetitions When output, the generation and output of the second repetitive signal are stopped until the next trigger (either the next rising or falling of the first repetitive signal) comes. As a result, every time the first repetitive signal rises or falls (first
The second repetitive signal is output a predetermined number of times for each repetitive signal of 1).

Such a second repetitive signal starts oscillation with a first repetitive signal externally added as a reference signal as a trigger in a ring oscillator composed of a selector and a variable delay circuit, for example. When a pulse passes through the oscillator a predetermined number of times, it is obtained by switching the selector to block the passage of the pulse. Then, with the input of the next first repeated signal as a trigger, the selector is switched again to pass the pulse. With such a configuration, the pulse passes through the ring oscillator a predetermined number of times for each cycle of the reference signal. Therefore, if the delay time of the variable delay circuit is adjusted so that the oscillation frequency of the ring oscillator is a predetermined multiple of the frequency of the reference signal, continuous oscillation with a frequency of a predetermined multiple of the reference signal can be obtained. Since this oscillation is triggered for each cycle of the reference signal, the delay time of the variable delay circuit does not have to be controlled after the initial adjustment, such as immediately after turning on the power of the apparatus. Further, even when the control of the variable delay circuit is always performed, abrupt control in a short time is unnecessary. As a result, a large jitter, which is a problem in the multiplication circuit using the conventional PLL circuit, does not occur.

Embodiments according to the present invention will be described below in more detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the configuration of the multiplication circuit of the present invention according to the present invention. In FIG. 1, 1 is a multiplication circuit according to the present invention, 2 is an oscillation circuit that generates a signal 153 as a third repetitive signal having a frequency n times as high as the input clock signal 150 as the first repetitive signal from the outside, 3 is the input clock signal 1
An oscillation starting circuit 4 that starts the oscillation circuit 2 triggered by either the rising or the falling edge of 50 is a repeating signal 1 for n cycles of the input clock signal 150 from the oscillation circuit 2.
When 53 is oscillated, the oscillation stop circuit 5 that stops the oscillation operation of the oscillation circuit 2 until either the next rise or fall of the input clock signal 150, the input clock signal 150 that triggers the activation of the oscillation circuit 2. Is a cycle adjusting circuit that adjusts the cycle of the repetitive signal 153 so that one cycle and the cycle of the repetitive signal 153 generated by the oscillation circuit 2 for n times match.

With such a configuration, the multiplication circuit 1 has the oscillation circuit 2 whose period is adjusted by the period adjustment circuit 5.
The repetitive signal 153 from 1 is output as the signal 160 as the second repetitive signal. Hereinafter, the configuration of the multiplication circuit according to the present invention will be described in more detail with reference to FIG.

FIG. 2 is a block diagram showing a second embodiment of the configuration of the multiplication circuit of the present invention according to the present invention. In FIG. 2, 101 is a shaper unit, 102 is a hazard prevention unit,
Reference numeral 103 is a ring oscillator control unit, 104 is a variable delay circuit, 105 is a delay time control unit, and 106 is a phase comparison circuit. Further, reference numeral 150 is an input clock signal, 160 is an output signal obtained by multiplying the input clock signal 150, 170 is a reset signal for initializing the delay time control unit 105, and 151 to 156 are signals between the respective constituent elements. There is.

The operation of the multiplication circuit having such a configuration will be described below. The shaper unit 101 is a unit that changes the clock signal 150 input at a constant cycle into a pulse signal 151 having the same cycle and a short time width. The multiplication circuit of this example has several flip-flop circuits, but a normal flip-flop circuit may cause a so-called hazard phenomenon in which the output becomes uncertain when a reset signal and a clock signal are simultaneously input. is there.
The hazard prevention unit 102 is for eliminating this,
The pulse signal 151 is output as the pulse signal 152 after a sufficient time has elapsed since the reset signal 170 was released. Also, reset signal 1
Signal 70 before and immediately after 70 is released.
2 is fixed at low level.

The ring oscillator control section 103 and the variable delay circuit 104 constitute a ring oscillator. This ring oscillator starts oscillation when a pulse appears in the pulse signal 152, and when the oscillation output vibrates a predetermined number of times,
Oscillation is stopped by the action of the ring oscillator control unit 103 described later. Then, when the next pulse appears in the pulse signal 152, the same operation is repeated again. The phase comparison circuit 106 compares the early / late relationship between the timing at which the output 154 of the variable delay circuit 104 changes immediately before the ring oscillator stops oscillating and the timing at which the next pulse signal 152 appears, and the result is compared. Delay time control unit 1
Output to 05.

The delay time control unit 105 includes a phase comparison circuit 1
The delay time of the variable delay circuit 104 is adjusted so that the timings of the signal 152 and the signal 154 coincide with each other, based on the signal 155 indicating the comparison result sent from 06. When this timing coincides, the timing at which the oscillation of the ring oscillator stops and the timing at which the next oscillation starts coincides with each other, so that the ring oscillator continuously oscillates at a constant cycle. Then, while the pulse signal 152 appears once,
Since the oscillation output of the ring oscillator oscillates the predetermined number of times, by taking out this oscillation output as the output signal 160, a multiplied output of a predetermined multiplication rate can be obtained. still,
In order to prevent the oscillation output of the reset signal 170 from oscillating at a multiplication ratio other than a predetermined value, first the delay time control unit 105
Is a signal that resets the delay time and minimizes the delay time of the variable delay circuit 104.

Next, the details of each constituent element of the multiplier circuit in FIG. 2 will be described with reference to FIGS. FIG. 3 is a circuit diagram showing a specific configuration example of the shaper section in FIG. In FIG. 3, 201 is a gate circuit group for delaying and inverting the input clock signal 150, and 202 is a NAND circuit that takes the logic of the signal output from the gate circuit group 201 and the input clock signal 150. The shaper unit is configured to output a pulse having the same width as the time until it passes through the gate circuit group 201 as the signal 151 each time a rising edge appears in the input clock signal 150. Therefore, the pulse signal 151 having the same period as the input clock signal 150 having a constant period and a short width is obtained.

FIG. 4 is a circuit diagram showing a concrete configuration example of the hazard prevention unit in FIG. In FIG. 4, 3
Reference numerals 01 and 302 denote edge-triggered flip-flop circuits, 303 denotes a NOR circuit for not passing the pulse signal 151 when a hazard may occur, and 304 denotes a buffer circuit. Further, reference numeral 152 indicates an output signal in which a hazard is prevented. The signal 151 output from the shaper unit 101 in FIG. 3 also functions as a clock signal for the edge trigger type flip-flop circuits 301 and 302. Initially, when the reset signal 170 is active, the flip-flop circuit 301 outputs a low level, the flip-flop circuit 302 outputs a high level, and the signal 152 remains fixed at a low level.

When the reset state by the reset signal 170 is released, the outputs of the flip-flop circuits 301 and 302 are sequentially inverted every time the pulse signal 151 rises, and then the pulse signal 151 passes through the NOR circuit 303 to be a signal. It is output as 152. In this case, a hazard may occur in the flip-flop circuit 301, but the flip-flop circuit 302 uses the same pulse signal 151 as the flip-flop circuit 301 and shifts the output signal of the flip-flop circuit 301 by one cycle. Hazard does not occur because it is configured. As a result, the NOR circuit 303 outputs the pulse signal 15 after at least one cycle has elapsed after the reset was released.
1 is output as the signal 152.

FIG. 5 is a circuit diagram showing a concrete configuration example of the ring oscillator control section in FIG. In FIG. 5, reference numerals 401 and 402 denote gate circuits with enable terminals that perform switching for selecting a signal to be connected to the signal 153 from the signals 152 and 154, and 403 and 404 control the gate circuits 401 and 402. Edge-triggered flip-flop circuit, 405-407
Is an inverter circuit acting as a buffer, and 408 is N
An AND circuit is shown. The signal 153 is delayed and inverted by the variable delay circuit 104 at the next stage in FIG. 2 and added to the gate circuit 401 as the signal 154. Therefore, when the gate circuit 401 side is selected, the gate circuit 401 and the variable delay circuit 104 form a ring oscillator. The oscillation output is taken out as the output signal 160.

In FIG. 5, since the ring oscillator oscillates while the gate circuit 401 side is selected, the clock terminals of the flip-flop circuits 403 and 404 are supplied with the pulses of the oscillation period from the inverter circuits 405 to 405.
Added via 07. In addition, since the pulse signal 152 is at a low level for a much longer time than at a high level, the output signal 4 of the NAND circuit 408 is normally used.
53 is a high level, and the flip-flop circuit 40
The reset terminals of 3,404 are inactive. For this reason,
Due to the oscillation of the ring oscillator, the signals 450 and 451 sequentially go to high level and the signal 452 goes to low level, and the gate circuit 402 is finally selected. Then, the signal 153 is fixed at the same low level as the signal 152, and the oscillation of the ring oscillator is stopped.

When the pulse signal 152 becomes high level when the gate circuit 402 is selected, the signal 153 also becomes high level, so that the signal 453 becomes low level and the flip-flop circuits 403 and 404 are reset. Then, the gate circuits 401 and 402 are switched, the ring oscillator is configured by the gate circuit 401 and the variable delay circuit 104, and the signal 153 starts oscillating. Signal 15
Reference numeral 3 serves as clock signals 455 and 454 of the flip-flop circuits 403 and 404, and a group of inverter circuits 405 to 407 constitutes a delay circuit in its transmission path. Therefore, there is a difference in the time required for the clock signal to reach the flip-flop circuits 403 and 404.

That is, the flip-flop circuit 404 receives the clock signal earlier than the flip-flop circuit 403. Therefore, at the first rise of the signal 454, the output signal 450 of the flip-flop circuit 403 remains at the initial low level, and the flip-flop circuit 404 maintains the previous state. A little after that, the output signal 450 of the flip-flop circuit 403 rises from the low level to the high level, so that the signal 450 is at the high level and the signal 451 at this point.
Becomes low level.

At the next rising edge of the signal 454, the output signal 450 of the flip-flop circuit 403 is at high level, so the flip-flop circuit 40
The output signal 451 of 4 outputs a high level, and the output signal 452 outputs a low level. Therefore, the gate circuits 401 and 4
02 is switched and the side of the gate circuit 402 is selected, so that the ring oscillator is released and the signal 15
Stop the oscillation of 3. Then, when the next pulse signal 152 appears, the operation described above is repeated again. The oscillation cycle of the ring oscillator is from signal 153 to signal 15
4 is changed by controlling the time for transmission to 4 in the variable delay circuit 104 of FIG.

FIG. 6 is a timing chart showing an example of a time change of each signal of the ring oscillator control section in FIG. In FIG. 6, the ring oscillator control unit 10 of FIG.
The concept of the time change of each signal in 3 is shown for one period from the input of the first pulse of the signal 152 to the input of the next pulse. This figure shows, from the top, the pulse signal 152 from the hazard prevention unit 102 in FIG. 2, the signal 153 output from the ring oscillator control unit 103 in FIGS. 2 and 5 to the variable delay circuit 104 in FIG. 2, and the variable delay circuit in FIG. 10
4 to the signal 154 output to the ring oscillator control unit 103 of FIGS. 2 and 5, and the flip-flop circuit 40 of FIG.
3, 404 reset signal 453 and output signal 45
It is a graph which shows the voltage waveform of 0,451, and represents progress of time from left to right.

As mentioned above, first the pulse signal 152
5 is selected, the signal 153 becomes low level and the signal 154 becomes high level. Here, when the pulse signal 152 becomes high level, the signal 153 rises after passing through the gate circuit 402 in FIG. Pulse signal 152 and signal 15
When both 3 become high level, the reset signal 453 falls and the flip-flop circuits 403 and 404 of FIG.
Reset. The flip-flop circuit 403 of FIG.
When 404 is reset, each output signal 45
0 and 451 both fall. Although the gate circuits 401 and 402 in FIG. 5 are switched by the fall of the signal 451, the pulse signal 152 and the signal 154 are both at a high level at this point, so the signal 153 does not change.

The signal 154 is a signal obtained by delaying and inverting the signal 153 by the variable delay circuit 104 of FIG.
It will fall after that delay time. This is transmitted to the signal 153 through the gate circuit 401 of FIG. 5, and when the signal 153 falls, the flip-flop circuits 404 and 4 of FIG.
The signal applied to the 03 clock terminal rises. Then, as described above, the output signal 451 of the flip-flop circuit 404 in FIG. 5 remains low level, and only the output signal 450 of the flip-flop circuit 403 becomes high level. After that, the signals 153 and 154 further change through the variable delay circuit 104 of FIG. 2 and the gate circuit 401 of FIG. 5, and are changed to the clock terminal of the flip-flop circuit 404 of FIG. 5 at the second fall of the signal 153. The added signal rises. Since the signal 450 is at high level at that time, the output signal of the signal 451 also becomes high level, and the gate circuit 402 side in FIG. 5 is selected. Signal 1
Since 52 and 154 are both at the low level, the signal 153
Does not change.

The pulse width of the pulse signal 152 set by the number of stages of the inverter circuit 201 in the shaper section 101 shown in FIGS. 2 and 3 is activated at the rising edge of the pulse signal 152, and the flip-flop circuit 404 of FIG. 5 is reset and after the gate circuit 402 of FIG. 5 is switched to the gate circuit 401, the pulse signal 152 falls and the flip-flop circuits 403 and 404 of FIG. The reset signal 453 is set to be released. Also,
The minimum delay time of the variable delay circuit 104 in FIG.
The second rising edge of 4 is set later than the rising edge of the signal 451 and earlier than the rising edge of the pulse signal 152 of the next cycle.

FIG. 7 is a circuit diagram showing a concrete configuration example of the phase comparison circuit in FIG. In FIG. 7, 60
Reference numerals 1 and 602 are NAND circuits forming a set-reset type flip-flop circuit, 608 is an edge trigger type flip-flop circuit, 603 to 606 are inverter circuits acting as buffers, 607 is a NOR circuit,
Reference numeral 609 denotes an inverter circuit for delaying the signal, 61
Reference numerals 0 and 611 represent buffers.

Further, reference numeral 152 is a pulse signal output from the hazard prevention unit 102 shown in FIGS. 2 and 4, 154 is an output signal of the variable delay circuit 104 in FIG. 2, and the circuit of this example uses these two signals 152. , 154 are compared in phase. Further, 653 is a signal applied to the clock terminal of the flip-flop circuit 608, 620 is a signal representing the phase comparison result, and 630 is a signal obtained by inverting the signal 152, which is a clock signal for operating the delay time control circuit 105. The inverter circuit 603 and the buffer 611
Is a dummy circuit provided for equalizing the loads of the NAND circuits 601 and 602.

In the circuit of FIG. 7, the NAND circuit 60
1, 602 operate as a set-reset type flip-flop circuit, and output signal 1 of the variable delay circuit 104 in FIG.
The rising edge of 54 is compared with the rising edge of the output signal 152 of the hazard prevention circuit 102 shown in FIGS. 2 and 4, and the comparison result is output as a signal 652. Then, when the signals 152 and 154 both become high level, the signal 653 also becomes high level a little later, and the comparison result appearing in the signal 652 is fetched by the flip-flop circuit 608 and output as the signal 620. In the circuit of FIG. 7, when the signal 154 is earlier than the signal 152, it is low level, and when it is late, it is high level.
It is configured to output as 0.

FIG. 8 is a circuit diagram showing a first configuration example of the delay time control section in FIG. In FIG. 8, 70
1 to 704 are edge trigger type flip-flop circuits, 705 is a NAND circuit, 707 is a counter circuit, and 7
Reference numeral 06 denotes a buffer for driving many flip-flop circuits in the counter circuit 707. Also, 1
56 is a signal for controlling the delay time of the variable delay circuit 104,
Signals 620 and 630 are output signals of the phase comparison circuit of FIG. 7, 620 is a signal representing the result of the phase comparison, 63
Reference numeral 0 denotes a signal having the same cycle as the input clock signal 150 in FIG. 2 and indicates a signal which acts as a clock signal for each of the flip-flop circuits 701 to 704.

The flip-flop circuits 701 and 703 operate as frequency dividing circuits, and output signals 754 and 755 obtained by dividing the signal 630 by 2 and 4, respectively. The signal 754 acts as a clock signal for the flip-flop circuit 702, takes in the phase comparison result input as the signal 620, and outputs it as a signal 753. In such a configuration, after the reset signal 170 is released, the signal 750 is at the low level while the signal 620 as the phase comparison result is at the low level. During this time, signal 6
A signal 755 obtained by dividing 30 by 4 acts as a clock signal on the counter circuit 707 to increase the count value. Then, according to the count value, the variable delay circuit 104 of FIG.
Delay time is controlled. As will be described later, the variable delay circuit 104 in FIG. 2 is configured so that the delay time becomes longer as the count value increases.

Since the counter circuit 707 is reset first, the delay time of the variable delay circuit 104 in FIG. 2 starts from the minimum state and gradually increases. Then, when the early / late relationship of the phases of the signals 152 and 154 is reversed and the signal 620 becomes high level, the signal 750 becomes high level and the counter circuit 707 stops counting. Further, when the signal 750 goes high, the flip-flop circuit 704 holds that state, and thereafter holds the count value of the counter circuit 707. Signal 6
The reason why 30 is divided by 4 and added to the counter circuit 707 is that the result of controlling the delay time is reflected in the phase comparison result 620 and the next control is not performed until it appears in the signal 750. is there.

FIG. 9 is a circuit diagram showing a concrete configuration example of the variable delay circuit in FIG. In FIG. 9, 80
Reference numerals 1 to 804 are NOR circuits, 805 is a 4-input NOR circuit, 806 to 812 are selector circuits for selecting signal transmission paths, 813 to 815 and 818 are inverter circuit groups for making a delay time difference, and 816 and 817 are clocks. Inverter circuit groups for matching the polarities of signals and for making a delay time difference, and 819 and 820 are inverter circuit groups acting as loads. Also, 153 and 1
Reference numeral 54 denotes the ring oscillator control unit 103 in FIGS.
Connect with the input / output signal of.

Each of the NOR circuits 801 to 804 has two
Input 5 input, 6 input, 6 input, but input signal 15 from the ring oscillator control unit 103 in FIGS.
3 and the terminal 850 other than the terminal for receiving the control signal 156 from the delay time control unit 105 in FIG. 8 are fixed at a low level. Further, among the terminals 851 to 861, the terminals 851 to 854 are connected to the delay time control unit 1 of FIG.
A signal obtained by decoding the lower 2 bits of the control signal 156 from the terminal 05, a signal obtained by taking the next lower 1 bit at the terminal 858, and a signal obtained by taking the logic from the next lower 2 bits at the terminals 859 to 861, the terminal 855. Up to 857 are added higher-order bits and signals obtained by the logic thereof.

In the circuit of FIG. 9, when the delay time is set to the minimum, the signal 153 outputs the NOR circuits 801 and 80.
5, via selector circuits 806, 809, 810,
It is output as the signal 154. Then, the control signal 156
As the value of increases, the delay time is finely adjusted by selecting the NOR circuits 801 to 804, and the delay time is greatly adjusted by switching each selector circuit. A part of the construction technique of such a variable delay circuit (104) is disclosed in, for example, Japanese Patent Laid-Open No. 6-9778.
No. 8 discloses this.

FIG. 10 is a timing chart showing an example of the time change of each signal of the ring oscillator control section in FIG. 5 based on the control result of the delay time control section in FIG. 8 and the delay result of the variable delay circuit in FIG. . This figure 1
0 indicates a delay result of the signal 154 shown in FIG. 6 by the variable delay circuit (104) in FIG. 9. As shown by a solid line in FIG. 10, the delay time control unit (105) in FIG. The signal 154 in the ring oscillator control unit (103) of FIG. 5 based on the delay result of the variable delay circuit (104) of FIG.
Rises in synchronization with the rise of (signal 1 in FIG.
54 is indicated by a dotted line). As a result, the signal 154 and the signal 153 in the ring oscillator are signals that continuously repeat at a constant cycle. The period of these signals is 1 / n of the period of the reference signal 152,
Therefore, a signal having a frequency n times that of the reference signal 152 is obtained. The multiplication circuit of this example outputs this signal 153.

Although the embodiments of the frequency multiplying circuit of the present invention have been described above, other various configurations are conceivable and will be described below. FIG. 11 is a circuit diagram showing a configuration example of a frequency dividing circuit for dividing the output signal of the frequency multiplying circuit in FIGS. 1 and 2. This frequency dividing circuit corrects the duty of the clock signal by dividing the frequency of the signal 160 output from the frequency multiplying circuit in FIGS.
901, an edge-triggered flip-flop circuit for dividing the signal 160 in FIGS.
Shows a NOR circuit for adjusting the timing of starting the frequency division. Reference numeral 180 denotes a signal obtained by dividing the signal 160 and correcting the duty of the input clock signal 150.

The signal 160 is divided by the flip-flop circuit 901 and output as the signal 180.
The signal 160 is the input clock signal 15 in FIGS.
Since the signal has a substantially constant cycle multiplied by the ring oscillator regardless of the duty of 0, the duty of the signal 180 is almost 50%. Further, since the cycle of the signal 180 divides the multiplied signal 160,
Returning to the cycle of the input clock signal 150 in FIGS. That is, the input clock signal 15 in FIGS.
A signal 180 in which 0 is corrected to have a duty of 50% is obtained. The NOR circuit 902 is provided in order to match the timing of starting frequency division with the signal 152.

FIG. 12 is a circuit diagram showing a configuration example of a control circuit used for controlling the cycle of the output signal of the multiplication circuit in FIG. The circuit of this example controls the cycle of the signal 160 multiplied by the multiplier circuit in FIG. 2 every two cycles by inputting a control signal whose level is fixed from the outside, and the ring oscillator control unit in FIG. It is inserted between 103 and the variable delay circuit 104. Further, by combining the circuit of this example with the frequency dividing circuit in FIG. 11,
Signal 180 with duty consciously shifted from 50%
Can be obtained.

In FIG. 12, 1001 is AND and N
Composite gate circuit with OR function, 1002 and 1
Reference numeral 003 indicates a gate circuit with an enable terminal for selecting a signal transmission path, and reference numeral 1004 indicates a gate circuit group for creating a delay time difference. Further, 1051 and 1052 are control signals fixed to a high level or a low level respectively, 1057 and 1058 are signals for selecting the gate circuits 1002 and 1003, and 1053 and 1054.
Is a flip-flop circuit 70 in the delay time control unit 105.
4 shows an output signal of No. 4 and an inverted signal thereof.
The signal 1054 side shows the signal 752 in FIG.

With this configuration, the control circuit outputs the signal from the ring oscillator control unit 103 shown in FIG.
055 and outputs the signal 1056 to the variable delay circuit 104 of FIG.
03 and the variable delay circuit 104 are inserted and connected. In the following description, the operation until the phase of the signal 152 and the signal 154 in FIG. 2 match is defined as the adjustment state, and the operation after the phase of the signal 152 and the signal 154 match as the working state.

The signals 1051 and 1052 are fixed to the high level or the low level, but the output signals 1053 and 1054 of the flip-flop circuit 704 of FIG.
When the adjustment state ends and the operation state is entered, the signal 1053 is inverted from the low level to the high level, and the signal 1054 is inverted from the high level to the low level. Accordingly, the signal 105
7 and signal 1058 are controlled and gate circuit 1002
Since the gate circuit 1003 is switched from the ring oscillator control unit 103 to the variable delay circuit 104 in FIG.
The signal transmission time to is controlled. As a result, in the adjustment state and the operating state, the signals 153 to 15 in FIG.
Since the signal propagation time up to 4 increases or decreases, the oscillation cycle of the ring oscillator changes, and the cycle of the output signal 160 of the multiplier circuit in FIG. 2 is controlled every two cycles.

Signal 1051 is set to high level and signal 10
When 52 is set to the low level, the control signal 1058 falls from the high level to the low level when the adjustment state is finished and the operation state is entered, and the gate circuits 1002 to 1
Since it is switched to 003, the cycle of the output signal 160 of the multiplication circuit in FIG. 2 becomes long in the first cycle and short in the second cycle. In addition, the signal 1051 is at a low level and the signal 1052 is
Is set to a high level, the control signal 1058 rises from a low level to a high level when the adjustment state ends and the operating state is entered, and the gate circuits 1003 to 100
Since the frequency is switched to 2, the cycle of the output signal 160 of the multiplication circuit in FIG. 2 becomes short in the first cycle and long in the second cycle. Further, when both the signal 1051 and the signal 1052 are set to the low level, the control signal 1058 does not change even when the adjustment state is ended and the operation state is entered, so that the gate circuit is not switched and the output signal of the multiplication circuit in FIG. The period of 160 does not change.

That is, the signal 1051 and the signal 105
Depending on the setting of the two signals, the first cycle of the output signal 160 of the multiplier circuit in FIG. 2 is controlled to be longer, shorter or unchanged than the second cycle. When this control circuit is combined with the frequency dividing circuit shown in FIG. 11, the output signal 160 acting as the clock signal of the flip-flop circuit 901 in FIG. 11 fluctuates as described above, so the duty 50% is intentionally increased. Or
The reduced signal can be obtained as the signal 180 in FIG.

FIG. 13 is a circuit diagram showing an example of the configuration of the ring oscillator control unit of the multiplication circuit in which the multiplication ratio is 4. In FIG. 13, reference numerals 1101 and 1102 denote edge-triggered flip-flop circuits.
Is an output signal of the flip-flop circuit 1101, 1151
Indicates the output signal of the flip-flop circuit 1102.
The other circuits and signals are the same as those shown in FIG. Further, each component of the multiplication circuit is the same as that of the embodiment described in FIGS. 2 to 10, except for the ring oscillator control unit of this example.

The specific operating principle of the ring oscillator control section in FIG. 13 is the same as that of the ring oscillator control section shown in FIG. 5, but in the ring oscillator control section of this example, the number of stages of the flip-flop circuit is increased. As a result, the number of vibrations of the signal 153 increases. Pulse signal 15
Until the second pulse appears, the gate circuits 401, 40
In No. 2, the gate circuit 402 side is selected.
Here, since the signal 153 also rises when the signal 152 rises, the signal 453 becomes low level, each flip-flop circuit is reset, and the gate circuit 401 side is selected.

The signal 153 is an inverter circuit 405-40.
It acts as a clock signal of each flip-flop circuit via 7. At the first fall of the signal 153, the signal 454 rises first, but the flip-flop circuit 4
03, 1101, 1102 output signals 450, 115
Since 0 and 1151 remain at the initial low level, the flip-flop circuit 404 holds the previous state as it is. A little after that, the output signal 450 of the flip-flop circuit 403 rises. The operation up to this point is the same as in the case of the ring oscillator control unit in FIG.

However, in the case of the ring oscillator control section in FIG. 13, since there are four stages of flip-flop circuits, at the second fall of the signal 153, the signal 1
150 goes high and signals 1151 and 4
51 holds the previous state as it is, the signal 1151 becomes high level even at the third fall of the signal 153, and the signal 451 holds the previous state as it is. Then, at the fourth fall of the signal 153, the signal 451 goes high and the signal 452 goes low, switching the gate circuit and stopping the oscillation of the signal 153. These operations are a series of operations from the appearance of a pulse in the signal 152 to the appearance of the next pulse. Therefore, the frequency of the signal 153 is four times within one cycle of the input clock signal 150 in FIG. 2, and thus the signal 160 obtained by multiplying the input clock signal 150 by four is obtained.

FIG. 14 is a circuit diagram showing a second configuration example of the delay time control section in FIG. The delay time control unit of this example is configured to continue the control of the delay time even after the operating state is reached, and in FIG. 14, 1201 indicates an up / down counter circuit. The up / down counter circuit 1201 increases the count value when the signal 753 is at the high level, and decreases the count value when the signal 753 is at the low level. Other circuits and signals are the same as those of the delay time control unit shown in FIG. Also,
Each component other than the delay time control unit of the present example which constitutes the multiplication circuit is the same as the example described in FIGS.

The delay time control unit of this example is a circuit in which the counter circuit 707 of FIG. 8 is replaced with an up / down counter circuit 1201 and a portion for storing whether or not the phase is reversed is removed, and its operation will be described below. explain. This circuit operates on signal 152 during the adjustment state as in FIG.
The count value of the up / down counter circuit 1201 is increased until the phases of the signal 154 and the signal 154 match. Then, when entering the operating state from the adjustment state, this circuit increases or decreases the count value according to the phase comparison result in order to reflect the phase comparison result in the up / down counter circuit 1201 regardless of the adjustment state and the operation state. Therefore, even if the oscillation cycle of the ring oscillator changes due to, for example, a change in temperature after entering the operating state, the up / down counter circuit 12
Since the operation of 01 is performed, the delay time is controlled and the signal 160 is corrected to a constant cycle.

In this circuit example, when the upper bits of the up / down counter circuit 1201 are switched, while the signal is passing through the variable delay circuit 104 in FIG.
There is a possibility that the selector circuits 806 to 812 in FIG. 9 will be switched, and in that case, pulsed noise may occur and malfunction may occur. A technique for preventing such a malfunction is shown in FIG. 15 below.

FIG. 15 is a circuit diagram showing a third configuration example of the delay time control section in FIG. In FIG. 15,
1301 is an up / down counter circuit, 1302 is a counter circuit, 1303 is a NOR circuit, and 1304 is an inverter circuit. Further, 1350 is a control signal input to each selector circuit 806 to 812 in the variable delay circuit 104,
1351 decodes the NAND circuits 801 to 804
The control signal to be input to is shown. The other circuits and signals are the same as those in the delay time control section shown in FIG. Further, each component of the multiplication circuit other than the delay time control section composed of this circuit is the same as that of the embodiment described in FIGS. In addition, this circuit is similar to the circuit shown in FIG.
It is also a circuit that combines the circuits shown in.

The operation of the circuit thus constructed will be described below. First, in the reset state, the counter circuit 1302 is set to a count value that minimizes the delay time, and the up / down counter circuit 1301 is set to a count value corresponding to about half the maximum count value. When the reset state is released and the adjustment state is set, the signal 752 is initially high level and constant, so that the NOR circuit 1303 outputs only a low level signal. As a result, the clock signal is not supplied to the up / down counter circuit 1301 and the count value does not change. On the other hand, the counter circuit 1302 performs the same operation as in FIG. 8 in the adjusted state.

Next, when the adjustment state is changed to the operation state, the signal 752 becomes low level, and the counter circuit 1302 stops while holding the count value at that time. However, regarding the up / down counter circuit 1301, the signal 755 is output from the inverter circuit 1304 and the NOR circuit 130.
3 is supplied, the count value changes based on the signal 753. That is, in the operating state, the up / down counter circuit 1301 controls.

As described above, if the selector circuit in the variable delay circuit 104 in FIG. 8 is switched during operation, the waveform may be disturbed. This occurs when the selector circuit is switched between the time when the signal in the variable delay circuit 104 in FIG. 8 passes through the path on the short delay time side and the path on the long side. The disturbance of the waveform is not a problem when it occurs in the adjustment state, but it may cause a malfunction when it occurs in the operation state.
In order to prevent this, the delay time control unit shown in FIG. 15 switches the counter circuit to be operated in the adjustment state and the operating state.

In the operating state, the up / down counter circuit 1301 is used, and the variable delay circuit 1 in FIG. 9 is used.
Only the NAND circuits 801 to 804 in 04 are switched, but since the variable width of this part is small, it is possible to switch after the signal passes. As a result, the disturbance of the waveform is unlikely to occur and the malfunction does not occur. That is, the NAND circuits 801 to 8 in the variable delay circuit 104 in FIG.
In No. 04, the signal first passes through the variable delay circuit 104, passes through each circuit and the ring oscillator within the variable delay circuit 104 of FIG. 9, and the NAND circuits 801 to 8 again.
There is sufficient time before it is input to 04. Therefore, the control signal 1351 can be switched during that time. That is, in the adjustment state, the control signal 1 having a large variable width
Adjustment is performed by 350, but in the operating state, the control signal 13
By performing only the fine adjustment by 51, the disturbance of the waveform can be prevented and the malfunction can be prevented.

As described above with reference to FIGS. 1 to 15, in the frequency multiplying circuit of the present embodiment, generation of the multiplied signal is started with the rising of the input clock signal 150 applied from the outside as a trigger, The next trigger (the rising edge of the input clock signal 150) is generated by the number of times
By stopping the generation of the multiplied signal until the time comes, a repetitive signal that repeats a predetermined number of times for each cycle of the input clock signal 150 is output.

That is, the ring oscillator control section 103
A ring oscillator including the variable delay circuit 104 and the variable delay circuit 104 is provided, and an oscillation for generating a multiplied signal is started by using an input clock signal 150 externally added as a reference signal as a trigger, and a pulse is generated a predetermined number of times in the ring oscillator. When it passes, the selector is switched to block passage of the pulse. Then, using the next input clock signal 150 as a trigger, the selector is switched again to pass the pulse. This allows the input clock signal 150
It is possible to obtain a repetitive signal that is repeated a predetermined number of times for each cycle. Then, the delay time by the variable delay circuit 104 is controlled by the delay time control unit 105 or the like, so that a multiplied signal having a substantially constant cycle can be generated.

As described above, the multiplication circuit can be constructed without using the conventional PLL circuit, and a large jitter due to the PLL circuit does not occur. The present invention is shown in FIG.
The present invention is not limited to the embodiment described with reference to FIG. 15, and various modifications can be made without departing from the spirit of the invention. For example, in FIG. 13, a circuit configuration for obtaining a signal multiplied by 4 is shown. However, in order to obtain a signal with a predetermined multiplication rate, the number of stages of the flip-flop circuits may be increased by the number corresponding to the multiplication rate. In addition, in the present embodiment, FIG.
As shown in, although the rising edge of the input clock signal is mainly used as the timing for starting and stopping the oscillation circuit, the falling edge may be used.

[0059]

According to the present invention, in the multiplication circuit, P
It is possible to perform multiplication without generating a large phase difference that occurs in the LL circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the configuration of a multiplication circuit according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the configuration of the multiplication circuit according to the present invention.

FIG. 3 is a circuit diagram showing a specific configuration example of a shaper section in FIG.

FIG. 4 is a circuit diagram showing a specific configuration example of a hazard prevention unit in FIG.

5 is a circuit diagram showing a specific configuration example of a ring oscillator control section in FIG.

6 is a timing chart showing an example of a time change of each signal of the ring oscillator control unit in FIG.

7 is a circuit diagram showing a specific configuration example of the phase comparison circuit in FIG.

FIG. 8 is a circuit diagram showing a first configuration example of the delay time control section in FIG.

9 is a circuit diagram showing a specific configuration example of the variable delay circuit in FIG.

10 is a diagram showing a delay result of the variable delay circuit in FIG. 9 based on a control result by the delay time control unit in FIG. 8;
5 is a timing chart showing an example of a time change of each signal of the ring oscillator control unit in FIG.

11 is a circuit diagram showing a configuration example of a frequency dividing circuit for dividing the output signal of the frequency multiplying circuit in FIGS. 1 and 2. FIG.

FIG. 12 is a circuit diagram showing a configuration example of a control circuit used for controlling the cycle of the output signal of the multiplication circuit in FIG.

FIG. 13 is a circuit diagram showing a configuration example of a ring oscillator control unit of a multiplication circuit in which the multiplication rate is 4 times.

14 is a circuit diagram showing a second configuration example of the delay time control section in FIG.

15 is a circuit diagram showing a third configuration example of the delay time control section in FIG.

[Explanation of symbols]

1: multiplication circuit, 2: oscillation circuit, 3: oscillation start circuit, 4:
Oscillation stop circuit, 5: period adjustment circuit, 101: shaper unit, 102: hazard prevention unit, 103: ring oscillator control unit, 104: variable delay circuit, 105: delay time control unit, 106: phase comparison circuit, 150: input Clock signal, 151 to 160: signal, 170: reset signal, 1
80: signal, 201: gate circuit, 202: NAND circuit, 301, 302: flip-flop circuit, 303:
NOR circuit, 304: buffer circuit, 401, 402:
Gate circuit, 403, 404: flip-flop circuit,
405 to 407: inverter circuit, 408: NAND circuit, 450 to 455: signal, 601, 602: NAND
Circuit, 603 to 606: Inverter circuit, 607: NO
R circuit, 608: flip-flop circuit, 609: inverter circuit, 610, 611: buffer, 620, 63
0: signal, 701 to 704: flip-flop circuit, 7
05: NAND circuit, 706: buffer, 707: counter circuit, 750-755: signal, 801-805: N
OR circuit, 806 to 812: selector circuit, 813 to 8
20: Inverter circuit, 850-861: Terminal, 90
1: flip-flop circuit, 902: NOR circuit, 10
01: composite gate circuit, 1002 to 1005: gate circuit, 1051 to 1058: signal, 1101, 1102:
Flip-flop circuit, 1150, 1151: signal, 1
201, 1301: Up-down counter circuit, 130
2: counter circuit, 1303: NOR circuit, 1304:
Inverter circuit, 1350, 1351: signal.

Claims (4)

[Claims] 1. A first repetitive signal having a predetermined frequency is input, and n (n = 2, 3 ...) Of the first repetitive signal is input.
A multiplying circuit for outputting a second repetitive signal having a doubled frequency, comprising means for oscillating a third repetitive signal having a frequency corresponding to the second repetitive signal, and a rising edge of the first repetitive signal (or Falling) to activate the means for oscillating, and the oscillation of the third repetitive signal is continued for n cycles until the next rising (or falling) of the first repetitive signal. And at least means for stopping the third repetitive signal for every one cycle of the first repetitive signal, and aligning the cycle of n times of the third repetitive signal with the second repetitive signal. A multiplication circuit characterized by outputting as a signal. 2. A first repetitive signal having a predetermined frequency is input, and n (n = 2, 3 ...) Of the first repetitive signal is input.
A multiplying circuit for outputting a second repetitive signal having a doubled frequency, comprising at least a ring oscillator control means, a variable delay means, a phase comparison means, and a delay time control means, and the ring oscillator control means. The variable delay means constitutes a ring oscillator by connecting one output to the other input, and the ring oscillator control means is activated at the rising edge (or falling edge) of the first repeating signal, The oscillation of the ring oscillator at the frequency of n times is started, and the oscillation is continued for n cycles and then stopped, and the phase comparison means stops the rise (or fall) of the output of the variable delay means. The timing is compared with the rising (or falling) timing of the first repetitive signal, and the comparison result is compared. Output to the delay time control means, and the delay time control means, based on the comparison result of the phase comparison means, the timing of the rise (or fall) of the output of the variable delay means and the rise of the first repetitive signal. The delay time of the variable delay means is controlled so that the timings of (or falling) coincide with each other, and the output of the variable delay means after completion of control by the delay time control means is output as the second repetitive signal. A multiplication circuit characterized in that 3. The multiplication circuit according to claim 2, wherein the ring oscillator control means selects either one of the output signal of the variable delay means and the first repetitive signal, and the variable delay means. Selector means for outputting to
At the rising edge (or falling edge) of the first repeating signal, the selector means selects the output signal of the variable delay means to start the oscillation of the ring oscillator, and the oscillation continues for the n cycles. A multiplying circuit comprising at least switching means for causing the selector means to select the first repetitive signal and stopping the oscillation of the ring oscillator. 4. The multiplier circuit according to claim 2 or 3, wherein the delay time control means gradually increases the delay time of the variable delay means from a predetermined minimum value. Means for increasing the delay time of the variable delay means and adjusting the rising (or falling) timing of the output of the variable delay means and the rising (or falling) timing of the first repetitive signal. A multiplication circuit characterized by matching.