JPH09245498A - Semiconductor memory device and test method thereof - Google Patents

Abstract

The present invention provides a test circuit capable of realizing a highly functional test with a simple configuration, a semiconductor memory device capable of an efficient burn-in test, and a test method therefor. An address generating circuit for generating an address signal necessary for a selecting operation of a memory array in which rewritable memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines, and the memory array. A test circuit including a data holding circuit provided in a signal path for inputting and outputting data is provided, and the address generating circuit and the data holding circuit are controlled by setting a test mode to externally control a part of the memory array. By writing a test pattern and designating a test mode from the outside to the test circuit, the semiconductor memory device alone is automatically tested by the test circuit according to the test pattern and the test mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and its test, and more particularly to a technique effective when used as a test technique for a dynamic RAM (random access memory) having a large storage capacity.

[0002]

2. Description of the Related Art Regarding the inspection method of IC memory,
Hitachi, Ltd., "Hitachi IC Memory Data Book", page 73, etc., issued March 1991.
It is performed by connecting the IC tester and the IC memory under test. As an example of a semiconductor memory device having a built-in test circuit in which the read data from a memory array is compared with an expected value and the comparison result is held in an internal circuit of the semiconductor memory device, Japanese Patent Laid-Open No. 1-282799 There is a gazette.

[0003]

The above IC tester is
The relatively large scale and high price limit the time spent in one IC memory. Therefore, it is possible to incorporate a test circuit having a high function into the IC memory, but various patterns must be generated in order to check that the internal constituent elements are functioning properly and mutual interference of bits. However, the scale of the test circuit also becomes large. In addition, since the test circuit is used only before the product is shipped, the degree of integration is substantially lowered. Therefore, it is not a good idea to incorporate the above-mentioned highly functional test circuit in the IC memory.

An object of the present invention is to provide a semiconductor memory device having a built-in test circuit capable of implementing a highly functional test with a simple structure and a test method therefor.
Another object of the present invention is to provide a semiconductor memory device capable of performing an efficient burn-in test and a test method thereof. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, an address generation circuit that generates an address signal necessary for a selection operation of a memory array in which rewritable memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines, and data for the memory array. Providing a test circuit including a data holding circuit provided in a signal path for performing input and output,
By controlling the address generation circuit and the data holding circuit by setting the test mode, a test pattern including a series of write and read operations for the memory array is performed by using a test pattern externally written in a part of the memory array. Try to do it.

[0006]

The outline of other typical inventions among the inventions disclosed in the present application will be briefly described as follows. That is, an address generation circuit that generates an address signal necessary for a selection operation of a memory array in which rewritable memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines, and data input to the memory array. A test circuit including a data holding circuit provided in a signal path for outputting is provided, and the address generating circuit and the data holding circuit are controlled by setting a test mode to write a test pattern to a part of the memory array from the outside. By externally designating a test mode for the test circuit, the semiconductor memory device alone is automatically tested by the test circuit according to the test pattern and the test mode.

[0007]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM according to the present invention. In the figure, of the circuit blocks constituting the dynamic RAM, a portion related to the present invention is shown so as to be understood. It is formed on one semiconductor substrate.

The dynamic RAM of this embodiment has a storage capacity of about 64 M (mega) bits, although not particularly limited. The memory array is divided into eight as a whole. Four memory arrays are divided into left and right with respect to the longitudinal direction of the semiconductor chip, and although not shown in the figure in the central portion, an input / output interface circuit such as an address input circuit, a data input / output circuit, and a test circuit Is provided.

As described above, the memory arrays divided into four pieces on the left and right sides with respect to the longitudinal direction of the semiconductor chip are arranged in groups of two. The main word driver MWD is arranged in the central portion of the two memory arrays thus arranged in pairs. The main word driver MWD forms a selection signal for the main word line extending so as to penetrate the one memory array. One memory array is connected to dynamic memory cells forming a storage capacity of 2 Kbits in the main word line direction and 4 Kbits in a complementary bit line (or also referred to as a data line) not shown which is orthogonal to the main word line direction.
Since eight such memory arrays are provided in total,
As a whole, it has a large storage capacity of 8 × 2K × 4K = 64 Mbits.

The one memory array is divided into eight in the main word line direction. A sub-word driver SWD is provided for each of the divided memory blocks. The sub-word driver SWD is divided into の of the length of the main word line and forms a sub-word line selection signal extending in parallel with the main word line. In this example,
In order to reduce the number of main word lines, in other words, to make the wiring pitch of the main word lines gentle, there is no particular limitation, but one main word line consists of four in the direction of complementary bit lines. Place the sub-word lines. As described above, one sub-word line is selected from sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction. A sub word select line driver is provided. This subword select line driver
A selection signal for selecting one of the four subword selection lines extending in the arrangement direction of the subword drivers is formed.

Thus, focusing attention on the above-mentioned one memory array, in the sub-word driver SWD corresponding to one memory block including the memory cell to be selected among the eight memory blocks allocated to one main word line, As a result of selecting one subword selection line, one subword line is selected from the 8 × 4 = 32 subword lines belonging to one main word line. As described above, 2K (204
Since the memory cell of 8) is provided, 2048/8 = 256 memory cells are connected to one sub-word line. Although not particularly limited, in the refresh operation (for example, the self-refresh mode), eight sub word lines corresponding to one main word line are selected.

In the figure, the thick black line indicates S
A is a sense amplifier, and Column Dec provided near the center of the chip is a column decoder. An CTRL disposed between the two memory arrays is an array control circuit, and supplies an address decoder and a timing signal required for operation.

As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into eight in the direction of the complementary bit line. That is, the complementary bit line is divided into eight by the sense amplifier SA indicated by the thick black line. Although not particularly limited, as will be described later, the sense amplifier SA is configured by a shared sense system, and except for the sense amplifiers arranged at both ends of the memory array, complementary bit lines are provided on the left and right around the sense amplifier. , And is selectively connected to either the left or right complementary bit line.

FIG. 2 is a principal block diagram for explaining the relationship between the main word line and the sub word line of the memory array. In the figure, 2 as a representative
Book main word lines MWL0 and MWL1 are shown. These main word lines MWL0 are selected by a main word driver MWD0. The main word line MWL1 is also selected by the similar main word driver.

The one main word line MWL0 has
Eight sets of sub-word lines are provided in the extending direction. FIG. 2 exemplarily shows two sets of the sub-word lines as representatives. As for the sub word line SWL, a total of eight sub word lines of even numbers 0 to 6 and odd numbers 1 to 7 are alternately arranged in one memory block. Even numbers 0 to 6 adjacent to the main word driver and odd numbers 1 to 7 arranged on the far end side of the main word line (opposite side of the word driver)
Except for, the sub word driver SWD arranged between the memory blocks forms a selection signal for the sub word lines of the left and right memory blocks centered on the sub word driver SWD.

As described above, there are 8 memory blocks.
Although it is divided into blocks, as described above, the subword lines corresponding to the two memory blocks are substantially selected by the subword driver SWD at the same time, so that the subword lines are substantially divided into four blocks. In the configuration in which the sub-word lines are divided into the even-numbered 0 to 6 and the even-numbered 1 to 7 and the sub-word drivers SWD are arranged on both sides of each memory block as described above, the sub-word lines SWL arranged at high density according to the arrangement of the memory cells. The sub-word driver SWD and the sub-word line SWL0 and the like can be efficiently laid out.

The sub word driver SWD supplies a selection signal commonly to the four sub word lines 0 to 6 (1 to 7). Further, it supplies an inverted signal via an inverter circuit. A subword selection line FX for selecting one subword line from the above four subword lines is provided. The sub-word selection lines FX are composed of eight lines, such as FX0 to FX7, of which the even-numbered sub-word selection lines FX0 to FX6 are connected to the even-numbered sub-word drivers 0 to FX6.
To 6 of which odd-numbered sub-word select lines FX1
To FX7 are supplied to the sub-word drivers 1 to 7 in the odd columns. Although not particularly limited, the sub-word selection line FX
0 to FX7 are formed by the second metal wiring layer M2 in the peripheral portion of the array, and are similarly formed by the second metal wiring layer M2.
2 main word lines MWL0 to MWLn
Are formed by the third metal wiring layer M3.

FIG. 3 is a principal block diagram for explaining the relationship between the main word line of the memory array and the sense amplifier. In the figure, 1 as a representative
The main word line MWL of the book is shown. This main word line MWL is selected by the main word driver MWD. Adjacent to the main word driver, a sub word driver SW corresponding to the even sub word line
D is provided.

Although not shown in the figure, complementary bit lines (Pair Bit Lines) are provided so as to be orthogonal to the sub-word lines arranged in parallel with the main word lines MWL. In this embodiment, although not particularly limited, the complementary bit lines are also divided into even-numbered columns and odd-numbered columns, and sense amplifiers SA are distributed to the left and right corresponding to the respective memory blocks (memory arrays). The sense amplifier SA is of the shared sense type as described above, but the sense amplifier SA at the end portion is not provided with substantially one complementary bit line.
Connected to the complementary bit line via SFET.

In the configuration in which the sense amplifiers SA are dispersedly arranged on both sides of the memory block as described above, since the complementary bit lines are distributed to the odd columns and the even columns, the pitch of the sense amplifier columns can be made gentle. it can. In other words, it is possible to secure element areas for forming the sense amplifiers SA while arranging complementary bit lines at high density. Input / output lines are arranged along the arrangement of the sense amplifiers SA. This input / output line is connected to the complementary bit line via a column switch. The column switch is composed of a switch MOSFET. The gate of this switch MOSFET is connected to a column decoder (COLUMN D
ECORDER) is connected to the column selection line YS to which the selection signal is transmitted.

FIG. 4 shows a circuit diagram of a main part of an embodiment of the sense amplifier section of the dynamic RAM according to the present invention. FIG. 2 exemplarily shows a sense amplifier SA1 arranged between memory mats (same as the memory block) MAT0 and MAT1 and circuits related thereto. The memory mat MAT1 is shown as a black box, and has a sense amplifier SA provided at an end.
0 is also shown as a black box.

Four dynamic type memory cells are exemplarily shown corresponding to the sub-word lines SWL provided in the memory mat MMAT0. The dynamic memory cell is composed of an address selection MOSFET Qm and an information storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the sub word line SWL
And the drain of the MOSFET Qm is connected to the bit line, and the information storage capacitor Cs is connected to the source. The other electrode of the information storage capacitor Cs is shared and supplied with a plate voltage.

The pair of complementary bit lines are arranged in parallel as shown in the figure, and are appropriately crossed as necessary to balance the capacitance of the bit lines. Such complementary bit lines are connected to input / output nodes of a unit circuit of the sense amplifier by shared switch MOSFETs Q1 and Q2. The unit circuit of the sense amplifier is an N-channel type MO in which a gate and a drain are cross-connected to form a latch.
SFET Q5, Q6 and P-channel MOSFET Q
7, Q8. N-channel type MOSFET
The sources of Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. The common source lines CSN and CSP have power switches MOSF of N-channel MOSFET and P-channel MOSFET.
Each ET is provided so that the power switch MOSFET is turned on by the activation signal of the sense amplifier to supply the voltage necessary for the operation of the sense amplifier.

A MOSFET Q11 for short-circuiting the complementary bit line is provided at the input / output node of the unit circuit of the sense amplifier.
And a precharge circuit including switch MOSFETs Q9 and Q10 for supplying the half precharge voltage HVC to the complementary bit lines. These MOSFET Q9
The precharge signal PCB is commonly supplied to the gates of Q11 to Q11.

The MOSFETs Q12 and Q13 form a column switch which is switch-controlled by the column selection signal YS. In this embodiment, one column selection signal YS
Thus, four pairs of bit lines can be selected. That is, a similar column switch is provided in the sense amplifier SA0 indicated by a black box. As described above, the two sense amplifiers SA0 and SA1 sandwich the memory mat MMAT0 to divide the complementary bit lines into the even-numbered bit lines and the odd-numbered bit lines so that the sense amplifiers SA0 and SA1 correspond to each other. is there. Therefore, the column selection signal YS has a total of four bits corresponding to the two pairs of bit lines exemplarily shown on the sense amplifier SA1 side and the remaining two pairs of bit lines (not shown) provided on the sense amplifier SA0 side. A pair of complementary bit lines can be selected. These two pairs of complementary bit lines are connected to the two pairs of common input / output lines I / O via the column switch.
Connected to.

The sense amplifier SA1 is connected to the memory mat MMA via shared switch MOSFETs Q3 and Q4.
It is connected to the complementary bit line of the similar odd column of T1. The complementary bit lines of the even-numbered columns of the memory mat MMAT1 are connected to a sense amplifier SA2 (not shown) arranged on the right side of the memory mat MMAT1 by the shared switch MOSFET.
Shared switch MOSFET corresponding to Q1 and Q2
Connected via With such a repetitive pattern, the memory array is connected to a sense amplifier provided between memory mats (the memory blocks) formed by dividing the memory array.

For example, when the sub-word line SWL of the memory mat MMAT0 is selected, the sense amplifier SA
The right shared switch MOSFET of 0 and the left shared switch MOSFET of the sense amplifier SA1 are turned on. However, the sense amplifier SA at the above end
At 0, only the right shared switch MOSFET is provided. The signal SHRL is a left side shared selection signal and a SHRR right side shared selection signal.

FIG. 5 is a schematic block diagram showing one embodiment of the peripheral portion of the dynamic RAM according to the present invention. The timing control circuit TG receives a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and an output enable signal / OE supplied from external terminals, and determines an operation mode and responds to it. Thus, various timing signals necessary for the operation of the internal circuit are formed. In this specification and the drawings, the symbol / is used to mean that the low level is the active level. The timing control circuit TG is provided with a test circuit TST having a test function to be described later.

Signals R1 and R3 are row-related internal timing signals, and are used for row-related selection operations.
The timing signal φXL is a signal for taking in and holding a row-related address, and is supplied to the row address buffer RAB. That is, the row address buffer RAB
Is controlled by the address signal A0 by the timing signal φXL.
ＡAi are fetched and held in the latch circuit.

The timing signal φYL is a signal for taking in and holding the column address, which is supplied to the column address buffer CAB via the multiplexer MXY. That is, the column address buffer RAB is
In the normal operation mode, the multiplexer M
The column address signal input from the address terminal via X is fetched by the timing signal φYL and held in the latch circuit. Also, when in test mode,
The column address counter CAC is fetched through the multiplexer MXY and held in the latch circuit.

The signal φREF is a signal generated in the refresh mode, and is supplied to the multiplexer MXX provided at the input of the row address buffer.
In the refresh mode, control is performed to switch to the refresh address signal formed by the refresh address counter circuit RFC. The refresh address counter circuit RFC counts the refreshing step pulse φRC formed by the timing control circuit TG to generate a refresh address signal. In this embodiment, an auto refresh and a self refresh as described later are provided. Although not particularly limited, the refresh address counter circuit RFC is also used to form an X address signal in the test mode.

The timing signal φX is a word line selection timing signal, which is supplied to the decoder XIB, and is supplied to the decoder XIB based on the decoded signal of the lower 2 bits of the address signal.
Word line selection timing signals XiB are formed. The timing signal φY is a column selection timing signal and is supplied to the column system predecoder YPD to output the column selection signals AYix, AYjx, AYkx.

The timing signal φW is a control signal for instructing a write operation, and the timing signal φR is a control signal for instructing a read operation. These timing signals .phi.W and .phi.R are supplied to the input / output circuit I / O to activate the input buffer included in the input / output circuit I / O during the write operation and bring the output buffer into the output high impedance state. On the other hand, at the time of the read operation, the output buffer is activated, and the input buffer is set to the output high impedance state. This input / output circuit I /
The O has a register REG. This register R
The EG is mainly used in the test mode. In other words, it is used for generating the write signal by temporarily storing the data read from the memory array and performing logical processing such as that or inverting it by a control signal.

Although the timing signal φMS is not particularly limited, it is a signal for instructing a memory array selection operation, is supplied to a row address buffer RAB, and outputs a selection signal MSi in synchronization with this timing. Timing signal φSA is a signal for instructing the operation of the sense amplifier. An activation pulse for the sense amplifier is formed based on the timing signal φSA.

In this embodiment, a row-related redundant circuit XR
ED is illustratively shown as a representative. That is, the circuit X-RED includes a storage circuit for storing a defective address and an address comparison circuit. The stored defective address is compared with the internal address signal BXi output from the row address buffer RAB, and when they do not match, the signal XE is set to the high level, and the signal XEB is set to the low level to enable the operation of the normal circuit. When the input internal address signal BXi matches the stored defective address, the signal XE is set to low level to inhibit the operation of selecting the defective main word line of the normal circuit, and the signal XEB is set to high level to set one signal. A selection signal XRiB for selecting a spare main word line is output.

The outline of the test operation by the test circuit of this embodiment is as follows. By a normal memory access, a test pattern is written in a predetermined storage area of the memory array from an external test device such as a tester. When the writing of such a test pattern is completed, the test mode is set. The setting of this test mode is not particularly limited, but when the signal / RAS is at high level,
It is created by a combination of control signals / RAS, / CAS, / WE and / OE which do not exist in normal memory access such as setting / CAS and / WE and / OE to low level.

When the test mode as described above is entered, the refresh address counter RFC is not particularly limited.
And the column address counter CAC is initialized. This initialization is the start address of the storage area in which the test pattern is written. If the predetermined storage area corresponds to the cleared counter RFC and CAC, the initialization is performed for each counter RFC and CAC.
You can clear (reset) both and.

By generating the address signal as described above,
The data is read from the predetermined storage area, stored in the register of the input / output circuit I / O, inverted as it is or by the inverter circuit, and the Y address counter CAC is incremented by +1 and sequentially written. . When all the initialized X addresses have been written, the refresh address counter RFC is caused to perform a counting operation of +1 and the next X address is sequentially written while advancing the column address in the same manner as above. To do.

If the above-described write operation is performed for all memory areas, the address counters RFC and CAC return to the initial state, so the test pattern signal is read from the top address and the input / output circuit I / A test pattern is set to the register REG of O, and the comparison circuit compares the stored data sequentially read from the subsequent addresses with the expected value as an expected value. It is stored that there is a defect in the latch circuit that stores the defect flag.

When such a test mode is used in the burn-in test as will be described later, the above operation may be repeated during the time required for burn-in. When using to perform a test operation instead of a conventional tester, read out whether there is a defect in the latch circuit from the tester, input another test pattern, and perform a similar test based on this test pattern. carry out. In this case, the tester only needs to input the test pattern for starting the test and set the test mode.

Therefore, when performing a test on the semiconductor memory device according to the present invention, the tester is connected only at the start stage of the test, and is disconnected from the semiconductor memory device for most of the test time, and other similar tests are performed. Only the test start setting for the semiconductor memory device need be made. In other words, the substantial test time when one semiconductor memory device is viewed from the tester is, although the test time in the semiconductor memory device is spent for a long time.
The test time including one test pattern including the electrical connection and disconnection can be made as short as 1 to 2 seconds. When a plurality of (N) semiconductor memory devices can be simultaneously connected at one time, the test time for one semiconductor memory device seen from the above tester can be further shortened to 1 / N.

FIG. 6 shows a synchronous D according to the present invention.
A schematic block diagram of one embodiment of a RAM (hereinafter simply referred to as SDRAM) is shown. SDRA shown in the figure
The M is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The SDRAM of this embodiment has a memory bank 0 (BANK).
0) A memory array (Memory Array) 200A
And a memory array 200B constituting the memory bank 1 (BANK1).

Each of the above memory arrays 200A, 2A
00B includes dynamic memory cells arranged in a matrix similar to the dynamic RAM described above. According to the drawing, the selection terminals of the memory cells arranged in the same column are connected to word lines (not shown) for each column. The data input / output terminals of the memory cells arranged in the same row are coupled to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to a selection level according to the decoding result of the row address signal by the row decoder 201A. The complementary data lines (not shown) of the memory array 200A are sense amplifiers and column selection circuits (Sense Ampli
fier & I / O BUS) 202A. The sense amplifier (Sense A in the sense amplifier and column selection circuit 202A)
mplifier) is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from the memory cell. In that case, the column switch circuit selects the complementary data lines individually and selects the complementary common data lines (I
/ O BUS). The column switch circuit is a column decoder 20.
The selection operation is performed according to the result of decoding the column address signal by 3A.

On the side of the memory array 200B, similarly to the above, a row decoder 201B, a sense amplifier and column selection circuit (Sense Amplifier & I / O BUS) 202B.
Also, a column decoder 203B is provided. The complementary common data line (I / O BUS) of the memory banks 200A and 200B is a shift register (Shifr register) 21 used for image processing as described later.
2 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. The input terminal of the input buffer 210 and the output terminal of the output buffer 211 are connected to 8-bit data input / output terminals I / O0 to I / O7.

The row address signal and the column address signal supplied from the address input terminals A0 to A11 are fetched in a column address buffer (Column Address Buffer) 205 and a row address buffer (Row Address Buffer) 206 in an address multiplex format. The supplied address signals are held in the respective buffers 205 and 206. The row address buffer 206 is a refresh counter (Refresh Counte) in the refresh operation mode.
r) The refresh address signal output from 208 is fetched as a row address signal. The refresh counter 208 is also used in the test mode as described above, and generates a test row address signal.

The output of the column address buffer 205 is the column address counter 2
The column address counter 207 supplies the column address signal as the preset data, or a value obtained by sequentially incrementing the column address signal, according to an operation mode specified by a command or the like described later. 203A, 20
Output to 3B. Column address counter 2
07 is also used in the test mode as described above,
Generates a column address signal for testing.

Controller (Control Logic & Timing Ge
nerator) 213 includes, but is not limited to, a clock signal C
LK, clock enable signal CKE, chip select signal / CS, column address strobe signal / CAS
(The symbol / means that the signal attached thereto is a row enable signal), external control signals such as a row address strobe signal / RAS, a write enable signal / WE, and a data input / output mask control signal DQM;
Control data from the address input terminals A0 to A11 are supplied, and an internal timing signal for controlling the operation mode of the SDRAM and the operation of the circuit block is formed based on a change in the level of these signals and timing. Therefore, it has a control logic and a mode register for that purpose.

The clock signal CLK is used as the master clock of the SDRAM, and the other external input signals are significant in synchronization with the rising edge of the internal clock signal. The chip select signal / CS instructs the start of a command input cycle by its low level. When the chip select signal / CS is at a high level (chip is not selected) and other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. /
The RAS, / CAS, and / WE signals have different functions from the corresponding signals in a normal DRAM, and are significant signals when defining a command cycle described later.

The clock enable signal CKE is a signal for instructing the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. Further, in a read mode (not shown), an external control signal for controlling output enable for the output buffer 211 is also supplied to the controller 213. When the signal is at a high level, for example, the output buffer 211 is set to a high output impedance state.

The row address signal is the clock signal C.
It is defined by the levels of A0 to A10 in a row address strobe / bank active command cycle described later that is synchronized with the rising edge of LK (internal clock signal). The input from A11 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A11 is at a low level, the memory bank BANKA is selected, and when the input of A11 is at a high level, the memory bank BANKB is selected.
The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the input buffer 210 and the output buffer of the selected memory bank only. It can be performed by processing such as connection to 211.

The input of A10 in the precharge command cycle described later indicates the mode of the precharge operation for the complementary data lines and the like, and its high level indicates that the precharge targets are both memory banks, and its low level. Indicates that one of the memory banks designated by A11 is to be precharged.

The column address signal is defined by the levels of A0 to A8 in the read or write command (column address read command, column address write command described later) cycle synchronized with the rising edge of the clock signal CLK (internal clock). To be done.
The column address defined in this way is used as a start address for burst access.

Next, the SDR designated by the command
The main operation mode of the AM will be described. (1) Mode register set command (Mo) This is a command for setting the mode register 30 and is data specified by / CS, / RAS, / CAS, / WE = low level, and data to be set (register set data). ) Is given via A0-A11. The register set data may be burst length, CAS latency, write mode, etc., although not particularly limited. Although not particularly limited, burst lengths that can be set are 1, 2, 4, 8 and full page (25
6) and the configurable CAS latencies are 1, 2,
3, the settable write mode is burst write and single write.

The CAS latency is output buffer 21 from the falling edge of / CAS in a read operation instructed by a column address read command described later.
This indicates how many cycles of the internal clock signal are to be consumed before the output operation of 1. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the internal clock signal. In other words, when using a high-frequency internal clock signal, set the CAS latency to a relatively large value, and when using a low-frequency internal clock signal, set the CAS latency to a relatively small value. I do. Although not particularly limited, the CAS latency may be set to a large value in order to secure the word line switching time in the image processing operation described later, if necessary.

(2) Row address strobe / bank active command (Ac) This is a command for validating the row address strobe instruction and the memory bank selection by A11.
Instructed by S, / RAS = low level and / CAS, / WE = high level, addresses supplied to A0 to A10 at this time are taken as row address signals, and signals supplied to A11 are taken in as memory bank selection signals. . The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

(3) Column address read command (Re) This command is a command necessary for starting the burst read operation, and also a command for giving a column address strobe, / CS, / CAS =
Instructed by low level, / RAS, / WE = high level. At this time, column addresses supplied to A0 to A8 are taken in as column address signals. The fetched column address signal is supplied to the column address counter 207 as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the internal clock signal. Are sequentially selected in accordance with the address signal output from the column address counter 207 and are successively read out. The number of data to be continuously read is the number specified by the burst length. The start of reading data from the output buffer 211 is performed after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column address write command (Wr) When the burst write is set in the mode register as the mode of the write operation, it is a command necessary to start the burst write operation, and the mode of the write operation. When the single write is set in the mode register as, the command is required to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The command is / CS, / CA
S, / WE = low level, / RAS = high level. At this time, addresses supplied to A0 to A8 are taken in as column address signals. The column address signal thus captured is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the acquisition of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a start command for the precharge operation for the memory bank selected by A10 and A11, and /
Instructed by CS, / RAS, / WE = low level and / CAS = high level.

(6) Auto-refresh command This command is a command required to start auto-refresh and is / CS, / RAS, / CA.
Instructed by S = low level, / WE, CKE = high level.

(7) Burst stop in full page command This command is necessary to stop the burst operation for full pages for all memory banks, and is ignored in burst operations other than full page. This command is for / CS, / WE = low level, / RAS, / CA
Indicated by S = high level.

(8) No operation command (No
p) This is a command instructing that no substantial operation is performed, / CS = low level, / RAS, / CAS, /
Indicated by the high level of WE.

(9) Check & operation command This command is for setting the test mode, and / CS = low level, / RAS, / CAS, / W.
It is set by a combination other than the above combination of E, and the automatic test mode and the necessary arithmetic processing are designated.
When this command is input, for example, the address signal is referred to, and one of a plurality of types of test modes is set in the check & calculation unit. When the test mode is set, the check & calculation unit is operated by the address counter 2 described above.
07, 208 and the register 212 are controlled to execute the test operation as described above while performing the data processing and comparison operation in the arithmetic unit using the test pattern written in the specific area as described above. .

Since the SDRAM can input and output data, address and control signals in synchronization with the clock signal CLK (internal clock signal), it is possible to operate a large capacity memory similar to the DRAM at a high speed comparable to that of the SRAM. ,
By specifying the number of data to be accessed for one selected word line by the burst length, the selection state of the column system is sequentially switched by the built-in column address counter 207, and a plurality of data are accessed. Can be read or written continuously.

In the SDRAM, when a burst operation is performed in one memory bank, another memory bank is designated in the middle of the burst operation and a row address strobe / bank active command is supplied. The row address operation in the other memory bank is enabled without affecting the operation in one memory bank. For example, the SDRAM has means for internally holding data, addresses, and control signals supplied from the outside, and the held contents, particularly the address and control signals, are held for each memory bank. Alternatively, the data for one word line in the memory block selected by the row address strobe / bank active command cycle is latched in advance by the latch circuit (not shown) for the read operation before the column operation. There is. Therefore, as long as data does not collide at the data input / output terminals I / O0 to I / O7, during execution of a command whose processing is not completed, a command for a memory bank different from the memory bank to be processed by the command being executed is executed. It is possible to start the internal operation in advance by issuing a charge command and a row address strobe / bank active command.

Therefore, in the SDRAM of this embodiment, these functions can be effectively used to perform the internal automatic test operation. That is, check & as above
The arithmetic unit includes a register 212 provided in the input / output unit, a refresh counter 208, and a column address counter 2.
07, the test pattern is stored in the memory bank 0, and the memory bank 1 is tested using the test pattern. Alternatively, the test pattern is written to the memory bank 0 by inputting a test command by externally writing the above-described basic test pattern to the head address portion of the memory bank. After that, the write operation is performed on all the memory arrays by a simple write operation of sequentially copying the storage data of the memory bank 0 to the memory bank 1. Then, the memory banks 0 and 1 are read out, and the quality is judged by the comparison in the arithmetic unit.

FIG. 7 shows a block diagram of another embodiment of the semiconductor memory device to which the present invention is applied. The semiconductor memory device of this embodiment is directed to an image memory having a random input / output port and a serial input / output port. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

Row address buffer (Row Add. Buff) 1
Takes in a row (X) system address signal input in synchronization with a row address strobe signal / RAS from an address terminal Address and supplies an internal address signal to a row decoder (Row Decoder) 3. The row decoder 3 decodes it and selects one word line. The row decoder 3 also includes a word driver that drives a word line that has a large load capacitance by connecting a large number of memory cells at high speed.

Column address buffer (Column Add.
ff) 2 takes in the column (Y) system address signal input in synchronization with the column address strobe signal / CAS from the address terminal Address and outputs the internal address signal to the random column decoder (Column Decoder) 5
And address counter for serial (SAM Add. Counte
r) Supply to 13. The column decoder 5 for random is
In the random access mode, the address signal is decoded to form the bit line selection signal. The address counter 13 for serial, when in the serial access mode,
Take it in as an initial value.

In the memory array 6, a dynamic memory cell composed of an address selection MOSFET and an information storage capacitor is arranged in a matrix at the intersections of the word lines and the bit lines (or the data lines or digit lines). The bit line is of a folded bit line type in which a pair of complementary bit lines are arranged so as to extend in parallel to the sense amplifier SA. In the figure, the bit lines are arranged to extend in the horizontal direction of the memory array 6, and the word lines are arranged to extend in the vertical direction of the memory array 6.

The circuit block 5 comprises a sense amplifier SA and an input / output line (I / O Bus). The sense amplifier SA and the input / output line (I / O bus) 3 are provided corresponding to the bit lines of the memory array 6. The sense amplifier SA amplifies a minute signal level difference read to the complementary bit line and amplifies the potential of the complementary bit line into a high level and a low level corresponding to the power supply voltage and the ground potential of the circuit. As a result, the read signal can be amplified and restored based on the information charge that is about to be lost in the information storage capacitor that constitutes the memory cell due to the read operation. Among the above input / output lines (I / O Bus), the above bit lines
A column switch MOSFET connected to us) is also included. The selection signal formed by the column decoder 4 is supplied to the gate of the column switch MOSFET.

One of the input / output lines (I / O bus) 3 is an output buffer (Output B) which constitutes a random port.
uffers) 8. In this embodiment, although not particularly limited, 4-bit unit data is randomly input / output. The 4-bit random data is output from the terminal I / O through the output buffer 8.

A pixel data arithmetic circuit 9 is provided for inputting random data. This arithmetic circuit performs logical operations such as logical product, logical sum and exclusive logical sum of image data. The calculation result of the calculation circuit 9 is written in the memory array 6 through the column selection circuit for the random port in the same memory cycle or output through the output buffer 8.

Input Data Control Circuit
l) 10 has a mask register and the like, and enables masking of any bit in the data of a unit of 4 bits. That is, for a specific bit of the input data input from the external terminal I / O, the data is masked to prevent writing, and the original bit is retained. This allows
Only specific bits of the 4 bits can be rewritten.

The write control circuit (Write Control) 11 is
The input data control circuit 10 and a write address control circuit (Write Add. Control) 12 described below are controlled, and the input data control circuit 10 is set with data masking. The write address control circuit 12
Masking for block writing composed of a plurality of data units or flash writing for each word line unit described below is performed. For block write, multiple unit data
The same data is written as one block. The flash write is for writing the same data in word line units. These write operations are specifically realized by instructing the column decoder 4 to perform multiple selection of column switches in block units or word line units. Since the block write and flash write functions exist as described above, the serial input function of the serial port described below may be omitted.

The serial memory (SAM) 15 is composed of a static RAM, and also includes a transfer gate for transferring the information of the bit lines of the memory array 6 in parallel. Although not particularly limited, the SAM 15 is divided into two parts, and the data transfer circuit is also divided into two parts corresponding to the SAM 15, so that when one side performs serial input / output, the other side transfers data between the memory arrays 6. Good.

Serial selection circuit (SAM Column Decoder)
Reference numeral 14 decodes the address signal formed by the address counter 13 to form a selection signal supplied to the gate of the switching MOSFET for selection of the serial memory 15, and the serial output circuit (SAM) through the serial output line. Output Buffer) 17 through output terminal SI /
Output from O. Alternatively, the serial input circuit (SAM I
The serial data input via the nput buffer 16 is transferred to the serial memory 15.

In order to perform random input / output or serial input / output in 4-bit units as described above, the memory array 6
It should be understood that four are provided, and four data input / output paths are provided corresponding to each. The peripheral circuit for address selection is provided in common to the four circuits and simultaneously accesses each of them.

Timing Generation Circuit (Timing Generator)
18 is a signal / RAS, / CAS supplied from the outside,
Upon receiving / DT / OE, / WE, DSF1, DSF2, SC and / SE, various control signals and timing signals necessary for the operation of the internal circuit are generated. Where / RAS, /
In CAS, / WE, etc., the attached slash (/) is a signal for setting the low level to the active level, and usually corresponds to the addition of a horizontal line (bar) above a character.

Of the above signals, / RAS and / CAS are strobe signals for fetching the address signal as described above. / WE is a write enable signal, which is a read operation when it is at a high level during random access and a write operation when it is at a low level. / DT / OE
Has two meanings: parallel transfer timing control for setting the operation timing of the transfer gate according to the operation mode and output enable control.

SC is a serial clock, and the address counter 12 counts this and generates a serial address signal. That is, data is output from the serial output terminal SI / O in synchronization with the serial clock SC. /
SE is a silyl enable signal. When this signal is set to a low level, each circuit for the serial output operation is activated and the serial data output as described above is performed.

The control clock generation circuit 18 receives the output enable signal / OE, the row address strobe signal / RAS, the column address strobe signal / CAS, and the write enable signal / WE, determines the internal operation mode, and responds to the clock operation accordingly. Generate a pulse. Clock pulses for serial transfer of the serial input / output circuit are also supplied from here to the shift register.

Refresh Counter
19 starts its operation by setting / CAS to a low level when / RAS is at a high level, performs a counting operation using a change in / RAS as a clock, and generates a row-related address signal necessary for the refresh operation. This refresh address signal is supplied to the row decoder 3 through the row address buffer 1 to read and amplify the memory cell by the word line selecting operation and the sense amplifier SA amplifying operation, and rewrite it to the original memory cell. Perform a refresh operation.

The mode setting for activating the arithmetic circuit 9 is designated by DSF1 and DSF2. The type of calculation is set by the above control signals / RAS, / CAS, / DT
It is set by a combination of / OE, / WE, SC and / SE. For example, when the signal / RAS is at high level / WE
Is set to the low level, the operation mode is set and the DSF
Depending on the combination of 1 and DSF2, each operation mode of logical product, logical sum, or exclusive logical sum may be designated, or other control signals may be combined. Alternatively, the type of operation may be designated by a combination of the signal DSF1 and an address signal or data.

In this embodiment, the refresh counter 19 and the SAM address counter 13 as described above are used to generate X-system address signals and Y-system address signals.
A test pattern stored at a specific address of the memory array 6 is used, and it is processed using the above arithmetic circuit,
The write data is generated, or the test pattern and the read signal are compared with each other. At this time, it is also possible to use the data stored in the register for one word line of the SAM section to perform the copy in word line units in the memory array.

In the two-port memory as in this embodiment, the test bit pattern is written to a specific word line, read in parallel to the SAM section, and is read as it is, inverted, or shifted by 1 bit. Write in parallel to memory cells of different word lines of the memory array. By using this kind of operation, writing all 0s and all 1s,
Writing of a flag bit pattern, a stripe pattern, etc. can be performed efficiently. The setting of the test mode as described above is performed by the control clock generation circuit 18
Is performed by the test circuit as described above.

FIG. 8 shows a block diagram of an embodiment of the microcomputer according to the present invention. Each circuit block in the figure is formed on a semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The microcomputer MCU has a so-called stored program type central processing unit CPU as its basic constituent element.

The central processing unit CPU is not particularly limited, but includes a read-only memory ROM, a random access memory RAM, an analog-digital conversion circuit A / D, a watchdog timer WDT, and an internal bus IBUS.
The timer circuit TIM and the serial communication interface SCI are coupled. A predetermined clock signal CLK is supplied from the clock generation circuit CLKG to each unit of the microcomputer MCU including the central processing unit CPU, and the microcomputer MCU further controls a clock controller for controlling the operation of the clock generation circuit CLKG. CLKC and a power-on reset circuit POR for resetting each part of the microcomputer MCU to the initial state when the power is turned on.

The watchdog timer WDT is supplied with an internal signal PR from the central processing unit CPU, and its output signal, that is, the abnormality detection signal TD, is sent to the clock controller C.
Supplied to LKC. In addition, the clock generation circuit CLKG
One of the input terminals is coupled to one electrode of the crystal oscillator XTAL via the external terminal EXTAL, and the other input terminal is supplied with the clock output signal CG of the clock controller CLKC. The other electrode of the crystal oscillator XTAL is coupled to the clock controller CLKC via the external terminal XTAL.

The power-on reset circuit POR is supplied with the power supply voltage VCC and the ground potential VSS, which are the operating power supplies of the single-chip microcomputer MCU, via the external terminals VCC and VSS, respectively. The power-on reset signal POR is supplied to the clock controller CLKC. The clock controller CLKC further includes a complete stop control register RST from the central processing unit CPU.
The output signal RSTP of P (first register) and the output signal RCMD of the mode control register RCMD (second register) are supplied, and the output signal, that is, the normal reset signal RS, of the microcomputer MCU including the central processing unit CPU. Supplied to each part.

The central processing unit CPU carries out step operation according to the user program stored in the read-only memory ROM to execute predetermined arithmetic processing and
Controls and controls each part of the microcomputer. In this embodiment, the central processing unit CPU comprises an instruction-writable complete stop control register and a mode control register, the output signals RSTP and RCMD of which are supplied to the clock controller CLKC as described above. The internal signal PR indicating the program execution status of the central processing unit CPU is constantly monitored by the watchdog timer WDT and is used for abnormality detection of the microcomputer MCU.

The read-only memory ROM is, for example, a mask ROM having a predetermined storage capacity, and stores programs and fixed data necessary for controlling the central processing unit CPU. In addition, a simple program for carrying out a test of a built-in RAM described later is also stored. The random access memory RAM is, for example, a static RAM having a predetermined storage capacity, and temporarily stores the calculation result of the central processing unit CPU, control data, and the like. Further, the analog-digital conversion circuit A / D converts an analog input signal input from various external sensors into a digital signal of a predetermined bit and transmits it to the central processing unit CPU or the like via the internal bus IBUS. The timer circuit TIM measures time according to the clock signal supplied from the clock generation circuit CPG, and the serial communication interface SCI is a high speed interface between a serial input / output device and a random access memory RAM, which are coupled to the outside of the microcomputer, for example. Support data transfer.

The watchdog timer WDT monitors the internal signal PR output from the central processing unit CPU, and in response to the internal signal PR not being formed over a predetermined time, in other words, the instruction by the central processing unit CPU. In response to the fact that the fetch is not performed for a long period of time, an abnormality of the central processing unit, that is, the microcomputer is detected, and its output signal, that is, the abnormality detection signal TD is selectively set to the high level. Power-on reset circuit POR
Monitors the potentials of the power supply voltage VCC and the ground potential VSS supplied through the external terminals VCC and VSS, and temporarily outputs the output signal, that is, the power-on reset signal POR, for a predetermined period when the operating power is turned on. To high level. The abnormality detection signal TD from the watchdog timer WDT and the power-on reset signal POR from the power-on reset circuit POR are supplied to the clock controller CLKC.

Microcomputer MCU of this embodiment
Is a mode control register RCMD of the central processing unit CPU
Is in the set state, its output signal RCMD is set to the high level, and the watchdog timer WDT detects the abnormality of the central processing unit CPU, thereby detecting the abnormality detection signal TD.
Is set to a high level, or the central processing unit CP
Complete stop control register RST by set command from U
When P is set and its output signal RSTP is set to the high level, the normal operation state is selectively transited to the complete stop state, and the operation is completely stopped. This complete stop state is the reset signal RST via the external terminal RST.
Is set to a high level, or the central processing unit C
Since the mode control register RCMD of the PU is in the reset state, its output signal RCMD is set to the low level and the central processing unit CPU is controlled by the watchdog timer WDT.
Is detected and the abnormality detection signal TD is set to the high level, the normal reset is not canceled even if the reset is executed, and the operating power of the microcomputer MCU is turned on again to turn off the power-on reset signal POR. It will be released for the first time.

As a result of the above, it is possible to realize a microcomputer capable of preventing a runaway state at the time of occurrence of an abnormality without the need for external parts, and by this, the occurrence of an abnormality in the microcomputer and automobiles and industrial machines including the same. It is possible to prevent accidents and damages of parts at the time and improve the reliability of the system. Reset signal RS
T, abnormality detection signal TD, output signal RCMD of mode control register RCMD, output signal RSTP of complete stop control register RSTP and power-on reset signal POR
When both are set to the low level, the state of the microcomputer MCU is not changed and the normal operation state or the complete stop state is continued. In addition, microcomputer MCU
The reset state is released unconditionally upon the fall of the normal reset signal RS, and transitions to the normal operation state.

In a microcomputer having a built-in RAM as described above, when the built-in RAM is tested,
A test pattern written in a specific storage area of the RAM as described above is used. That is, when a test pattern is externally stored in a specific area of the RAM by a tester or the like and a test mode is set, the test pattern of the RAM is read and the data is processed according to a simple test program stored in the ROM. A test is repeated to perform and write to another area of RAM. At this time, a +1 operation is performed every cycle so that a test address is generated so that address information is also written in a specific area of the RAM. By doing so, the address counting operation can be realized by utilizing the adder circuit of the central processing unit and the RAM.

FIG. 9 is a flow chart for explaining an embodiment of the semiconductor memory device testing method according to the present invention. In step (1), the semiconductor memory device is assembled. As is well known, a semiconductor memory device has semiconductor memory chips formed in a grid pattern on a semiconductor wafer. When an element forming process is completed, a test operation is performed by wafer probing, and a dicing process is performed to individually cut individual semiconductor wafers. After being separated into the semiconductor chips, the non-defective ones and the defect-relieved ones are directed to the assembly of the step (1) according to the result of the test, and the defective semiconductor chips are discarded.

In step (2), a test by a tester is carried out. The test by the tester is a high-precision voltage value / current value test and a DC function test of a memory unit for a general-purpose memory such as a conventional dynamic RAM. This confirms the basic operation of the general-purpose memory. Specifically, in step (2), although not particularly limited, (1) DC parametric test and (2) DC function test are performed. The (1) DC parametric test is an open / short test and highly accurate measurement of various current values, output pin voltage level and current level, input pin voltage level and current level, and the like. The above (2) DC function test
They are easy function test and timing test.

In step (3), a test using the built-in memory is performed. In the test using this built-in memory, as described above, the test pattern is written from the tester to the memory array of the IC memory to be inspected, and the memory is set to the test mode. carry out. The test items performed in this step (3) are not particularly limited, but the logic part functional test, the logic part high speed operation functional test, the long-time measurement test (retention test, shoe test, pause / refresh test, power-on test) ), RAM AC test (high-speed DC function test), RAM
Part special function test (user specification test, bump test). In the logic part function test, each operation mode operates as specified, or in the image memory of 7 or the like, the function in the operation part is inspected.

Various patterns such as all 0, all 1, checkered flag, stripe pattern, marching, galloping, walking, ping-pong, etc. are available as various patterns for inspecting whether the internal elements of RAM are functioning properly. Is being considered. These patterns may be useful for examining mutual interference of bits, or may be patterns that maximize power consumption. The former four are so-called N patterns, and N
It is possible to examine one sequence with a pattern of an integer multiple of N at most for the bit memory IC. The latter three contrast, known as N ² pattern, requiring multiple of the pattern of N ² with respect to the N-bit memory. For this reason, in a dynamic RAM having a small storage capacity of 1 Mbit, for example, 120 hours are actually consumed when an inspection is performed by galloping. Therefore, in the dynamic RAM having the storage capacity of 64 times that of FIG. 1, even if the built-in test circuit is used, it is not realistic.

FIG. 10 shows a simplified block diagram for explaining the inspection method by marching. Marching is a pattern in which all 0s are written and 1s progress. That is, the storage data of all the memory cells are cleared to 0 as shown in FIG.
Next, as shown in (B), the memory cell at address 0 is read out and set to 0.
Check that it is and write 1 to it. Less than,
If 0 is read sequentially and checked while advancing the address, it is rewritten to 1 and finally all the stored data are set to 1. Then, when all the values become 1, the original 0 state is obtained by rewriting the above 1 to 0. In this way, 5N memory cycles can complete the test for the N-bit memory.

FIG. 11 is a schematic block diagram for explaining the method of testing the semiconductor memory device according to the present invention. After the test circuit is provided in the semiconductor memory device as described above and the basic test pattern and test mode are set by using the memory array of the semiconductor memory device itself,
After that, even if there is no instruction from the tester, the address signal is generated by itself and the same operation is repeated.

Therefore, in this test method, a substantial test is not performed in the state where the IC memory and the IC tester are connected one-to-one as in the conventional case, that is, the so-called online state. That is, the IC tester only sets the necessary test pattern (expected value) and test mode for the currently connected memory under test IC7, and when such setting is completed, similar settings are made before that. The tested memories IC1 to IC6 are separated from each other.
That is, the IC to be inspected is conveyed in the direction shown by the arrow in the figure, the tester is connected to the next memory IC 8 to be inspected,
Set the same test pattern and test mode as above.
After that, n pieces of memories to be inspected from IC1 to ICn are sequentially circulated around the tester by a conveying device such as a turntable or a belt conveyor.

If the test time by the above-mentioned built-in test circuit is shortened with respect to the time required for one IC1 to be connected to the tester again, the tester can successively test the memories to be inspected without wasteful waiting time. A test input operation can be performed, and in a memory having a pass / fail judgment result function as described above, the pass / fail judgment flag is read and the next test step is designated.

As described above, the substantial test time for one IC memory when viewed from the tester is the above test pattern and test mode even if the true test time by the test circuit built in the IC memory becomes long. Setting, and reading of the pass / fail judgment result for each test step becomes an extremely short time, which makes it possible to substantially reduce the test time and significantly reduce the cost.

In FIG. 9, in the state where the IC memory is separated from the IC tester as described above, paying attention to performing the test operation involving continuous writing and reading by the built-in test circuit, the initial defect detection In the burn-in step (4) for, the test using the built-in memory is performed again. That is, in this step (4), the IC memory is placed in a high-temperature furnace to operate all of the X-system address selection circuit, the Y-system address selection circuit, and the read / write circuit, so that the initial failure is highly reliable. Can be washed out.

In step (5), a test is performed to determine the initial failure after burn-in. This step (5)
If the test result in the burn-in step (4) is stored in the above-mentioned blowfish, it can be omitted substantially. In other words, after a burn-in test in which a relatively long time has been spent, the test results are read by an IC tester or the like into a storage circuit such as a flip-flop of a built-in test circuit, and only defective products are tested.
A test with an IC tester may be performed again for confirmation and analysis of a defective portion.

The operational effects obtained from the above embodiment are as follows. That is, (1) an address generation circuit for generating an address signal necessary for a selection operation of a memory array in which rewritable memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines, and the memory array. A test circuit including a data holding circuit provided in a signal path for inputting and outputting data to and from the memory array is provided as a part of the memory array by controlling the address generating circuit and the data holding circuit by setting a test mode. By performing a test operation including a series of write and read operations on such a memory array by using a test pattern written from the semiconductor memory device, a semiconductor memory device can perform a test that requires a long time by itself. The effect of being able to do is obtained.

(2) The memory cell is a dynamic memory cell, and a part of the address generation circuit is shared by the X address counter of the built-in automatic refresh control circuit, so that the test circuit can be simplified. The effect is obtained.

(3) The memory array is composed of two memory banks forming a synchronous dynamic RAM, and the address generating circuit has an internal X-address counter for automatic refresh and a Y-address counter for burst mode. The test pattern is stored in one memory bank, and the test operation including the write and read operations is performed for the other memory bank, thereby simplifying the test circuit. The effect that it can be realized is obtained.

(4) The test circuit compares the internally generated expected value including the test pattern with the signal read by the read operation from the memory signal written by the write operation, and the comparison result is obtained. An effect that the efficiency of the test can be achieved by providing a function of storing in a part of the memory array is obtained.

(5) Address generating circuit for generating address signals necessary for selecting operation of a memory array in which rewritable memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines, and the above memory A test circuit including a data holding circuit provided in a signal path for inputting and outputting data to and from the array is provided, and the address generating circuit and the data holding circuit are controlled by setting a test mode to form a part of the memory array. By writing a test pattern from the outside and designating the test mode from the outside to the above test circuit, the semiconductor memory device alone can automatically perform the test according to the test pattern and the test mode by the above test circuit. , The tester's use time in the IC test can be shortened, and the efficient tester can be used. The effect that a strike can be realized is obtained.

(6) By performing the continuous test operation by the test circuit when performing the burn-in, there is an effect that it is possible to wash out the initial defect with high reliability.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, a sequential test operation is a program-type test in which a command for instructing a series of read / write operations and address stepping operations is stored in a memory array, the commands are sequentially read, and a series of operations in accordance with the commands are performed. A circuit may be provided. In this case, the memory itself can perform a more complicated test operation. As described above, in a dynamic RAM having a large storage capacity of about 64 Mbits, the overall circuit scale itself is large, so even if the test circuit of the programming method as described above is built in, the proportion occupied by it is small. can do.

In addition to the read / write operations such as the dynamic type RAM and the static type RAM, the present invention is practically applicable to the flash memory having the on-board electrical erasing function. Since the same writing and reading as the RAM are possible, the same can be applied. Further, such a semiconductor memory device includes, in addition to the semiconductor memory device incorporated in the microcomputer,
It may be incorporated in various digital integrated circuit devices such as a gate array.

[0116]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an address generation circuit that generates an address signal necessary for a selection operation of a memory array in which rewritable memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines, and data for the memory array. Providing a test circuit including a data holding circuit provided in a signal path for performing input and output,
By controlling the address generation circuit and the data holding circuit by setting the test mode, a test pattern including a series of write and read operations for the memory array is performed by using a test pattern externally written in a part of the memory array. By doing so, it is possible to perform a test in which the semiconductor memory device itself needs to spend a long time.

An address generating circuit for generating an address signal necessary for a selecting operation of a memory array in which rewritable memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines, and data for the memory array. A test circuit including a data holding circuit provided in a signal path for inputting and outputting data is provided, and the address generating circuit and the data holding circuit are controlled by setting a test mode to externally test a part of the memory array. By writing a pattern and designating a test mode from the outside to the test circuit, the semiconductor memory device alone automatically performs a test according to the test pattern and the test mode by the test circuit.
The use time of the tester in the C test can be shortened, and an efficient test can be realized.

[Brief description of drawings]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM according to the present invention.

FIG. 2 is a main part block diagram for explaining a relationship between a main word line and a sub word line of the memory array of FIG. 1;

FIG. 3 is a main part block diagram for explaining a relationship between a main word line and a sense amplifier of the memory array of FIG. 1;

FIG. 4 is a main part circuit diagram showing one embodiment of a sense amplifier section of the dynamic RAM according to the present invention.

FIG. 5 is a schematic block diagram showing one embodiment of a peripheral portion of a dynamic RAM according to the present invention.

FIG. 6 is a schematic block diagram showing an embodiment of an SDRAM according to the present invention.

FIG. 7 is a block diagram showing another embodiment of a semiconductor memory device to which the present invention is applied.

FIG. 8 is a block diagram showing an embodiment of a microcomputer according to the present invention.

FIG. 9 is a flow chart diagram for explaining one embodiment of a method for testing a semiconductor memory device according to the present invention.

FIG. 10 is a simplified configuration diagram for explaining an inspection method by marching.

FIG. 11 is a schematic configuration diagram for explaining a method for testing a semiconductor memory device according to the present invention.

[Explanation of symbols]

SA, SA0, SA1 ... sense amplifier, SWD ... sub-word driver, MWD ... main word driver, ACT
RL ... Memory array control circuit, MWL0 to MWLn ... Main word line, SWL0 ... Sub word line, YS ... Column selection line, MMAT0, MMAT1 ... Memory mat (memory block), TG ... Timing control circuit, I / O ... Input / output circuit , RAB ... Row address buffer, CAB ... Column address buffer, AMX ... Multiplexer, RF
C: refresh address counter circuit, XPD, YP
D: Pre-tecoder circuit, X-DEC: Row system redundant circuit,
XIB: decoder circuit, Q1 to Q13: MOSFET,
CSP, CSN ... Common source line, YS ... Column selection signal, HVC ... Half precharge voltage, SHRL, SH
RR ... Shared selection line, I / O ... Input / output line, 200
A, 200B ... Memory array, 201A, 201B ... Row decoder, 202A, 202B ... Sense amplifier and column selection circuit, 203A, 203B ... Column decoder,
205 ... Column address buffer, 206 ... Row address buffer, 207 ... Column address counter, 208
… Refresh counter, 209… Address check &
Arithmetic unit, 210 ... Input buffer, 211 ... Output buffer, 212 ... Shift register, 213 ... Controller.
1 ... Row address buffer, 2 ... Column address buffer, 3 ... Row decoder, 4 ... Column decoder, 5 ... Sense amplifier & input / output line, 6 ... Memory array, 7 ... Input buffer, 8 ... Output buffer, 9 ... Arithmetic circuit 10 ... Input data control circuit, 11 ... Write control circuit, 12 ... Write address control circuit, 13 ... Address counter, 14 ... Serial column decoder, 15 ... Serial memory, 16 ...
Serial input buffer, 17 ... Serial output buffer,
18 ... Timing generating circuit, 19 ... Refresh counter, MCU ... Single chip microcomputer, C
PU ... Central processing unit, IBUS ... Internal bus, ROM ... Read-only memory, RAM ... Random access memory,
A / D ... Analog-digital conversion circuit, WDT ... Watchdog timer, TIM ... Timer circuit, SCI ... Serial communication interface, POR ... Power-on reset circuit, CLKC ... Clock controller, CLKG ... Clock generation circuit, XTAL ... Crystal oscillator.

Claims (6)

[Claims] 1. A memory array in which rewritable memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines, and an address generator for generating an address signal necessary for a selecting operation of the memory array. A circuit, a data holding circuit provided in a signal path for inputting and outputting data to and from the memory array, and controlling the address generating circuit and the data holding circuit by setting a test mode to form a part of the memory array. A semiconductor memory device comprising: a test circuit that performs an automatic test operation including a series of write and read operations on the memory array using a written test pattern. 2. The memory cell is a dynamic memory cell, and a part of the address generation circuit is shared with an X address counter of an internal automatic refresh control circuit. 1. The semiconductor memory device of 1. 3. The memory array is composed of two memory banks that constitute a synchronous dynamic RAM, and the address generation circuit includes an internal X address counter for automatic refresh and a Y address counter for burst mode. 2. The semiconductor memory device according to claim 1, wherein the test pattern is shared, and the test pattern is stored in one memory bank, and the test operation including the write and read operations is performed for the other memory bank. . 4. The test circuit compares an internally generated expected value containing the test pattern with a signal read by the read operation from a memory signal written by the write operation, and the comparison result is obtained by the above. 2. The semiconductor memory device according to claim 1, which has a function of storing data in a part of the memory array. 5. A memory array in which rewritable memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines, and an address generation circuit for generating an address signal necessary for a selection operation of the memory array. , A data holding circuit provided in a signal path for inputting and outputting data to and from the memory array, and controlling the address generating circuit and the data holding circuit by setting a test mode to write data in a part of the memory array. A first operation of externally writing the test pattern to a semiconductor memory device including a test circuit that performs an automatic test operation including a write operation and a read operation to and from the memory array using the existing test pattern; And a second operation for designating a test mode externally to the test circuit. Method of testing semiconductor memory device. 6. The burn-in is performed in the operating state in which the automatic test operation is executed after the second operation is designated and the external operation is executed to disconnect the first operation and the second operation. 6. The method of testing a semiconductor memory device according to claim 5, wherein.