JPH09245488A - Ferroelectric memory - Google Patents

Abstract

(57) [Summary] (Modified) [PROBLEMS] To prevent the bias and deterioration of the information retention characteristics of the ferroelectric capacitor due to imprinting, and to improve the reliability of the ferroelectric memory. SOLUTION: Two pairs of switching MOSFETs N8 and N9
And NA.NB or NC.ND and NE.NF, respectively, and non-inverting and inverting signal lines of the complementary bit lines of the memory array ARYL or ARYR and the sense amplifier SA.
Bit line connection switching circuits SL and SR formed of bit line inversion circuits capable of selectively non-inverting or inverting connection with the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit of
And a bit line switching state storage circuit for storing whether the connection between the complementary bit line and the unit amplifier circuit by these bit line connection switching circuits is non-inverting or inverting connection, and the refresh operation is performed. Each time the data is written, the data held in the memory cell is inverted and rewritten in word line units without changing its substantial logical value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory, for example, a shadow RAM (random access memory) that can be used in a volatile mode and a non-volatile mode, and a technique that is particularly effective when used for improving its reliability. Is.

[0002]

2. Description of the Related Art Ferroelectric capacitors and address selection M
A memory array in which ferroelectric-type memory cells including an OSFET (metal oxide semiconductor field-effect transistor; generically referred to as an insulated gate field-effect transistor in this specification) is arranged in a grid pattern is provided. There is a ferroelectric memory as its basic constituent element. Also,
Such a ferroelectric memory is operated in a volatile mode during normal operation with the plate potential of the ferroelectric capacitor and the precharge potential of the bit line as an intermediate potential between the power supply voltage VCC and the ground potential VSS. A so-called shadow RAM that operates in a non-volatile mode with the plate potential of the ferroelectric capacitor as the ground potential VSS is described in, for example, Japanese Patent Application Laid-Open No. 7-21784.

[0003]

In the shadow RAM described above, reading and writing of the held data in the volatile mode is performed by utilizing the electric charge accumulated in the interelectrode capacitance of the ferroelectric capacitor as it polarizes. Charge is
Similar to a normal dynamic RAM, leakage occurs over time, so refresh operation is required within a predetermined period.

On the other hand, as is well known, the information holding characteristic of a ferroelectric capacitor is a so-called because a pulse of the same polarity is applied between its electrodes during reading of held data including refresh operation and writing of the same data. Imbalance occurs due to imprint, or the amount of information decreases due to deterioration of the ferroelectric. This is a matter of course in a normal ferroelectric memory, and is a relatively serious problem particularly in a shadow RAM in which a refresh is performed at a predetermined cycle, which causes a decrease in its reliability.

An object of the present invention is to prevent imbalance / deterioration of information holding characteristics of a ferroelectric capacitor due to imprinting and improve reliability of the ferroelectric memory.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a ferroelectric memory, such as a shadow RAM, which can be used in a volatile mode and a non-volatile mode, has a memory array in which ferroelectric memory cells including a ferroelectric capacitor are arranged in a grid as a basic constituent element. For example, it includes two pairs of switching MOSFETs, and selectively non-inverts between the non-inverting and inverting signal lines of each complementary bit line of the memory array and the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit of the sense amplifier. Alternatively, a bit line inversion circuit capable of inverting connection and a switching state storage circuit for storing whether the connection between the complementary bit line and the unit amplifier circuit by these bit line inversion circuits is non-inverting or inverting connection are provided, For example, each time a refresh operation is performed, the data held in the memory cells is retained in word line units without changing the actual logical value. Rolling, and rewrite.

According to the above means, the polarity of the pulse applied between the electrodes of the ferroelectric capacitor can be inverted at a predetermined cycle even if the substantial logical value of the held data does not change. Prevents biased / degraded information retention characteristics of ferroelectric capacitors due to printing, shadow R
The reliability of AM and the like can be improved.

[0009]

FIG. 1 is a block diagram showing an embodiment of a shadow RAM (ferroelectric memory) to which the present invention is applied. 2 shows a partial circuit diagram of an embodiment of the memory array included in the shadow RAM of FIG. 1 and its peripheral portion, and FIG. 3 shows a ferroelectric circuit constituting the memory array of FIG. An information retention characteristic diagram of one embodiment of a body memory cell is shown. Based on these figures, first, the outline of the configuration and operation of the shadow RAM of this embodiment and the information retention characteristics of the ferroelectric memory cell will be described. The circuit elements of FIG. 2 and the circuit elements of each block of FIG. 1 are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique. In the circuit diagram below,
M with an arrow on the channel (back gate)
The OSFET is a P-channel type and is shown separately from an N-channel MOSFET without an arrow.

In FIG. 1, the shadow RA of this embodiment is shown.
M adopts a shared sense system and a pair of memory arrays ARYL and AR arranged on both sides of the sense amplifier SA.
YR and X provided corresponding to these memory arrays
Address decoders XDL and XDR are provided. Bit line connection switching circuits SL and SR are provided between the sense amplifier SA and the memory arrays ARYL and ARYR, respectively, and a Y address decoder YD is provided on the left side of the memory array ARYL.

The memory arrays ARYL and ARYR are so-called 2-cell / 2-transistor type arrays, and as shown in FIG. 2, m + 1 arranged in parallel in the vertical direction.
Book word lines WL0 to WLm or WR0 to WRm
And n + 1 sets of complementary bit lines BL0 * to BLn * or BR0 * to BRn * arranged in parallel in the horizontal direction.
(Here, for example, the non-inverted bit line BL0T and the inverted bit line BL0R are collectively denoted by an asterisk such as the complementary bit line BL0 *. Also, when it is enabled, it is selectively set to a high level. A so-called non-inverted signal or the like is indicated by adding T to the end of its name, and a so-called inverted signal or the like that is selectively brought to a low level when it is valid is added with B at the end of its name. The same shall apply hereinafter). At the intersections of these word lines and complementary bit lines, a total of (m + 1) × (n + 1) pairs of ferroelectric memory cells composed of ferroelectric capacitors Cp or Cn and address selection MOSFETs Qp or Qn are arranged in a grid pattern. .

One electrode of the ferroelectric capacitors Cp or Cn of the m + 1 pairs of memory cells arranged in the same column of the memory arrays ARYL and ARYR serves as an information storage node of the corresponding address selection MOSFET Qp or Q.
complementary bit lines BL0 * to BLn * or B
R0 * to BRn * are commonly coupled to non-inverted signal lines or inverted signal lines. The gates of the address selection MOSFETs Qp and Qn of the n + 1 pairs of memory cells arranged in the same row of the memory arrays ARYL and ARYR have corresponding word lines WL0 to WLm or WR0 to WRm.
Are commonly connected to each other. A predetermined plate voltage VP is commonly supplied to the other electrode, that is, the plate of the ferroelectric capacitors of all the memory cells forming the memory arrays ARYL and ARYR. The plate voltage V
P is an internal voltage HVC, that is, an intermediate potential between the power supply voltage VCC and the ground potential VSS when the power supply voltage is applied and the shadow RAM is in the volatile mode, and the power supply voltage is cut off and the shadow RAM is in the non-volatile mode. , Ground potential VSS, that is, 0V.

By the way, the memory arrays ARYL and AR
The ferroelectric memory cell forming the YR has information holding characteristics as shown in FIG. 3 in relation to the electric field applied between the electrodes of the ferroelectric capacitor and the polarization of the ferroelectric substance between the electrodes. . That is, the initial ferroelectric memory cell at the point A shifts its state to the point B when an electric field + Ep in the positive direction is applied, and the maximum polarization + Pp in the positive direction occurs. This polarization gradually decreases as the electric field becomes smaller, but polarization + Pr remains at point C where the electric field becomes zero. On the other hand, the polarization of the ferroelectric memory cell is reversed at the point D to which the electric field −Ec in the reverse direction is applied as a boundary, and the maximum polarization in the reverse direction −P at the point E to which the electric field −Ep is applied.
yields p. This polarization gradually decreases as the electric field becomes smaller, but at the point F where the electric field becomes 0, the polarization −P
r remains. Then, it makes a normal rotation with the point G to which the electric field + Ec in the positive direction is applied as a boundary, and reaches the point B.

In this embodiment, when the shadow RAM is set to the volatile mode, the internal voltage HVC, that is, the plate voltage VP at the intermediate potential is supplied to the plate of the ferroelectric capacitor which constitutes the ferroelectric memory cell. Also,
Complementary bit lines BL0 * to BLn * and BR0 * to BR forming the memory arrays ARYL and ARYR when the shadow RAM is brought into a non-selected state in the volatile mode.
The non-inverted and inverted signal lines of n * are precharged to the internal voltage HVC. Furthermore, when the read operation is performed in the volatile mode in the shadow RAM, the internal voltage HV
Complementary bit lines BL0 * to BLn precharged to C
The potentials of the non-inversion and inversion signal lines of * and BR0 * to BRn * are slightly increased or decreased by discharging the charge accumulated in the interelectrode capacitance of the ferroelectric capacitor of the selected memory cell. Then, such a minute read potential in the non-inversion and inversion signal lines of the complementary bit line is
As will be described later, each is amplified by the corresponding unit amplifier circuit of the sense amplifier SA and becomes a high level or low level binary read signal.

In other words, when the read operation in the volatile mode is performed in the shadow RAM of this embodiment, the polarization states of the ferroelectric capacitors of the selected memory cell are complementary bit lines BL0 * to BLn * and BR0 *. ˜BRn * non-inverted and inverted signal lines reciprocate between point C or point F in FIG. 2 in the precharged state to point B corresponding to the high level after amplification or point E corresponding to the low level after amplification. However, the polarization inversion accompanying the read operation does not occur. Therefore, it is possible to reduce the number of times of rewriting of the ferroelectric memory cell per time, and thereby to prolong the service life of the ferroelectric memory.

On the other hand, when the same data is written in the volatile mode in the shadow RAM, that is, the non-inverted write operation is performed, the polarization state of the ferroelectric capacitor of the selected memory cell is the same as in the read operation, and the complementary bit line BL is used.
0 * to BLn * and BR0 * to BRn * have non-inverted and inverted signal lines in a precharged state from point C or point F in FIG. 2 to point B corresponding to the high level after amplification or point E corresponding to the low level. However, no polarization reversal associated with the write operation occurs. However, when writing data of different logical values, that is, inversion writing operation, the polarization state of the ferroelectric capacitor of the selected memory cell shifts from point C to point E or from point F to point B, respectively, and the polarization inversion is performed. It will be accompanied.

Returning to the explanation of FIG. The bit line connection switching circuit SL includes complementary bit lines B of the memory array ARYL.
There are provided n + 1 bit line inversion circuits provided corresponding to L0 * to BLn *, and each of these bit line inversion circuits includes non-inversion and inversion signal lines of complementary bit lines BL0 * to BLn * and a sense amplifier SA. Of the corresponding unit amplifier circuit of the non-inverting input / output nodes BS0T to BSnT and the inverting input / output nodes BS0B to BSnB or the inverting input / output nodes BS0B to BSnB and the non-inverting input / output node B.
It includes two pairs of N-channel type switching MOSFETs N8 and N9 and NA and NB provided respectively between SOT and BSnT. Of these, switching MOSF
A shared control signal SHTL is commonly supplied from the bit line switching control circuit BLCC described later to the gates of ETN8 and N9, and a shared control signal SHBL from the bit line switching control circuit BLCC is commonly supplied to the gates of the switching MOSFETs NA and NB. Supplied.

As a result, the shared control signal SHTL is set to the high level and the switching MOSFETs N8 and N of the bit line connection switching circuit SL are applied to the non-inverted and inverted signal lines of the complementary bit lines B0 * to Bn * of the memory array ARYL.
When 9 is turned on, the non-inverting input / output nodes BS0T to BSn of the corresponding unit amplifier circuit of the sense amplifier SA are
Non-inverted connection to T and inverted input / output nodes BS0B to BSnB, shared control signal SHBL is set to high level, and switching MOSF of bit line connection switching circuit SL is switched.
When ETNA and NB are turned on, the inverted input / output nodes BS0B to BSnB and the non-inverted input / output node BS0 of the corresponding unit amplifier circuit of the sense amplifier SA.
It will be connected in reverse to T to BSnT.

Similarly, the other bit line connection switching circuit SR includes complementary bit lines BR0 * of the memory array ARYR.
To BRn * provided with n + 1 bit line inversion circuits, and each of these bit line inversion circuits corresponds to the non-inversion and inversion signal lines of the complementary bit lines BR0 * to BRn * and the sense amplifier SA. The non-inverting input / output nodes BS0T to BSnT and the inverting input / output nodes BS0B to BSnB or the inverting input / output nodes BS0B to BSnB and the non-inverting input / output node BS0 of the unit amplifier circuit
It includes two pairs of N-channel type switching MOSFETs NC and ND and NE and NF which are respectively provided between T and BSnT. Of these, switching MOSFET
The shared control signal SHTR is commonly supplied from the bit line switching control circuit BLCC to the gates of NC and ND, and the shared control signal SHBR is commonly supplied to the gates of the switching MOSFETs NE and NF.

As a result, in the non-inverted and inverted signal lines of the complementary bit lines BR0 * to BRn * of the memory array ARYR, the shared control signal SHTR is set to the high level, and the switching MOSFET NC of the bit line connection switching circuit SL.
And ND are turned on, the non-inverting input / output node BS0T of the corresponding unit amplifier circuit of the sense amplifier SA
BSnT and inverted input / output nodes BS0B to BSnB
And the shared control signal SHBR is set to the high level to switch the bit line connection switching circuit SR to the switching M.
When the OSFET NE and NF are turned on,
Inverted input / output nodes BS0B to BSnB and non-inverted input / output nodes BS0T to BSnT of the corresponding unit amplifier circuit of the sense amplifier SA are inversely connected. The high level of the shared control signals SHTL, SHBL, SHTR, and SHBR is a high voltage VCH higher than the power supply voltage VCC by at least the threshold voltage of the MOSFETs N8 to NF, as will be described later. The threshold voltage does not lower the signal level of each complementary bit line. Further, as is clear from the above description, the bit line connection switching circuits SL and S
MOSFETs N8 to NB and NC to N forming R
F is a shared MOS for so-called shared sense
Since it is also used as an FET, the shadow RAM is provided by providing the bit line connection switching circuits SL and SR.
The increase in chip size is small.

The sense amplifier SA is a memory array ARY.
N provided corresponding to complementary bit lines of L and ARYR
+1 unit circuits, each of which includes a P-channel MOSFET P1 and an N-channel M
OSFET N1 and P-channel MOSFET P2
And a pair of CM composed of N-channel MOSFET N2
A unit amplifier circuit in which OS (complementary MOS) inverters are cross-coupled, and a pair of N-channel type switches MO
SFETs N3 and N4 and three N-channel MOSF
And a bit line precharge circuit in which ETN5 to N7 are connected in series and parallel. Of these, the sources of the P-channel MOSFETs P1 and P2 forming the unit amplifier circuit are
Commonly connected to common source line CSP, N channel M
The sources of the OSFETs N1 and N2 are the common source line C
Commonly connected to SN. Also, MOSFETs P1 and N
One commonly coupled drain as well as MOSFET P2
And N2 are commonly coupled gates of non-inverting input / output nodes BS0T to BSnT of each unit amplifier circuit, and the commonly coupled gates of MOSFETs P1 and N1 and the commonly coupled drains of MOSFETs P2 and N2 are respectively coupled to each unit. It becomes the inverting input / output nodes BS0B to BSnB of the amplifier circuit.

As a result, the unit amplifier circuits of the unit circuits of the sense amplifier SA are connected to the common source lines CSP and CSN.
Is supplied with the power supply voltage VCC or the ground potential VSS via the memory cells to be selectively and simultaneously activated to correspond to n + 1 pairs of memory cells coupled to the selected word line of the memory array ARYL or ARYR. The minute read signals output to the complementary input / output nodes BS0 * to BSn * via the complementary bit lines BL0 * to BLn * or BR0 * to BRn * are respectively amplified to be a high level or low level binary read signal. To do.

The drains of the switch MOSFETs N3 and N4 forming each unit circuit of the sense amplifier SA have non-inverting input / output nodes BS0T to BS of the corresponding unit amplifier circuit.
nT or inverted input / output nodes BS0B to BSnB. The source is the non-inverted common data line C.
Each of them is commonly coupled to the DT or the inverted common data line CDB, and the corresponding bit line selection signals YS0 to YSn are supplied to the commonly coupled gates from the Y address decoder YD.

As a result, the complementary input / output nodes BS0 * to BSn * of each unit amplifier circuit of the sense amplifier SA receive the high level of the corresponding bit line selection signals YS0 to YSn, and are selectively complementary common data lines CD. It is connected to * and selectively connected to a main amplifier MA described later through the complementary common data line.

An internal control signal PC is commonly supplied from a clock generation circuit CG, which will be described later, to the gates of the MOSFETs N5 to N7 constituting the bit line precharge circuit of each unit circuit of the sense amplifier SA, and the MOSFETs N6 and N6.
A predetermined precharge voltage VC is commonly supplied to the commonly coupled sources of 7. The internal control signal PC
Is at a high level such as the power supply voltage VCC when the shadow RAM is in the non-selected state, and is at a low level such as the ground potential VSS at a predetermined timing when the shadow RAM is in the selected state. Further, as will be described later, the precharge voltage VC is the power supply voltage VCC when the shadow RAM is in the normal operation state in the volatile mode.
And an intermediate potential between the ground potential VSS and the internal voltage HVC
When the shadow RAM is set to the recall mode for conversion to the volatile mode, it is temporarily set to the low level like the ground potential VSS at a predetermined timing.

As a result, the complementary input / output nodes BS0 * to BSn * of each unit amplifier circuit of the sense amplifier SA, that is, the complementary bit lines BL of the memory arrays ARYL and ARYR.
0 * to BLn * and BR0 * to BRn * are precharged to the internal voltage HVC when the shadow RAM is in the non-selected state of the volatile mode, and when the shadow RAM is set to the recall mode, the ground potential is set at a predetermined timing. It will be precharged to a low level like VSS. The specific operation of the shadow RAM in the recall mode will be described later in detail.

Returning to FIG. The word lines WL0 to WLm of the memory array ARYL and the word lines WR0 to WRm of the memory array ARYR are coupled to the corresponding X address decoder XDL or XDR under the word lines, and are alternatively selected. To the X address decoders XDL and XDR, i-bit internal address signals X0 to Xi-1 excluding the most significant bit are commonly supplied from the X address latch XL, and the clock generation circuit CG supplies the internal control signal X.
GL and XGR are respectively supplied. In addition, the X address latches XL include X address signals AX0 to AX from the address input terminals A0 to Ai via the address buffer AB.
Xi is supplied in a time division manner, and refresh address signals RX0 to RX are supplied from the refresh counter RFC.
Xi is supplied. The X address latch XL is further supplied with internal control signals RF and XL from the clock generation circuit CG, and the refresh counter RFC is supplied with an internal control signal RC (not shown) from the clock generation circuit CG.

When the shadow RAM is in the refresh mode, the refresh counter RFC performs a step operation according to the internal control signal RC supplied from the clock generation circuit CG, and refresh address signals RX0 to RX.
i is formed and supplied to the X address latch XL. When the shadow RAM is in the normal operation mode and the internal control signal RF is at low level, the X address latch XL is
Address buffer AB from address input terminals A0 to Ai
X address signals AX0 to AX0 input in a time division manner via
AXi is fetched and held according to the internal control signal XL. When the shadow RAM is set to the refresh mode and the internal control signal RF is set to the high level, the refresh address signals RX0 to RXi supplied from the refresh counter RFC are fetched and held according to the internal control signal XL. Then, these X address signals AX0 to AXi or the refresh address signal RX
Internal address signals X0 to Xi are formed based on 0 to RXi. Of these, the most significant bit internal address signal X
i is supplied to the clock generation circuit CG and the bit line switching control circuit BLCC, and other internal address signals X
0 to Xi-1 are X address decoders XDL and XDR
Supplied in common.

The X address decoders XDL and XDR are
Receiving the high level of the internal control signal XGL or XGR, they are selectively brought into the operating state, and the X address latch XL
The internal address signals X0 to Xi-1 supplied from the above are decoded to selectively set the corresponding word line of the memory array ARYL or ARYR to the high level.

The Y address decoder YD has an i + 1 bit internal address signal Y0 to Y1 from the Y address latch YL.
Yi is supplied, and the internal control signal YG is supplied from the clock generation circuit CG. The Y address latches YL are time-divisionally supplied with Y address signals AY0 to AYi from the address input terminals A0 to Ai via the address buffer AB, and the internal control signal Y from the clock generation circuit CG.
L is supplied.

The Y address latch YL is a shadow RAM
Are selected, the address input terminals A0 to Ai
Fetches and holds the Y address signals AY0 to AYi supplied in a time division manner through the address buffer AB according to the internal control signal YL, and forms the internal address signals Y0 to Yi based on these Y address signals. And supplies it to the Y address decoder YD. Further, the Y address decoder YD receives the high level of the internal control signal YG and is selectively brought into an operating state, and the internal address signal Y0
To Yi are decoded, and the corresponding bits of the bit line selection signals YS0 to YSn to be supplied to the sense amplifier SA are alternatively set to the high level.

The complementary common data line CD * is coupled to the main amplifier MA on the other side, and the main amplifier M is connected to the main amplifier MA.
A includes a write amplifier and a read amplifier. Of these, the input terminal of the write amplifier is coupled to the output terminal of the input buffer IB, and the output terminal is connected to the complementary common data line CD.
Combined with *. The input terminal of the read amplifier is coupled to the complementary common data line CD *, and the output terminal is coupled to the input terminal of the output buffer OB. Input buffer IB
Is coupled to the data input terminal Din, and the output terminal of the output buffer OB is coupled to the data output terminal Dout. The write amplifier of the main amplifier MA is supplied with the internal control signal WC from the clock generation circuit CG, and the output buffer OB is supplied with the internal control signal OC.

The input buffer IB fetches the write data input through the data input terminal Din when the shadow RAM is selected in the write mode,
It is transmitted to the write amplifier of the main amplifier MA. At this time, the write amplifier of the main amplifier MA is selectively activated by receiving the high level of the internal control signal WC, converts the write data transmitted from the input buffer IB into a predetermined complementary write signal, and then complements it. Common data line CD
* To the memory array ARYL via the sense amplifier SA
Alternatively, write to one selected ferroelectric memory cell of ARYR.

On the other hand, the read amplifier of the main amplifier MA, when the shadow RAM is selected in the read mode, selects from one selected ferroelectric memory cell of the memory array ARYL or ARYR, the sense amplifier SA and the complementary common. The read signal output via the data line CD * is further amplified and transmitted to the output buffer OB. At this time, the output buffer OB is selectively operated in response to the high level of the internal control signal OC, and outputs the read signal transmitted from the read amplifier of the main amplifier MA from the data output terminal Dout to the outside of the shadow RAM. To do.

The clock generation circuit CG is supplied from the X address latch XL and the row address strobe signal RASB, the column address strobe signal CASB, the write enable signal WEB and the output enable signal OEB which are supplied as the activation control signal from the external access device. The various internal control signals and the like are selectively formed on the basis of the internal address signal Xi of the most significant bit to be supplied to each unit. In addition, the mode switching circuit MC receives the mode control signals MOD0 and MOD1 to selectively determine the operation mode of the shadow RAM, and the internal signal VOM corresponding to the volatile mode and the internal signal STRM corresponding to the store mode.
In addition, the internal signal RECM corresponding to the recall mode is selectively set to the high level. These internal signals VOM,
STRM and RECM are supplied to each part of the shadow RAM.

The shadow RAM of this embodiment further includes
It includes a bit line switching control circuit BLCC and a bit line switching state storage circuit BLCM (switching state storage circuit). The bit line switching control circuit BLCC has an internal address signal Xi of the most significant bit from the X address latch XL.
, The clock control circuit CG supplies the internal control signal SH, and the bit line switching state storage circuit BLCM supplies the complementary internal signal BLS *. The bit line switching state storage circuit BLCM stores the switching state of complementary bit lines by the bit line connection switching circuits SL and SR, and the bit line switching control circuit BLC.
C is a shared control signal S based on the internal address signal Xi, the internal control signal SH, and the complementary internal signal BLS *.
HTL, SHBL, SHTR, and SHBR are selectively formed to control the bit line inversion switching operation by the bit line connection switching circuits SL and SR. Specific configurations of the bit line switching control circuit BLCC and the bit line switching state storage circuit BLCM and the bit line inversion switching operation will be described in detail later.

FIG. 4 is a conceptual diagram of an embodiment for explaining the operation mode of the shadow RAM of FIG. Further, FIG. 5 is a circuit diagram of an embodiment of the bit line switching state storage circuit BLCM and the bit line switching control circuit BLCC included in the shadow RAM of FIG.
FIG. 6 shows an operation condition diagram of one embodiment of the bit line switching control circuit BLCC of FIG. Further, FIGS. 7 and 8 show signal waveform diagrams of one embodiment of the write operation and the read operation in the volatile mode of the shadow RAM of FIG. 1, respectively, and FIGS. 9 and 10 show the refresh mode. Signal waveform diagrams of one embodiment of the inversion rewriting operation for the first word line and the last word line are shown. In addition, FIG. 11 shows a signal waveform diagram of one embodiment of the inversion repair operation for the final word line using the store mode of the shadow RAM of FIG.
4 shows a signal waveform diagram of an embodiment of the conversion operation to the volatile mode by the recall mode. Based on these figures, the specific configurations of the bit line switching state storage circuit BLCM and the bit line switching control circuit BLCC included in the shadow RAM of this embodiment, the outline of each operation mode of the shadow RAM, and the features of the shadow RAM are described. explain.

In FIG. 4, the shadow RA of this embodiment is shown.
When the power supply voltage is turned on, M operates in the volatile mode using the accumulated charge of the interelectrode capacitance of the ferroelectric capacitor, like the normal dynamic RAM, and when the power supply voltage is turned off, It operates in a non-volatile mode using the polarization of the dielectric capacitor. The shadow RAM access device normally sets both the mode control signals MOD0 and MOD1 to low level to set the shadow RAM internal signal VOM to high level, and sets the shadow RAM to the volatile mode. Immediately before the power supply voltage is cut off, the mode control signals MOD0 and MOD1 are set to the high level and the low level, respectively, and the internal signal STRM is set to the high level, and the shadow RAM is set to the store mode. Further, when the power supply voltage is turned on again, first the mode control signals MOD0 and MOD1 are set to low level and high level, respectively, the internal signal RECM is set to high level, the shadow RAM is temporarily set to the recall mode, and then the volatile mode is entered. .

When the shadow RAM is set to the volatile mode, the ferroelectric memory cells forming the memory arrays ARYL and ARYR are used in a region where polarization inversion does not occur except during inversion writing, as described above. The charges accumulated in the interelectrode capacitance of the dielectric capacitor gradually leak through the PN junction portion of the source region of the address selection MOSFET. For this reason, a refresh operation for reading and rewriting the data held in the memory cell in units of word lines at a predetermined cycle tref according to the leak characteristic of the ferroelectric capacitor is required. However, in the shadow RAM of this embodiment. , At least a memory array ARYL or AR
Word lines WL0 to WLm or WR0 forming YR
A series of refresh operations for WRm to WRm are continuously executed, and the data held in each memory cell is inverted and rewritten. Shadow RA including inversion rewriting
The specific operation of M will be described later.

As shown in FIG. 5, the bit line switching state storage circuit BLCM of the shadow RAM has flip-flops for receiving internal control signals BLC and RST from a preceding circuit (not shown) at its trigger input terminal T and reset input terminal R, respectively. Includes BLCF. The bit line switching control circuit BLCC receives an internal address signal Xi of the most significant bit and selectively forms array selection signals ASL and ASR, and an array selection circuit ASLC and a NOR (N
OR) gates NO1 and NO2 or NO3 and NO
And 4 latches, 4 each being cross-coupled. The NOR gates NO1 to NO4 are connected to the power supply voltage VC.
A predetermined high voltage VCH, which is higher than C by at least the threshold voltage of the address selection MOSFET forming the ferroelectric memory cell, is used as an operating power source, and its output signal, that is, shared control signals SHTL, SHBL, SHTR and SH.
The high level of BR is the high voltage VCH.

A NAND gate NA1 is provided at the first input terminal of the NOR gate NO1 and the second input terminal of the NOR gate NO2 of the bit line switching control circuit BLCC.
Of the output signal of the inverter V1, that is, the inverted internal signal SHLB is commonly supplied to the NOR gate NO3.
Of the output signal of the NAND gate NA2 to the first input terminal of the NOR gate NO2 and the second input terminal of the NOR gate NO4.
The inversion signal by 2, that is, the inversion internal signal SHRB is commonly supplied. The second of the NOR gates NO1 and NO3
Of the bit line switching state storage circuit BLC
The non-inverted output signal of the flip-flop BLCF forming the M, that is, the non-inverted internal signal BLST is commonly supplied, and the inverted output signal thereof, that is, the inverted internal signal BLSB is commonly supplied to the third input terminals of the NOR gates NO2 and NO4. To be done. An array selection signal ASL is supplied from the array selection circuit ASLC to one input terminal of the NAND gate NA1, and an array selection signal ASR is supplied to one input terminal of the NAND gate NA2. The clock generation circuit CG is connected to the other input terminals of the NAND gates NA1 and NA2.
The internal control signal SH is supplied in common. The output signals of the NOR gates NO1, NO2, NO3 and NO4 are
The shared control signals SHTL, SHBL, SHTR and SHBR are supplied to the sense amplifier SA.

The flip-flop BLCF of the bit line switching state memory circuit BLCM is brought into a reset state in response to the rise of the internal control signal RST to a high level,
In response to the rising of the internal control signal BLC, the state is alternately inverted from the reset state to the set state or from the set state to the reset state.

On the other hand, the bit line switching control circuit BLCC
Array select circuit ASLC selectively sets the array select signal ASL corresponding to the memory array ARYL to the high level when the internal address signal Xi is set to the low level, and the memory array ARYR when the internal address signal Xi is set to the high level. The array selection signal ASR corresponding to is selectively set to the high level. The internal control signal SH is
When the shadow RAM is in the non-selected state, it is at the low level, and when it is in the selected state, it is at the high level at a predetermined timing. Further, when the shadow RAM is in the non-selected state, both array selection signals ASL and ASR are set to the low level.

From the above, when the flip-flop BLCF of the bit line switching state memory circuit BLCM is in the reset state, that is, the state in which the bit line inversion is not performed and the shadow RAM is in the non-selected state, the non-inversion internal signal BL is set.
ST, internal control signal SH and array selection signal ASL
As shown in FIG. 6, both ASR and ASR are at low level (L), and the inverted internal signal BLSB is at high level (H). Therefore, the shared control signal SHTL
And SHTR are both set to a high level such as high voltage VCH, and shared control signals SHBL and SHBR are both set to a low level such as ground potential VSS. When the shadow RAM is in the non-selected state, the flip-flop BLCF of the bit line switching state memory circuit BLCM is in the set state, that is, the state in which the bit line inversion is performed,
The non-inverted internal signal BLST changes to high level, and the inverted internal signal BLSB changes to low level. Therefore,
Shared control signals SHTL and SHTR are both set to low level, and shared control signals SHBL and SHBR are set to high level of high voltage VCH.

Next, the bit line switching state storage circuit BL
When the shadow RAM is selected and the internal control signal SH is set to the high level while the CM flip-flop BLCF is in the reset state, that is, the bit line inversion is not performed, the shared control signals SHTL and SHTR are set to the memory arrays ARYL and ARYR. One of them selectively changes to a low level according to the selected state of. That is, when the memory array ARYL is designated and the array selection signal ASL is set to the high level, the shared control signal SHTR corresponding to the memory array ARYR is set to the low level, and the shared control signal SHTL corresponding to the memory array ARYL remains at the high level. It is said that When the memory array ARYR is designated and the array selection signal ASR is set to the high level, the shared control signal SHTL corresponding to the memory array ARYL is set to the low level, and the shared control signal SHTR corresponding to the memory array ARYR remains at the high level. It is said that Similarly, the bit line switching state storage circuit BL
When the shadow RAM is selected and the internal control signal SH is set to the high level while the CM flip-flop BLCF is set, that is, the bit line inversion is performed, the memory array ARYL is designated and the array selection signal ASL is set to the high level. Then, the shared control signal SHBR is set to the low level and the shared control signal SHBL is kept at the high level. When the memory array ARYR is designated and the array selection signal ASR is set to the high level, the shared control signal SHBL is set to the low level and the shared control signal SHBR corresponding to the memory array ARYR is kept at the high level.

When the row address strobe signal RASB is set to the high level and the shadow RAM is in the non-selected state of the volatile mode, the clock generation circuit CG, as shown in FIG. 7, the internal control signal PC for the sense amplifier SA.
To high level. Further, the flip-flop BLCF of the bit line switching state memory circuit BLCM is in a reset state as an initial state, for example, its non-inverted output signal, that is, non-inverted internal signal BLST is set to low level, and its inverted output signal, that is, inverted internal signal BLSB is High level. Shared control signals SHTL and SHTR
Receives the low level of the non-inverted internal signal BLST and the internal control signal SH (not shown), and both are set to the high level like the high voltage VCH, and the shared control signals SHBL and SBL.
The HBR receives the high level of the inverted internal signal BLSB and is set to the low level like the ground potential VSS. As a result, each unit circuit of the sense amplifier SA receives the high level of the internal control signal PC and receives the precharge MOS.
The FETs N5 to N7 are turned on all at once. In addition, complementary bit lines BL0 * of the memory arrays ARYL and ARYR
.About.BLn * and BR0 * to BRn * receive the high levels of the shared control signals SHTL and SHTR, are non-invertedly connected to the corresponding unit amplifier circuits of the sense amplifier SA, and are precharged to the internal voltage HVC.

Next, the shadow RAM is selectively brought into a selected state in response to the low level of the row address strobe signal RASB. To the address input terminals A0 to Ai, in synchronization with the fall of the row address strobe signal RASB, the X address signals AX0 to AX0 to specify the word line WL0 of the memory array ARYL, that is, the row address ra0.
AXi is supplied and column address strobe signal CA
In synchronization with the falling edge of SB, the bit line selection signal YS0
That is, Y address signals AY0 to AYi are supplied to specify the column address ca0. The write enable signal WEB is set to the low level in synchronization with the fall of the column address strobe signal CASB, and the write data wd is supplied to the data input / output terminal Din.

In the shadow RAM, first, the internal control signal PC is set to the low level in response to the fall of the row address strobe signal RASB, and the precharge operation by the bit line precharge circuit of the sense amplifier SA is stopped. Further, the internal control signal SH (not shown) is set to the high level, and only the shared control signal SHTR corresponding to the unspecified memory array ARYR is set to the low level.
As a result, the complementary bit lines BR0 * to BRn * forming the memory array ARYR are disconnected from the non-inverted connection with the corresponding unit amplifier circuit of the sense amplifier SA, and are brought into a floating state. In the shadow RAM, the word line WL0 of the memory array ARYL designated at a predetermined timing is alternatively set to a selection level such as the high voltage VCH, and the complementary bit lines BL0 * to BLn * have word lines WL0. A minute read signal corresponding to the accumulated charge of the inter-electrode capacitance of the n + 1 pairs of ferroelectric memory cells coupled to is complementarily output. These minute read signals are supplied with the power supply voltage VCC to the common source line CSP and the ground potential VSS to the common source line CSN,
The signal is amplified by the corresponding unit amplifier circuit of the sense amplifier SA, and becomes a high level or low level binary read signal.

On the other hand, the column address strobe signal CA
When SB is set to the low level, in the shadow RAM, the bit line selection signal YS0 corresponding to the column address ca0.
Is alternatively set to the high level, and after a slight delay, the internal control signal WC for the write amplifier of the main amplifier MA is set to the high level. The sense amplifier SA receives the high level of the bit line selection signal YS0 and receives the memory array ARYL.
Corresponding complementary bit line BL0 * is complementary common data line C
Connected to D *. Further, the complementary common data line CD * is supplied with a write signal corresponding to the write data wd from the write amplifier of the main amplifier MA in response to the high level of the internal control signal WC. As a result, the binary read signal established on the complementary bit line BL0 * is inverted, for example, to correspond to the write data wd, and the ferroelectric memory cells of the pair of ferroelectric memory cells directly coupled to the intersection with the word line WL0. It is written in the inter-electrode capacitance of the body capacitor with polarization reversal. In the other complementary bit lines BL1 * to BLn *, the binary read signals established on the non-inverted and inverted signal lines are directly applied to the word line WL0.
The inter-electrode capacitance of the ferroelectric capacitors of the remaining n pairs of ferroelectric memory cells arranged at the intersection with
As described above, these rewritings are not accompanied by the polarization reversal of the ferroelectric capacitor.

Next, referring to FIG. 8, the read operation of the shadow RAM in the volatile mode will be described. Note that the read operation in the volatile mode has many of the same parts as the write operation of FIG. 7, and therefore only the parts different from this will be described.

In the shadow RAM shown in FIG. 8, the bit line selection signal YS0 is alternatively set to the high level in response to the fall of the column address strobe signal CASB, and the internal control signal OC to the output buffer OB is set to the high level with a slight delay. It is a level. In the sense amplifier SA, in response to the high level of the bit line selection signal YS0, the corresponding complementary bit line BL0 * of the memory array ARYL is connected to the complementary common data line CD *, and the non-inverted and inverted signal lines thereof are established. The binary read signal is output to the read amplifier of the main amplifier MA via the complementary common data line CD *. The binary read signal is further amplified by the read amplifier of the main amplifier MA, and then the internal control signal OC is set to a high level, and is output from the output buffer OB to the external access device via the data output terminal Dout. To be done. The complementary bit lines BL0 * to BLn *
The binary read signals established on the non-inversion and inversion signal lines of n are directly arranged at the intersection of the word line WL0 and n +.
The capacitance between the electrodes of the ferroelectric capacitors of the pair of ferroelectric memory cells is rewritten.

By the way, when the shadow RAM operates in the volatile mode, the charge accumulated in the interelectrode capacitance of the ferroelectric capacitors of the ferroelectric memory cells forming the memory arrays ARYL and ARYR is as described above. Since the leak gradually occurs via the PN junction part of the address selection MOSFET Qp or Qn, it is necessary to repeat the refresh operation of the held data with a cycle tref of, for example, about 64 ms (milliseconds). Further, in these refresh operations, rewriting to the ferroelectric memory cell is performed in the same manner as in the case of the above reading operation, but these rewriting operations are not accompanied by polarization reversal of the ferroelectric capacitor, but As a result, pulses of the same polarity are repeatedly applied between the electrodes of the capacitors, which causes imbalance or deterioration of the information retention characteristics of the ferroelectric memory cell due to imprinting.

In order to deal with this, in the shadow RAM of this embodiment, as shown in FIG. 4, the data held in the ferroelectric memory cell is forcibly inverted and rewritten in units of word lines during the refresh operation. By performing the inversion rewriting, the application of the pulse of the same polarity to the ferroelectric capacitor is prevented. At this time, the flip-flop BLC of the bit line switching state storage circuit BLCM
F is a complementary bit line BL0 * to BLn * or BR0 * to BRn * of the memory array ARYL or ARYR and the non-inverting input / output nodes BS0T to BSnT and the inverting input / output node B of the corresponding unit amplifier circuit of the sense amplifier SA.
It serves to remember whether the connection between S0B and BSnB is in a non-inverting or inverting connection. Further, in the shadow RAM of this embodiment, as described above, a series of refresh operations on at least m + 1 word lines WL0 to WLm or WR0 to WRm of the memory array ARYL or ARYR are continuously executed, and during the refresh operation. Care is taken not to invert the connection state between the complementary bit line and the sense amplifier.

Therefore, the flip-flop BLCF of the bit line switching state storage circuit BLCM includes the word lines WL0 to WLm-1 and WR0 except the final word line.
The original set state or reset state is returned to the original state when the refresh operation for WRm-1 is completed, but it is not returned to the original state when the refresh operation for the last word line WLm or WRm is completed. As a result, the data held in the ferroelectric memory cell is physically inverted by the inversion rewriting, but its substantial logical value is not changed.

On the other hand, the bit line switching state storage circuit BL
The flip-flop BLCF forming the CM is, so to speak, a volatile memory.
It disappears when the power supply voltage of the shadow RAM is cut off. For this reason, in this embodiment, immediately before the power supply voltage of the shadow RAM is connected, the store mode for returning the connection between the memory array and the sense amplifiers to the initial state, that is, the non-inverted connection state is executed for all the word lines. Is specified as the specification. 9 and 10, the memory array ARYL in the refresh mode will be described below.
The inversion rewriting operation for the first word line WL0 and the final word line WLm will be described, and the inversion repair operation for the final word line WLm of the memory array ARYL in the store mode will be described with reference to FIG. Note that the store mode is executed regardless of the state of the flip-flop BLCF of the bit line switching state storage circuit BLCM just before the power supply voltage is cut off in order to unify the specifications.
The AM selectively executes the inversion repair operation only when the flip-flop BLCF is in the set state, that is, when the connection between the memory array and the sense amplifier is in the inverted connection state.

In FIG. 9, when the shadow RAM is in the non-selected state, the bit line switching state storage circuit BLC
The flip-flop BLCF of M is reset, for example, and its non-inverted and inverted output signals, that is, the non-inverted internal signal BLST and the inverted internal signal BLSB are set to the low level and the high level, respectively. Further, in response to the low level of the internal control signal SH (not shown), the shared control signals SHTL and SHTR are both set to the high level like the high voltage VCH, and the shared control signals SHBL and SBL are set.
Both HBR are set to low level.

In the shadow RAM, the column address strobe signal CASB is the row address strobe signal RAS.
Low level before B, so-called CB
Starts R refresh operation. At this time, the X address signal for designating the word line is not input to the address input terminals A0 to Ai, and the word line to be refreshed is refreshed by the refresh address signals RX0 to RXi output from the refresh counter RFC. Autonomously specified by

In the shadow RAM, the internal control signal PC is first set to the low level in response to the fall of the row address strobe signal RASB, and the shared control signal SHTR is set to the high level of the internal control signal SH and the array selection signal ASL (not shown). Accordingly, the shared control signal SHTL is kept at the high level. In addition, the refresh address signal RX is slightly delayed.
For example, the word line WL0 designated by 0 to RXi is alternatively set to the selection level of the high voltage VCH, and the power supply voltage VCC and the ground potential VSS are supplied to the common source lines CSP and CSN after a short delay. The internal control signal BLC serving as a trigger signal for the flip-flop BLCF of the bit line switching state storage circuit BLCM is 2 in the complementary bit lines BL0 * to BLn * of the memory array ARYL.
It is temporarily set to a high level at a predetermined timing when the logical value of the value read signal will be established. Then, the row address strobe signal RASB and the column address strobe signal CASB are returned to the high level and the shadow R
When AM is deselected, the internal control signal PC is first returned to the high level and the flip-flop BL is slightly delayed.
The internal control signal BLC for CF is temporarily set to the high level again.

As a result, the non-inverting and inverting signal lines of the complementary bit lines BL0 * to BLn * of the memory array ARYL are non-inverting connected to the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit of the sense amplifier SA. Word line WL
Small read signals of n + 1 pairs of ferroelectric memory cells coupled to 0 are used as binary read signals and complementary bit lines BL
Established on 0 * -BLn * respectively. Further, when the logical value of the binary read signal is determined, the internal control signal BL
When C is temporarily set to the high level, the flip-flop BLCF of the bit line switching state memory circuit BLCM is inverted from the set state to the reset state, and its non-inverted and inverted output signals, that is, the non-inverted internal signal BLST and the inverted internal signal. The level of BLSB is inverted. Therefore, the shared control signal SHTL becomes low level, the shared control signal SHBL becomes high level, and the memory array A
The connection between the complementary bit lines BL0 * to BLn * of RYL and the complementary input / output node of each unit amplifier circuit of the sense amplifier SA is switched to the inverting connection. As a result, the memory array A
In the n + 1 pair of ferroelectric memory cells coupled to the RYL word line WL0, data having a logical value opposite to the held data up to now is rewritten all at once, and an inversion rewriting operation is realized.

When the shadow RAM is deselected,
First, the internal control signal PC is returned to the high level, and the precharge operation of the complementary bit lines BL0 * to BLn * of the memory array ARYL is restarted. Also, the shared control signal S
The HTR is set to the high level, the complementary bit lines BR0 * to BRn * of the memory array ARYR are also connected to the corresponding unit circuits of the sense amplifier SA, and undergo the precharge operation by the bit line precharge circuit. Then, when the internal control signal BLC is temporarily set to the high level again, the flip-flop BLCF of the bit line switching state storage circuit BLCM is returned to the reset state, and the internal signals BLST and BLSB are returned to the low level and the high level, respectively. . As a result, the connection between the memory array and the sense amplifier is returned to the state before the start of the refresh operation on the word line WL0, and the shadow RAM operates on the next word line W0.
Wait for the start of the refresh operation for L1.

On the other hand, the refresh operation for the last word line WLm of the memory array ARYL proceeds as in the refresh operation for the first word line WL0 as shown in FIG. 10, but the flip-flop BLC is used.
The internal control signal BLC serving as the trigger signal of F is not temporarily set to the high level again after the refresh operation is completed. Therefore, the flip-flop BLCF is left in the set state, for example, and the shared control signal SHT is set.
Shared control signals SHBL and SHBR are left at high level instead of L and SHTR. Therefore, the complementary bit line BL0 of the memory arrays ARYL and ARYR is
* To BLn * and BR0 * to BRn * are connected to the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit of the sense amplifier SA in an inverted connection and wait for access to the shadow RAM.

As is clear from the above description, the data held in all the ferroelectric memory cells forming the memory array ARYL is inverted at the time when the refresh operation, that is, the inversion rewriting operation on the final word line WLm is completed. . However, the shared control signals SHBL and SH
Since BR is set to the high level and the memory array and the sense amplifier are inversely connected, the data held in the selected memory cell viewed from the complementary input / output node of each unit amplifier circuit of the sense amplifier SA remains at the original logic level. However, its substantial logical value does not change due to inversion rewriting.

As described above, the shadow RA of this embodiment
M is normally used in the volatile mode and has a predetermined period tref.
However, the physically held data of the ferroelectric memory cells forming the memory arrays ARYL and ARYR is inverted and rewritten each time the refresh operation is performed.
Even if the actual logical value of the retained data is not inverted,
No pulse of the same polarity is applied between the electrodes of the ferroelectric capacitor of the ferroelectric memory cell. As a result, it is possible to prevent imbalance and deterioration of the information retention characteristics of the ferroelectric capacitor due to imprint, and to enhance the reliability of the shadow RAM and the like.

When the power supply voltage of the shadow RAM is cut off, the flip-flop BLCF of the bit line switching state storage circuit BLCM is cut off from its operating power supply and the connection state between the memory array and the sense amplifier cannot be stored. . Therefore, in this embodiment, the access device executes the store mode for all the word lines immediately before the power is turned off to return the connection state between the memory array and the sense amplifier to the reset state, that is, the non-inverted connection state. That is,
The access device uses the mode control signals MOD0 and MO0.
The shadow RAM is set to the store mode by setting D1 to high level and low level and the internal signal STRM to high level, and the CBR refresh operation for the word lines WL0 to WLm and WR0 to WRm of the memory arrays ARYL and ARYR is executed. At this time, in the shadow RAM, as shown in FIG. 11, provided that the flip-flop BLCF is in the set state, the shadow RAM shown in FIG.
Further, the inversion restoration is performed by the inversion rewriting operation similar to FIG. As a result, the connection between the memory array and the sense amplifier is in a non-inverting connection state in any case, and can operate normally even after the power supply voltage is next turned on.

On the other hand, the power supply voltage is cut off and the shadow RAM is
Array ARY when used in non-volatile mode
The ferroelectric memory cells forming L and ARYR selectively select the data of logic "1" or "0" depending on whether the polarization state of the ferroelectric capacitor is at point C or point F in FIG. The charge stored in the interelectrode capacitance of the ferroelectric capacitor in the volatile mode is completely discharged. Therefore, when the power supply voltage is turned on again and the shadow RAM shifts from the non-volatile mode to the volatile mode, the polarization state of the ferroelectric capacitor of each ferroelectric memory cell is identified and rewritten as the accumulated charge in the interelectrode capacitance. It is necessary to execute the recall mode for all the word lines. At this time, the access device sets the internal signal RECM to the high level by setting the mode control signals MOD0 and MOD1 to the low level and the high level, respectively, sets the shadow RAM to the recall mode, and then sets the word lines W of the memory arrays ARYL and ARYR.
A series of Cs for L0-WLm and WR0-WRm
BR refresh operation is repeated.

In the shadow RAM, as illustrated in FIG. 12, the internal control signal SH (not shown) is first set to high level in response to the fall of the row address strobe signal RASB, for example, the shared control signal SHTL is set to high level. The shared control signal SHTR is set to the low level as it is. The designated word line WL0 of the memory array ARYL is temporarily set to the selected level with a slight delay, and then immediately returned to the non-selected level, and in response to this, is supplied to the bit line precharge circuit of the sense amplifier SA. The precharge voltage VC is temporarily reduced from the intermediate potential, that is, the internal voltage HVC to the ground potential VSS, for example. Then, after the internal control signal PC is set to the low level while the precharge voltage VC is set to the ground potential VSS,
The word line WL0 of the memory array ARYL is set to the selection level again.

In the memory array ARYL, the word line WL
When 0 is first set to the selection level, this word line W
The address selection MOSFETs Qp and Qn of the n + 1 pair of ferroelectric memory cells coupled to L0 are turned on,
The information storage node of the ferroelectric capacitor is set to the precharge level of the complementary bit lines BL0 * to BLn *, that is, the internal voltage HVC. As a result, the information storage node of each memory cell in the floating state in the non-volatile mode is set to the same internal voltage HVC as the level of the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn *, and the memory cell of each memory cell is determined. The electric field applied between the electrodes of the ferroelectric capacitor becomes zero.

Here, when the word line WL0 of the memory array ARYL is set to the non-selection level and the precharge voltage VC is changed to the ground potential VSS, the memory array ARYL.
The non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * are both precharged to the ground potential VSS, that is, 0V. Then, when the word line WL0 is brought to the selection level again in this state, n + 1 coupled to the word line WL0
A reverse electric field whose absolute value is HVC is applied between both electrodes of the ferroelectric capacitors of the paired ferroelectric memory cells,
The state of each ferroelectric memory cell is from point C to point E in FIG. 3 if it holds data of logic "1", for example.
When the data of logic "0" is held, the flow goes from the point F to the point E.

As a result, for example, the non-inverted bit lines BL0T ... Of the memory cell pairs holding the data of logic "1".
In the memory cell coupled to the BLnT side, point C to point E
However, the potential of the corresponding non-inverted bit line rises comparatively greatly, but the inverted bit lines BL0B to BLnB.
In the memory cell coupled to the side, since the transition from point F to point E is accompanied by no polarization reversal, the amount of negative charges transferred is small, and the potential rise of the corresponding inversion bit line is relatively small. Similarly, in the memory cell pair which holds the data of logic "0", the memory cell coupled to the side of the inverted bit lines B0LB to BLnB is accompanied by the polarization reversal from the point C to the point E, so that a relatively large negative charge is generated. Is required, and the potential of the corresponding inversion bit line rises relatively large, but in the memory cell coupled to the non-inversion bit lines BL0T to BLnT side, the transition from point F to point E without polarization inversion occurs. Therefore, the potential rise of the corresponding non-inverted bit line is also small.

These potential differences in the complementary bit lines BL0 * to BLn * are respectively supplied to the common source lines CSP and CSN by the power supply voltage VCC and the ground potential VSS, respectively, by the corresponding unit amplifier circuits of the sense amplifier SA. After being amplified and converted into a high-level or low-level binary read signal, the inter-electrode capacitance of the ferroelectric capacitors of the n + 1 pairs of ferroelectric memory cells coupled to the word line WL0 is rewritten. As a result, the shadow RAM can shift to the volatile mode using the accumulated charges of the interelectrode capacitance, the number of polarization inversions of the ferroelectric memory cell can be reduced, and the service life of the shadow RAM can be lengthened. .

FIG. 13 shows a second part of the memory array and its peripheral part included in the shadow RAM to which the present invention is applied.
2 is a partial circuit diagram of the embodiment of FIG. Since the shadow RAM of this embodiment basically follows the embodiment of FIGS. 1 to 12, only the parts different from this will be described.

In FIG. 13, the shadow R of this embodiment is
AM is a complementary common data line CD *, that is, a sense amplifier S
Common data line CDS * complementary to A, that is, main amplifier M
Common data line switching circuit SC provided between A and A
The bit line connection switching circuits SL and SR of the above-described embodiment are replaced with shared MOSFETs NK and NL or NM and NN which receive the shared control signal SHL or SHR. The common data line switching circuit SC connects the non-inverting and inverting signal lines of the complementary common data line CD * and the non-inverting and inverting signal lines of the complementary common data line CDS *, that is, the non-inverting and inverting input / output nodes of the main amplifier MA. Complementary common data line C and N channel MOSFETs NG and NH which are respectively provided between and receive a common data line switching control signal SCT from a common data line switching control circuit (not shown)
Non-inverted and inverted signal lines of D * and complementary common data line CDS
Inverted and non-inverted signal lines of *, that is, N-channel MOSFETs NI and NJ which are respectively provided between the inverted and non-inverted input / output nodes of the main amplifier MA and receive the common data line switching control signal SCB at their gates.
The shadow RAM of this embodiment further includes a common data line switching state storage circuit (switching state storage circuit) (not shown), and the common data line switching control circuit is
Upon receiving the output signal of the common data line switching state storage circuit, the common data line switching control signals SCT and SCB are selectively formed.

As a result, the non-inverted and inverted signal lines of the complementary common data line CD * are set to the non-inverted and inverted signal lines of the complementary common data line CDS * by setting the common data line switching control signal SCT to the high level. That is, the non-inverting and inverting input / output nodes of the main amplifier MA are non-inverting connected,
When the common data line switching control signal SCB is set to the high level, it is inverted and connected to the inverted and non-inverted signal lines of the complementary common data line CDS *, that is, the inverted and non-inverted input / output nodes of the main amplifier MA. . As a result, the retained data can be inverted and rewritten in units of one sequentially selected memory cell of the memory array ARYL or ARYR, and the same effect as the above embodiment can be obtained. In the case of this embodiment, a MOS to be added to the shadow RAM as a bit line connection switching circuit.
Although the number of FETs is drastically reduced, the time required to invert and rewrite the held data is relatively long.

The operation and effect obtained from the above embodiment are as follows. That is, (1) a ferroelectric memory such as a shadow RAM that can be used in a volatile mode and a non-volatile mode with a memory array in which ferroelectric type memory cells including a ferroelectric capacitor are arranged in a grid as a basic constituent element. The memory includes, for example, two pairs of switching MOSFETs, and selectively connects between the non-inverting and inverting signal lines of each complementary bit line of the memory array and the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit of the sense amplifier. A bit line inverting circuit capable of non-inverting or inverting connection, and a switching state storage circuit for storing whether the connection between the complementary bit line and the unit amplifier circuit by these bit line inverting circuits is non-inverting or inverting connection. Is provided
For example, even when the refresh operation is performed, the data held in the memory cell is inverted and rewritten in word line units without changing the substantial logical value, and even if the actual logical value of the held data does not change, The polarity of the pulse applied between the electrodes of the ferroelectric capacitor can be inverted at a predetermined cycle.

(2) According to the above item (1), it is possible to prevent the imbalance and deterioration of the information holding characteristic of the ferroelectric capacitor due to imprinting. (3) Shadow RA according to the above (1) and (2)
The effect that the reliability of the ferroelectric memory containing M can be improved is obtained. (4) In the above items (1) to (3), the switching MOSFET forming the bit line inverting circuit is also used as a shared MOSFET for shared sense,
The effect that the increase in the chip size of the shadow RAM due to the provision of the bit line connection switching circuit can be suppressed can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the shadow RAM does not require the shared sense method as an essential condition. Further, the memory arrays ARYL and ARYR can be divided into a plurality of memory mats including their direct peripheral circuits. Furthermore, the shadow RAM may have any bit configuration such as x4 bits, x8 bits or x16 bits, and its block configuration, names of start control signals and internal control signals, combinations and effective levels, and power supply voltage. For the polarity and the like, various embodiments can be adopted.

In FIG. 2, the switching MOSFETs of the bit line connection switching circuits SL and SR can be replaced with a P-channel type, and their specific circuit configuration is also arbitrary. The shadow RAM can take various array configurations such as so-called 1-cell / 1-transistor type, and the memory arrays ARYL and ARYR and the sense amplifier SA.
The specific configuration of, the conductivity type of the MOSFET, and the like are also arbitrary.

In FIG. 3, the information retention characteristic of the ferroelectric memory cell is a standard example, and does not impose any restriction on the present invention. In FIG. 4, the inversion rewriting of the shadow RAM may be executed only once every predetermined number of refresh operations. Further, these inversion rewriting may be executed independently of the refresh operation, and it is not an indispensable condition to perform it in a strict cycle. When a means for storing which word line the inversion rewriting by the refresh operation has proceeded to is provided, a normal access can be accepted during the refresh operation. In FIG.
The specific configuration of the bit line switching control circuit BLCC can take various embodiments as long as its basic logical condition is satisfied. Further, the flip-flop BLCF of the bit line switching state storage circuit BLCM, which is the switching state storage circuit, is, for example, the memory array ARYL or ARY.
A ferroelectric memory cell located at a specific address of R may be used instead. In this case, the connection state between the memory array and the sense amplifier is maintained even after the power supply voltage is cut off.
There is no need to run store mode like. Figure 7
12 to 12, the activation control signal, the internal control signal, and the absolute time relations and levels of the internal signals are not restricted by these embodiments, and the effective levels thereof are also the same. In FIG. 13, the specific configuration of the common data line switching circuit SC is not limited to this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the shadow RAM which is the field of use which is the background of the invention has been described. However, the invention is not limited thereto, and, for example, in the volatile mode. The present invention can be applied to a normal ferroelectric memory that is never used, a single-chip microcomputer incorporating these ferroelectric memories, and the like. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a ferroelectric memory having a memory array in which ferroelectric memory cells including at least a ferroelectric capacitor are arranged in a lattice as a basic constituent element, and an apparatus or system including the same.

[0080]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a ferroelectric memory, such as a shadow RAM, which can be used in a volatile mode and a non-volatile mode, has a memory array in which ferroelectric memory cells including a ferroelectric capacitor are arranged in a grid as a basic constituent element. For example, it includes two pairs of switching MOSFETs, and selectively non-inverts between the non-inverting and inverting signal lines of each complementary bit line of the memory array and the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit of the sense amplifier. Alternatively, a bit line inversion circuit capable of inverting connection and a switching state storage circuit for storing whether the connection between the complementary bit line and the unit amplifier circuit by these bit line inversion circuits is non-inverting or inverting connection are provided, For example, each time a refresh operation is performed, the data held in the memory cells is retained in word line units without changing the actual logical value. Since the polarity of the pulse applied between the electrodes of the ferroelectric capacitor can be inverted in a predetermined cycle even if the actual logical value of the held data does not change by inverting and rewriting, It is possible to prevent the bias and deterioration of the information holding characteristics of the ferroelectric capacitor and improve the reliability of the shadow RAM and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of a shadow RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing one embodiment of a memory array included in the shadow RAM of FIG. 1 and a peripheral portion thereof;

FIG. 3 is an information holding characteristic diagram showing one embodiment of a ferroelectric memory cell constituting the memory array of FIG. 2;

FIG. 4 is a conceptual diagram showing an embodiment for explaining an operation mode of the shadow RAM shown in FIG.

5 is a circuit diagram showing an embodiment of a bit line switching state storage circuit and a bit line switching control circuit included in the shadow RAM of FIG.

6 is an operating condition diagram showing an embodiment of the bit line switching control circuit of FIG.

7 is a signal waveform diagram showing an example of a write operation in a volatile mode of the shadow RAM of FIG.

8 is a signal waveform diagram showing an embodiment of a read operation in a volatile mode of the shadow RAM of FIG.

9 is a signal waveform diagram showing an embodiment of an inversion rewriting operation on a leading word line in a refresh mode of the shadow RAM of FIG.

10 is a signal waveform diagram showing an embodiment of an inversion rewriting operation on a final word line in a refresh mode of the shadow RAM of FIG.

11 is a signal waveform diagram showing an embodiment of an inversion repair operation for a final word line in a store mode of the shadow RAM of FIG.

12 is a signal waveform diagram showing an example of an operation of converting the shadow RAM of FIG. 1 to a volatile mode in a recall mode.

FIG. 13 is a partial circuit diagram showing a second embodiment of a memory array and its peripheral portion included in a shadow RAM to which the present invention is applied.

[Explanation of symbols]

ARYL, ARYR ... Memory array, XDL, XDR
... X address decoder, XL ... X address latch,
AB ... Address buffer, RFC ... Refresh counter, SA ... Sense amplifier, SL, SR ... Bit line connection switching circuit (bit line inverting circuit), BLCC ...
... bit line switching control circuit, BLCM ... bit line switching state storage circuit, YD ... Y address decoder, Y
L ... Y address latch, MA ... main amplifier, IB
...... Input buffer, OB ... Output buffer, CG ... Clock generation circuit, MC ... Mode switching circuit. Din
…… Data input terminal, Dout …… Data output terminal, R
ASB: Row address strobe signal input terminal, CA
SB: Column address strobe signal input terminal, WE
B ... write enable signal input terminal, OEB ... output enable signal input terminal, MOD0-MOD1 ... mode control signal input terminal, A0-Ai ... address input terminal. WL0 to WLm, WR0 to WRm ... Word line, B
L0 * to BLn *, BR0 * to BRn * ... Complementary bit lines, Qp, Qn ... Address selection MOSFET, Cp,
Cn ... Ferroelectric capacitor, VP ... Plate voltage,
VC ... Precharge voltage, BS0 * to BSn * ... Sense amplifier complementary input / output nodes, SHLT, SHLB, S
HRT, SHRB ... Shared control signal, PC ... Precharge control signal, CSP, CSN ... Common source line, YS0-YSn ... Bit line selection signal, CD * ...
Complementary common data line. VOM (volatile mode), RECM
(Recall mode), STRM (store mode) ... internal signal for mode designation, tref ... refresh cycle.
ASLC ... Array selection circuit, ASL, ASR ... Array selection signal, BLCF ... Flip-flop. SHL,
SHR: Shared control signal, CDS *: Complementary common data line, SC: Common data line switching circuit. N1 to N
N ... N-channel MOSFET, P1-P2 ... P-channel MOSFET, V1-V2 ... Inverter, N
A1-NA2 ... NAND gate, NO1-
NO4 ... NOR gate.

Front Page Continuation (72) Inventor Kazuhiko Kajiya 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Inventor Seiji Narui 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) ) Inventor Tsuyuki Suzuki 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Within Hiritsu Cho-LS Engineering Co., Ltd. (72) Innovator Yasunobu Aoki 5-20, Kamimizuhoncho, Kodaira-shi, Tokyo No. 1 Hitate Super LSI Engineering Co., Ltd.

Claims (7)

[Claims] 1. A memory array comprising memory cells including ferroelectric capacitors arranged in a lattice, wherein data held in the memory cells can be inverted and rewritten without changing a substantial logical value thereof. Characteristic ferroelectric memory. 2. The inversion rewriting of the held data is performed at a predetermined cycle.
Ferroelectric memory. 3. The memory array includes word lines and complementary bit lines arranged orthogonally, and the information storage node of the memory cell is an address selection MOSFE.
The ferroelectric memory is coupled via T to a non-inversion or inversion signal line of a corresponding complementary bit line,
A sense amplifier including a unit amplifier circuit provided corresponding to the complementary bit line, and a non-inverting and inverting input / output node or inverting and non-inverting node of the unit amplifier circuit corresponding to the non-inverting and inverting signal lines of the complementary bit line. Including two pairs of switching MOSFETs respectively provided between the I / O node and the non-inverting and inverting signal lines of the complementary bit line and the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit, selectively non-inverting Or a bit line inversion circuit capable of inverting connection, and a switching state storage circuit for storing whether the connection between the complementary bit line and the unit amplifier circuit by the bit line inversion circuit is non-inverting or inverting connection The ferroelectric memory according to claim 1 or 2, wherein 4. The ferroelectric memory adopts a shared sense system, and the sense amplifier is shared by a pair of the memory arrays provided on both sides thereof, and the bit line inversion circuit. Switching MOS
FET is a shared MOSFE for shared sense
4. The ferroelectric memory according to claim 1, wherein the ferroelectric memory is also used as T. 5. The ferroelectric memory is a shadow RAM having a volatile mode and a non-volatile mode, and the inversion rewriting of the held data is performed in word line units during a refresh operation in the volatile mode of the shadow RAM. Therefore, the refresh operation is continuously performed in units of a predetermined number of word lines constituting at least one of the memory arrays. The ferroelectric memory according to claim 4. 6. The ferroelectric memory includes a complementary common data line to which the specified complementary bit line is selectively connected, non-inversion and inversion signal lines of the complementary common data line, and non-inversion of a main amplifier. And an inverting input / output node or an inverting and non-inverting input / output node, and two pairs of switching MOSFETs respectively provided between the complementary common data line non-inverting and inverting signal line and the main amplifier non-inverting and inverting input / output node. A common data line inverting circuit that can selectively connect non-inverting or inverting connection between the two, and whether the connection between the complementary common data line and the main amplifier by the common data line inverting circuit is non-inverting or inverting connection 3. The ferroelectric memory according to claim 1 or 2, further comprising: 7. The ferroelectric memory, between the complementary bit line and the unit amplifier circuit by the bit line inversion circuit or the common data line inversion circuit, or between the complementary common data line and the main amplifier, before the power supply is cut off or the like. 7. A ferroelectric memory according to claim 1, claim 2, claim 3, claim 4, claim 5, or claim 6 having a store mode for returning the connection to a non-inverting connection state. .