JPH09232449A - Mask ROM - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] Multi-valued mask ROM capable of easily realizing high integration.
To realize. Kind Code: A1 A mask ROM in which memory cell transistors are arranged in a matrix and stores data of at least three values or more, and at least a channel region of each memory cell transistor is made different according to a stored data value. Of the three types of concentrations, impurities having a concentration corresponding to the data value to be stored are respectively injected, and the threshold voltage of each memory cell transistor is set. Specifically, a memory cell transistor having a low threshold voltage has a small ion implantation amount, and a memory cell transistor having a high threshold voltage has a large ion implantation amount.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM that stores at least three-valued data.

[0002]

2. Description of the Related Art In a mask ROM mounted on a microcontroller or the like, data contents for a program from a customer are stored in a RO during a pre-process (wafer process) of the manufacturing process.
Program in M.

An ion implantation method is well known as a method for writing program data to a mask ROM. The ion implantation method is a method in which data is written by selectively performing ion implantation in the active region (channel region) under the gate electrode of the memory cell transistor and changing the threshold voltage of the memory cell transistor. is there.

For example, by ion-implanting B ⁺ (p-type impurity) into the channel portion of a specific n-type transistor to be written, the threshold voltage Vth of the transistor is written.
Becomes higher, and no current flows (does not turn on) even if the transistor is selected.

[0005]

However, in the current mask ROM, only two program states of "1 (high)" and "0 (low)" which can be represented by 1 bit per cell are set. However, there is a problem that it is difficult to achieve high integration.

In order to solve this, it is sufficient to realize multi-valued, but conventionally, since the multi-valued memory was realized by changing the cell size of the transistor, there was a problem that the manufacturing was complicated. .

The present invention has been made in view of the above circumstances, and an object thereof is to provide a mask ROM which can easily realize high integration.

[0008]

In order to achieve the above object, the present invention is a mask ROM in which memory cell transistors are arranged in a matrix and stores at least three-valued data. Impurities having a concentration corresponding to a data value to be stored among at least three types of concentrations which are different according to the stored data value are implanted into the active region, and the threshold voltage of each memory cell transistor is increased. It is set.

According to the mask ROM of the present invention, the dose amount of the ions implanted in the active region of the memory cell transistor is set to be different depending on the stored data value and the threshold voltage is set to be different. For example, the threshold voltage increases as the dose amount of ions increases. That is, a memory cell transistor having a low threshold voltage has a small amount of ion implantation, and a memory cell transistor having a high threshold voltage has a large amount of ion implantation.

[0010]

1 is a block diagram of a mask ROM according to the present invention.
FIG. 2 is a simplified cross-sectional view showing an embodiment of FIG.
It is a figure which shows the equivalent circuit of OM. This mask ROM 10
Is a non-volatile memory device of a so-called NAND type, which stores multi-valued data, for example, four values having a 2-bit information amount, as shown in the figure.

The n ⁺ diffusion layers 12 to 19 are formed on the silicon substrate 11.
And the gate electrodes 21 to 27 made of, for example, polysilicon are formed on the channel regions CH11 to CH17 of the transistors between the diffusion layers via the gate oxide film 20 so as to overlap the diffusion layers. . Specifically, the gate electrode 21 is formed between the diffusion layers 12 and 13 to form the selection transistor ST11, and the diffusion layer 1
The memory cell transistor MT11 is formed by forming the gate electrode 22 on the upper portion of the gate electrode 3. Similarly, the gate electrode 23 is formed between the diffusion layers 14 and 15 to form the memory cell transistor MT12, and the gate electrode 24 is formed between the diffusion layers 15 and 16 to form the memory cell transistor MT13. A gate electrode 25 is formed between the layers 16 and 17 to form a memory cell transistor MT14, a gate electrode 26 is formed between the diffusion layers 17 and 18 to form a memory cell transistor MT15, and the diffusion layers 18 and 19 are formed. The memory cell transistor MT16 is formed by forming the gate electrode 27 on the gap. The diffusion layer 12 is connected to the bit line BL (not shown in FIG. 1) made of a metal wiring such as aluminum, and the diffusion layer 19 is connected to the ground line GND.

That is, the memory cell transistors MT11 to MT16 made of n-type MOS transistors are connected in series, and the diffusion layer of the memory cell transistor MT11 is connected to the bit line BL via the selection transistor ST11.
The diffusion layer of the memory cell transistor MT16 is the ground line GND.
To form a NAND type device. Further, the gate electrode of the selection transistor ST11 is connected to the selection signal line SSL, and the memory cell transistors MT11 to MT11.
Each gate electrode of T16 is connected to each of control signal lines (word lines) CTL1 to CTL6.

Then, each memory cell transistor MT11
Into each of the channel regions CH12 to CH17 of MT16 to MT16, an impurity having a concentration corresponding to a data value to be stored, out of four types of concentrations different according to the stored data value, is injected to each memory cell transistor MT11. The threshold voltage of MT16 is set. In this embodiment, the memory cell transistor MT12 is in the state 0 (S
Memory cell transistor MT1 programmed to 0)
3, MT15 is programmed to state 1 (S1) corresponding to data "1", and memory cell transistors MT14, MT
16 is programmed to the state 2 (S2) corresponding to the data "2", and the memory cell transistor MT11 is the data "3".
Is programmed to state 3 (S3) corresponding to.

FIG. 3 is a conceptual diagram showing the relationship between the dose amount of impurities and the threshold voltage Vth. In FIG. 3, the horizontal axis represents the dose amount and the vertical axis represents the threshold voltage. As shown in FIG. 3, the threshold voltage increases as the dose amount of ions implanted in the channel region of the memory cell transistor increases. That is, less ion implantation is needed to program state 0, and more ion implantation is done to program state 3.

Specifically, when programming state 0, for example, boron ions (B ⁺ ) have an energy of 2
It is injected into a channel region of a predetermined memory cell transistor with a dose of 0 to 30 keV and a dose of 1 × 10 ¹³ / cm ³ . As a result, the threshold voltage of the memory cell transistor is set to about 0.8V, for example.

When programming state 1, for example, B ⁺ has an energy of 20 to 30 keV and a dose of 3
It is implanted into the channel region of a predetermined memory cell transistor at a dose of × 10 ¹³ / cm ³ . As a result, the threshold voltage of the memory cell transistor is set to, for example, about 1.6V.

When programming state 2, for example, B ⁺ has an energy of 20 to 30 keV and a dose of 5
It is implanted into the channel region of a predetermined memory cell transistor at a dose of × 10 ¹³ / cm ³ . As a result, the threshold voltage of the memory cell transistor is set to about 2.4V, for example.

When programming state 3, for example, B ⁺ has an energy of 20 to 30 keV and a dose of 7
It is implanted into the channel region of a predetermined memory cell transistor at a dose of × 10 ¹³ / cm ³ . As a result, the threshold voltage of the memory cell transistor is set to about 3.2V, for example.

A method of manufacturing the multi-valued mask ROM of FIG. 1 will be described below with reference to FIG. FIG. 4 is a simplified cross-sectional view at the time of ion implantation for programming in the manufacturing process of the multilevel mask ROM according to the present invention. Each process up to this stage can be performed according to a usual mask ROM manufacturing method.

First, LOCOS (not shown) made of silicon oxide is formed on a predetermined region of the surface of the semiconductor substrate 11 by, for example, a selective thermal oxidation method, and then a gate oxide film 20 is formed on the surface of the semiconductor substrate 11 surrounded by the LOCOS. To do. The gate oxide film 20 is formed after annealing is sufficiently performed in a nitrogen atmosphere at 850 to 900 ° C. and then the oxidation prevention film is removed. The gate oxide film 20 is formed in a hydrogen combustion atmosphere (wet type), a thermal oxidation method (dry type), or the like, and its thickness is about 6 to 12 nm.

Next, a polysilicon film or the like, which is a film material of the gate electrodes 21 to 27, is formed on the gate oxide film 20 by a CVD method or the like, and subsequently, a refractory metal film such as WSix is formed. The thickness of the polysilicon film is about 100 nm,
Impurities such as phosphorus are introduced to improve conductivity.
The refractory metal film is formed by the CVD method or the sputtering method.
A film of about 100 nm is formed. Then, the refractory metal film and the polysilicon film are sequentially etched using the resist having a predetermined pattern as a mask to obtain a gate electrode whose resistance is lowered by the refractory metal.

Next, for example, a low concentration LDD is formed by an ion implantation method using the formed gate electrode as a mask.
Then, a sidewall is formed on the sidewall of the gate electrode. The side wall is formed by forming a side wall material made of PSG so as to cover the gate electrode and then etching back by RIE or the like from the surface side. Then, using the formed sidewall as a mask, a high concentration region is formed by an ion implantation method to obtain the impurity diffusion layers 12 to 19.

Next, a first interlayer insulating layer (not shown) such as a silicon oxide film is formed, and a contact hole is opened on each diffusion layer. After that, a plug of W or the like is selectively grown by a CVD method or the like so as to fill the opened contact hole, and a main wiring metal film such as a barrier metal Al and an antireflection film are formed in this order. Then, after patterning these first metal wiring layers, a second interlayer insulating layer is formed. The second interlayer insulating layer is formed by, for example, SOG (Spin on Glass) or ozone NSG (Non-doped nat) for planarization.
ural Silicate Glass), etc. are used. After forming the first metal wiring layer, the wafer is stocked at the time when the planarization process is completed.

Then, the mask ROM 10 is sequentially programmed based on the program data from the customer. As shown in FIG. 4, the programming of the mask ROM 10 is performed by introducing an impurity (for example, B ⁺ ) into the channel region of the specific transistor using a mask pattern (resist pattern 30) opened only on the specific transistor. . Since this impurity introduction is performed by high-energy ion implantation, a thick film resist is used and its film thickness is set in the range of 1.7 to 2.5 μm.

The program ion implantation is carried out sequentially from the memory cell transistor side having the smallest impurity dose amount to the memory cell transistor having the largest dose amount.
That is, first, the state 0 in which the threshold voltage is about 0.8 V
Are programmed into the memory cell transistor MT12. Specifically, for example, B ⁺ has an energy of 20 to
The resist pattern 30 is used to selectively implant into the channel region CH13 of the memory cell transistor MT12 with a dose of 1 × 10 ¹³ / cm ³ at 30 keV. As a result, the threshold voltage of the memory cell transistor becomes 0.
It is set to about 8V.

Next, the state 1 in which the threshold voltage is about 1.6 V is programmed in the memory cell transistors MT13 and MT15. Specifically, for example, B ⁺ has an energy of 20 to 30 keV and a dose amount of 3 × 10 ¹³ / cm ^3.
Then, the resist pattern 30 is used to selectively inject into the channel regions CH14 and CH16 of the memory cell transistors MT13 and MT15. As a result, the threshold voltage of the memory cell transistor is set to about 1.6V.

Next, the state 3 in which the threshold voltage is about 2.4 V is programmed in the memory cell transistors MT14 and MT16. Specifically, for example, B ⁺ has an energy of 20 to 30 keV and a dose amount of 5 × 10 ¹³ / cm ^3.
Then, the resist pattern 30 is used to selectively inject into the channel regions CH15 and CH17 of the memory cell transistors MT14 and MT16. As a result, the threshold voltage of the memory cell transistor is set to about 2.4V.

Then, the state 3 in which the threshold voltage is about 3.2 V is programmed in the memory cell transistors MT11 and MT16. Specifically, for example, B ⁺ has an energy of 20 to 30 keV and a dose of 7 × 10 ¹³ / cm 3.
³ is selectively implanted into the channel region CH12 of the memory cell transistor MT11 using the resist pattern 30. As a result, the threshold voltage of the memory cell transistor is set to about 3.2V.

After that, although not particularly shown, after removing the resist pattern 30, a second metal wiring layer or the like is laminated via an interlayer insulating layer, and finally an overcoat is formed and a pad window is opened to form the mask ROM 10 of the present invention. Complete. In addition,
In the above description of the embodiment, there is no limitation other than the matters specifically mentioned, and various modifications can be made within the scope of the present invention. For example, in the present embodiment, the programming is performed from the interlayer insulating film after the first metal wiring layer is formed. However, if the energy is optimized, from the interlayer insulating film or the overcoat on the second metal wiring layer or from the LOCOS. It is possible to perform programming directly on the substrate after forming the film and before forming the gate oxide film or through the gate oxide film after forming the gate oxide film.

As described above, according to this embodiment, in the mask ROM in which the memory cell transistors are arranged in a matrix, the channel regions of the memory cell transistors are made different according to the stored data value. Since the impurity having a concentration corresponding to the data value to be stored among the plurality of types (four types in the present embodiment) of the concentration is injected and the threshold voltage thereof is set, the mask ROM
Can be multi-valued, the number of bits per memory cell can be increased, and the cell area can be reduced.

In the present embodiment, four values are described as an example of multivalues, but by setting the impurity concentration with good control, a multivalued mask ROM of 8 values, 16 values, etc. can be realized. .

In this embodiment, the NAND type mask ROM to which the ion implantation writing method is generally applied has been described as an example. However, the present invention is not limited to this, and the present invention is a NOR type mask ROM. Bit line has a hierarchical structure D
It goes without saying that it can be applied to various types of mask ROMs such as an INOR type.

[0033]

As described above, the mask R of the present invention is used.
According to OM, there is an advantage that high integration can be realized without going through complicated manufacturing steps.

[Brief description of drawings]

FIG. 1 is a simplified cross-sectional view showing an embodiment of a multi-valued mask ROM according to the present invention.

FIG. 2 is a diagram showing an equivalent circuit of the mask ROM of FIG.

FIG. 3 is a conceptual diagram showing a relationship between an impurity dose amount and a threshold voltage Vth.

FIG. 4 is a simplified cross-sectional view at the time of ion implantation for programming in the manufacturing process of the multi-valued mask ROM according to the present invention.

[Explanation of symbols]

10 ... Mask ROM, 11 ... Silicon substrate, 12-19
... Diffusion layer, 20 ... Gate oxide film, 21-27 ... Gate electrode, ST11 ... Select transistor, MT11-MT16 ... Memory cell transistor, CH11-CH17 ... Channel region,
BL ... bit line, SSL ... selection signal line, CTL1 to CT
L6 ... Control signal line, 30 ... Resist pattern.

Claims (2)

[Claims] 1. A mask ROM in which memory cell transistors are arranged in a matrix and stores data of at least three values, wherein active regions of each memory cell transistor are made different according to a stored data value. A mask ROM in which an impurity having a concentration corresponding to a data value to be stored among at least three types of concentrations is injected, and the threshold voltage of each memory cell transistor is set. 2. The mask ROM according to claim 1, which has a NAND structure.