JPH09232427A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the etching time of a side wall layer and to prevent a etching stopper layer to be exposed to an etchant. SOLUTION: A plurality of gate electrodes 4 and 4a are formed on a semiconductor substrate 1. On the plurality of gate electrodes 4 and 4a, an etching stopper layer is formed. On the side of the plurality of gate electrode 4 and 4a, the first side wall layer 10 is formed. An inter-layer insulation film 12 which covers a plurality of gate electrodes 4 and 4a and the side wall layer 10 is formed. On the inter-layer insulation film 12 between a plurality of gate electrodes 4 and 4a, a contact hole 15 is formed. Here, by making the etching speed of the etching stopper layer slower than that of the inter-layer insulation film 12, and the etching speed of the first side wall layer 10 equal to or faster than that of the inter-layer insulation film 12, the contact hole 15 is formed on the inter-layer insulation film 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a contact hole for wiring.

[0002]

2. Description of the Related Art The miniaturization and high-density of semiconductor devices are still being vigorously promoted, and at present, 1 gigabit DRAMs (256 gigabits) designed based on a 0.25 μm size standard or less are designed. Ultra-highly integrated semiconductor devices such as dynamic random access memories) have been developed and prototyped. With such high integration of semiconductor devices, there has been a strong demand for further reduction or elimination of a mask alignment margin in a lithography process, which is essential for forming a semiconductor element structure.

Usually, in the manufacture of a semiconductor device, patterns formed of various materials such as a metal film, a semiconductor film, and an insulator film are sequentially laminated on a semiconductor substrate to form a semiconductor device having a fine structure. In the case of laminating a pattern for a semiconductor element, in a lithography step, it is required to align a mask with a lower layer pattern formed in a previous step to form a next upper layer pattern. However, in this lithography process, a positional deviation occurs between the upper layer / lower layer patterns. Therefore, it is necessary to allow a margin for the pattern interval on the mask in consideration of the positional deviation and set a margin for the pattern interval. However, this margin becomes a hindrance factor for increasing the pattern density.

[0004] Therefore, various techniques have been started to be considered for a marginless technique for making the above-mentioned margin unnecessary.
Among them, particularly important one is to reduce the margin in forming a contact hole. These contact holes are formed in various layers on a semiconductor substrate, a semiconductor film, and a metal film and are often used. Therefore, reducing the margin is most effective in increasing the density / integration of a semiconductor device. is there. A prominent method among the marginless technologies is a method of forming a self-aligned contact hole, and various concrete methods have been studied. As an example thereof, an etching stopper layer having etching selectivity with respect to the interlayer insulating film is provided on the wiring so that the wiring is not etched by the etching for forming the contact hole.

For example, in Japanese Patent Laid-Open No. 3-106027, an etching stopper layer is provided on each of a plurality of gate electrodes arranged adjacent to a memory cell region, and side surfaces of the etching stopper layer and the gate electrode are covered. It is described that the interlayer insulating film is formed on the entire surface and the contact hole is formed in the interlayer insulating film between the plurality of gate electrodes. According to this disclosure, the contact hole is formed in a self-aligned manner by using the etching stopper layer on the gate electrode as a mask, and a sidewall layer made of an interlayer insulating film is formed on the side surface of the gate electrode, so that the gate electrode and the contact hole are formed. Is insulated from. However, in such a manufacturing method, the sidewall layer made of the interlayer insulating film is easily removed or the gate electrode is easily exposed in the contact hole, so that the insulation failure between the gate electrode and the contact hole is sufficiently generated. Can not be suppressed.

Next, as another conventional technique for solving such a problem, it is assumed that the method of forming a self-aligned contact hole is applied to a 256 Mbit DRAM with reference to FIGS. And explain.

As shown in FIG. 10A, an element isolation insulating film 102 is formed on the surface of a silicon substrate 101. Then, the memory cell portion 100a of the DRAM and the peripheral circuit portion 1
00b is electrically separated. Next, the gate insulating film 1
03 is formed. Here, this gate insulating film is a silicon oxide film having a thickness of about 8 nm. Memory cell section 10
A large number of memory cells each composed of one transistor and one capacitor are formed in 0a. The peripheral circuit portion 100b is composed of a CMOS circuit using both n-type and p-type transistors, and a transistor of a lightly doped drain (LDD) structure is adopted to improve transistor performance. Gate electrode 104 of transfer transistor formed in memory cell portion 100a
a is formed of tungsten polycide or titanium polycide, and its size is about 0.25 μm.
This gate electrode 104a is the word line of this memory device. Further, the interval between the adjacent gate electrodes 104a is about 0.2 to 0.25 μm. Further, the film thickness of the gate electrode 104a is also about 0.2 to 0.25 μm. The size of the gate electrode 104b of the CMOS transistor formed in the peripheral circuit part 100b is generally larger than the size of the gate electrode of the transfer transistor of the memory cell part, and is set to about 0.4 μm. The buffer layer 106 is formed on the gate electrodes 104a and 104b.
And the etching stopper layer 107 are formed by stacking.
Next, shallow diffusion layers 108 and 108a forming the source / drain of the MOS transistor are formed. here,
The impurity concentration of the shallow diffusion layers 108 and 108a is 1 ×
It is set to about 10 ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 10 (b), a covering insulating film 1 having a film thickness of 100 to 150 nm so as to cover the whole.
09 is deposited. Here, the coating insulating film 109 is SiO _{2 formed} by a known CVD (chemical vapor deposition) method.

Next, the entire surface of the coating insulating film 109 is etched by anisotropic reactive ion etching (RIE) (hereinafter referred to as "etchback"). By such etch back, the sidewall layers 110a and 110b are formed on the sidewalls of the gate electrodes 104a and 104b as shown in FIG. The sidewall layer 110b is used as an ion implantation mask for forming the deep diffusion layer 108b at a position away from the end of the gate electrode 104b, and the thickness of the sidewall layer is set to 100 to 150 nm.

Next, by well-known selective ion implantation using a resist (not shown) as a mask, the peripheral circuit portion 100b is formed.
The impurities are again introduced only into the shallow diffusion layer of the CMOS transistor and the heat treatment is applied to form the deep diffusion layer 108b. Here, the impurity concentration of the deep diffusion layer 108b is set to 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ . As described above, the diffusion layers of the source / drain of the CMOS transistor in the peripheral circuit section have the well-known LDD structure.

Next, as shown in FIG. 11A, an interlayer insulating film 113 such as a silicon oxide film (BPSG film) containing boron and phosphorus is deposited on the entire surface, and the gate electrode 10 is formed.
The steps caused by 4a and 104b are flattened. Next, using the resist pattern 114 as a mask, the contact hole 1
15 is opened. For the etching of the contact hole opening, an etching method having a selectivity with the etching stopper layer 107 is used.

For example, when the etching stopper layer 107 is a silicon nitride film, it is known that the silicon oxide film can be selectively dry-etched with respect to the silicon nitride film by using a mixed gas of carbon fluoride and carbon monoxide. Has been. In this case, the etching selectivity between the silicon oxide film and the silicon nitride film is 5: 1 to 15: 1. This etching stopper layer 107 is the gate electrode 1
Since only the upper part of 04a is covered, the sidewall of the gate electrode 104a is exposed in the contact hole 115 after contact etching. Therefore, the resist pattern 11
After peeling off 4, the insulating film 117 such as a silicon oxide film is deposited as shown in FIG. Further, as shown in FIG. 11C, the second sidewall layer 1 is formed on the sidewall of the contact hole 115 and the sidewall of the gate electrode 104a by anisotropic etching.
08 is formed.

In this way, the contact hole 115 insulated from the gate electrode 104a in a self-aligned manner can be obtained.

[0014]

In this conventional method,
The following new problems are considered to occur.

The sidewall layer 1 used for forming the LDD structure transistor of the peripheral circuit portion 100b.
The film thickness of 10b directly affects the transistor characteristics and reliability. Since this film thickness is determined by the diffusion coefficient of impurities and the heat treatment temperature and time in the device manufacturing process, it is not easy to reduce the film thickness in accordance with the miniaturization of the element. Particularly, since boron having a large diffusion coefficient is used for the source / drain impurities of the p-type transistor,
Even in 56M and 1G DRAM, this film thickness is 100 to 2
It is designed for 00 nm. Since the transistor of the memory cell portion 100a of this memory device does not need to have the LDD structure, the sidewall layer 110a is unnecessary. However, when the side wall layer 110b is formed, the side wall layer 110a is inevitably formed. The gate electrode 104 of the memory cell having this degree of integration
Since the distance a is 0.15 to 0.25 μm, the space between the gate electrodes 104a is almost completely filled with the sidewall layer 110a. That is, the space between adjacent word lines is filled with the sidewall layer 110a. The contact holes 115 are formed between the word lines.
In order to open the holes, the sidewall layer 110a as well as the interlayer insulating film 113 must be etched. However, normally, the HTO film used as the sidewall layer 110a has an etching rate of about 2 to 1/3 that of the BPSG film. Therefore, the etching time from the exposure of the etching stopper layer 107 above the word line to the contact hole 115 to the exposure of the diffusion layer 108 becomes long. Therefore, the etching stopper layer 107 on the upper portion of the wiring exposed to the etching atmosphere for a long time is etched from the corner with low selectivity, and the etching stopper layer 116 becomes thin as shown in FIG. 11A. turn into. For this reason, it causes a poor insulation between the contact hole 115 and the word line 104a.

It may be possible to prevent insulation failure by forming the etching stopper layer 107 to be thick in advance. However, if the etching stopper layer 107 is made thick in this way, the step difference between the word line 104a and the etching stopper layer 107 becomes large, and the depth of the contact hole 115 must be made deep. If the contact hole 115 becomes deeper, another problem arises in that it is difficult to open the hole, the flatness is deteriorated, and the coverage of a film formed thereafter is deteriorated.

Therefore, it is an object of the present invention to provide an improved method of forming a self-aligned contact hole.

[0018]

A method for manufacturing a semiconductor device according to the present invention comprises a step of forming a plurality of wirings on a semiconductor substrate, a step of forming a sidewall layer on a side surface of the plurality of wirings, and a step of forming the plurality of wirings. And a step of forming an interlayer insulating film covering the wiring and the sidewall layer, and by setting the etching rate of the sidewall layer to be equal to or higher than the etching rate of the interlayer insulating film, the interlayer insulating film between the wiring and A step of removing the sidewall layer to form a contact hole.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a plurality of wirings on a semiconductor substrate, a step of forming an etching stopper layer on the plurality of wirings, and a sidewall on a side surface of the plurality of wirings. A step of forming a layer, a step of forming an interlayer insulating film covering the plurality of wirings and the sidewall layer, and a step of forming a contact hole in the interlayer insulating film between the plurality of wirings. A step of forming a contact hole by setting the etching rate of the stopper layer to be slower than the etching rate of the interlayer insulating film and setting the etching rate of the sidewall layer to be equal to or higher than the etching rate of the interlayer insulating film. Characterize.

According to the present invention, the etching rate of the sidewall layer is made equal to or higher than the etching rate of the interlayer insulating film, so that the interlayer insulating film and the sidewall layer between the plurality of wirings are removed to form the contact hole. Therefore, the etching time of the sidewall layer is shortened, and the etching time required for forming the contact hole can be shortened.

Further, according to the present invention, the etching rate of the etching stopper layer is slower than the etching rate of the interlayer insulating film, and the etching rate of the sidewall layer is equal to or higher than the etching rate of the interlayer insulating film. Since the etching is performed, the etching time of the sidewall layer can be shortened and the time during which the etching stopper layer is exposed to the etchant can be shortened. Thereby, the etching amount of the etching stopper layer by the etchant can be reduced. Therefore, while thinning the etching stopper layer formed on the plurality of wirings,
It is possible to prevent the occurrence of defective insulation between the wiring and the contact hole. As a result, it is possible to reduce the depth of the formed contact hole and eliminate defective insulation between the plurality of wirings and the contact hole.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are sectional views in the order of manufacturing steps for explaining the first embodiment of the present invention.

As shown in FIG. 1A, an element isolation insulating film 2 is formed on the surface of a p-type silicon substrate 1 which is an example of a semiconductor substrate. As a result, the memory cell unit 1 of the DRAM
a and the peripheral circuit section 1b are partitioned and electrically separated. Next, the gate insulating film 3 is formed. Here, the gate insulating film 3 is a silicon oxide film or a silicon oxynitride film having a film thickness of about 6 to 8 nm. After this, a large number of MOS transistors, that is, transfer transistors are arranged in the memory cell portion 1a. Further, CMOS transistors are formed in the peripheral circuit portion 1b. Next, a titanium polycide film having a film thickness of about 0.2 μm is formed on the entire surface, and the film thickness is 10 n.
A silicon oxide film having a thickness of about m is formed on the entire surface, and a silicon nitride film having a thickness of about 50 nm is further formed on the entire surface. Next, the silicon nitride film, the silicon oxide film, and the titanium / polycide film are sequentially patterned to form an etching stopper layer 7 of the silicon nitride film, a buffer layer 6 of the silicon oxide film, and gate electrodes 4, 4a of the titanium / polycide film. , 5 are formed respectively. Memory cell section 1a
The size of the gate electrodes 4 and 4a formed on the substrate is 0.2 μm.
It is a degree. The distance between adjacent gate electrodes 4 and 4a is about 0.2 μm. The gate electrodes 4 and 4a formed in the memory cell portion 1a are
It is an AM word line (wiring). The size of the gate electrode 5 formed in the peripheral circuit portion 1b is larger than the size of the gate electrodes 4 and 4a formed in the memory cell portion 1a by 0.4.
It is set to about μm.

Next, impurities are introduced into the semiconductor substrate 1 using the etching stopper layer 7, the buffer layer 6 and the gate electrodes 4, 4a and 5 as a mask, and the source / source of the MOS transistor is removed.
N-type shallow diffusion layers 8 and 8a forming the drain are formed in alignment with the gate electrodes 4, 4a and 5, respectively. Here, the impurity concentration of the shallow diffusion layers 8, 8a is 1 × 10
It is set to about ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 1B, a first coating insulating film 9 having a film thickness of 150 nm is deposited so as to cover the entire surface. Here, as an example of the first coated insulating film 9, PSG by LPCVD (low pressure chemical vapor deposition) method is used.
The film is a silicon oxide film containing phosphorus glass. The concentration of phosphorus atoms contained in this PSG film is about 10 mol%.

Next, anisotropic etchback is applied to the first coated insulating film 9. Here, this etchback is performed by using a mixed gas of C ₄ F ₈ and CO as a reaction gas.
The method E is used. By such etch back, FIG.
As shown in (c), first sidewall layers 10 and 10a are formed on the sidewalls of the gate electrodes 4, 4a and 5, respectively. Here, the film thickness of the first sidewall layers 10 and 10a is set to 100 nm. By this etch back process, the above-mentioned first sidewall layers 10 and 10a are formed.
At the same time, the buried insulating layer 11 made of the first sidewall layer 10 is left between the gate electrodes 4 and 4a having a small separation distance in the memory cell portion 1a.

Next, as shown in FIG. 2A, a resist mask 12 for ion implantation is formed by a known lithography technique. Then, by well-known selective ion implantation using this as a mask, impurities are reintroduced only into the shallow diffusion layer 8a of the MOS transistor in the peripheral circuit portion 1b, and heat treatment is applied to form an n-type deep diffusion layer 8b. To be done. Here, the impurity concentration of this deep diffusion layer 8b is 1 × 10 ¹⁹ to 1
It is set to × 10 ²⁰ atoms / cm ³ . In this way,
The MOS transistor of the peripheral circuit portion 1b has an LDD structure in which the source / drain regions are composed of the diffusion layers 8a and 8b.

Next, after removing the resist mask 12, an interlayer insulating film 13 is formed on the entire surface to form the gate electrodes 4, 4a, 5
The level difference caused by the above is flattened. Here, the interlayer insulating film 13 is a BPSG film (silicon oxide film containing boron glass and phosphorus glass) having a film thickness of 400 nm. In this case, the concentrations of boron and phosphorus atoms contained in the BPSG film are set to about 5 mol% and 10 mol%, respectively, in terms of molar concentration. Next, a contact hole resist mask 14 is formed by patterning into a predetermined shape. Then, using this as a dry etching mask,
The interlayer insulating film 13, the buried insulating layer 11 made of a sidewall layer, and the gate insulating film 3 on the surface of the diffusion layer 8 are etched. Thus, the contact hole 15 is formed. Here, since the etching stopper layer 7 is formed on the gate electrodes 4 and 4a, the contact hole 15 is formed on the diffusion layer 8 in self-alignment with the gate electrodes 4 and 4a as described above. In the dry etching of the interlayer insulating film 13 and the buried insulating layer 11, it is more preferable to increase the etching rate ratio between the interlayer insulating film 13 and the buried insulating layer 11 and the etching stopper layer 7. Therefore, C ₄ F is used as a reaction gas in RIE.
A gas in which CO is mixed with ₈ is used. By selecting such a gas, the etching rate ratio becomes about 20, and the role of the etching stopper layer 7 as an etching mask is secured.

Next, after removing the resist mask 14, a second coating insulating film 16 is deposited on the entire surface so as to cover the contact hole 15 and the interlayer insulating film 13 as shown in FIG. 2C. It Here, the second coating insulating film 16 is a silicon oxide film having a film thickness of about 60 nm. This silicon oxide film is an HTO film which is excellent in step coverage and is formed by the CVD method at a high film forming temperature of about 800 ° C.

Next, the entire surface of the second insulating film 16 is etched back. Here, in this etch back, for example, a mixed gas of CHF ₃ and CO or a mixed gas of C ₄ F ₈ and CO is used as an anisotropic RIE reaction gas. In this manner, as shown in FIG. 2D, the second sidewall layer 17 is formed on the side walls of the gate electrodes 4 and 4a of the transfer transistor in the memory cell portion. Further, sidewall layers 17 'are also formed on the sidewalls of the contact holes 15 formed in the interlayer insulating film 13. In this case, the thickness of the second sidewall layer 17 is 50
It is about nm. And the final contact hole 15 '
Is about 100 nm.

As described above, the MO of the peripheral circuit section 1b is
A film thickness of 100 is formed on the side wall of the gate electrode 5 of the S transistor.
a first sidewall layer 10a having a thickness of 10 nm, a second sidewall layer 17 is formed on sidewalls of the gate electrodes 4 and 4a of the transfer transistor of the memory cell portion 1a, and the gate electrode 4 having the second sidewall layer 17 is formed. , 4a are self-aligned with contact holes 15 '
Formed on top.

Further, an impurity-doped polysilicon plug 18 filling the contact hole 15 'is formed. The polysilicon plug 18 can be formed by selective growth of polysilicon or by etchback after full surface growth. Next, the interlayer insulating film 13 and the polysilicon plug 1
A tungsten silicide film 19 having a film thickness of about 0.15 μm is formed so as to cover the film 8. This tungsten silicide 1
9 is an example of a high boiling point metal silicide film. The tungsten silicide film 19 is a digit line of the DRAM, is connected to the diffusion layer 8 located between the gate electrodes 4 and 4a through the polysilicon plug 18, and the digit line is through the self-aligned contact hole 15 '. Connected to the diffusion layer 8.

According to the present embodiment, the first sidewall layers 10 and 10a are made of a material having an etching rate equal to or higher than the etching rate of the BPSG film forming the interlayer insulating film 13. Therefore, when the etching of the interlayer insulating film 13 for forming the contact hole 15 is completed, the buried insulating layer 11 made of the first sidewall layer 10 is also removed. As a result, the etching time required to form the contact hole 15 can be shortened.
Further, the interlayer insulating film 13 for forming the contact hole 15 is formed.
When the etching is completed, the embedded insulating layer 11 made of the first sidewall layer 10 is also removed, so that the time when the etching stopper layer 7 is exposed to the etchant can be shortened. by this,
It is possible to prevent film loss of the etching stopper layer 7. By preventing the film thickness reduction, it is possible to prevent the occurrence of insulation failure between the contact holes 15 'at the corners of the gate electrodes 4 and 4a forming the word line (wiring). That is, it is possible to prevent a short circuit between the word line and the digit line. Further, according to the present embodiment, it is possible to reduce the film thickness of the etching stopper layer 7, so that the film thickness of the etching stopper layer 7 formed on the gate electrodes 4 and 4a can be reduced. As a result, the etching stopper layer 7 is thinned to reduce the depth of the contact hole 15 and to prevent occurrence of a short circuit between the gate electrode 4, 4a forming the word line and the contact hole 15 '. Can be made.

In this embodiment, the first sidewall layer 10 is formed as P on the interlayer insulating film 13 of the BPSG film.
The SG film was selected and explained. However, other membranes can be used. PSG film and BSG are used as the interlayer insulating film 13.
When an impurity-doped silicon oxide film such as a film, a BPSG film, or a laminated film of these is used, the first sidewall layer 10 is doped with an impurity such as a PSG film, a BSG film, a BPSG film, or a laminated film of these. A silicon oxide film can be used, and the etching rate of the first sidewall layer can be made equal to or higher than the etching rate of the interlayer insulating film 13. Particularly, when the BPSG film is used as the first sidewall layer for the interlayer insulating film of the PSG film, the etching rate of the first sidewall layer is made higher than that of the interlayer insulating film for the same etchant for forming contact holes. be able to.

Further, in this embodiment, the contact hole 1
The tungsten silicide film 19 of the digit line was connected to the diffusion layer 8 through the polysilicon plug 18 filling the 5 '. This is because the contact hole 15 'is so fine that the metal film cannot be formed well in the contact hole 15'. Therefore, when the contact hole is not particularly fine, for example, a digit line having a polycide structure is formed on the interlayer insulating film 13 and the second sidewalls 17 and 17 '.
It is also conceivable to form the diffusion line 8 thinly so as to cover the surface thereof and connect the digit line to the diffusion layer 8. That is, a polysilicon film is thinly formed on the entire surface and then a tungsten silicide film is thinly formed on the entire surface to form a digit line having a polycide structure.

Next, a second embodiment will be described with reference to FIGS. As shown in FIG. 3A, an element isolation insulating film 22 is formed on the surface of a silicon substrate 21 which is an example of a semiconductor substrate. Then, a gate insulating film 23 is formed. Here, the gate insulating film is a silicon oxide film or a silicon oxynitride film having a film thickness of about 8 nm. After this, M of the memory cell section 20a
A large number of OS transistors, that is, transfer transistors are arranged and formed. Further, CMOS transistors are formed in the peripheral circuit section 20b. Memory cell section 2
The gate electrodes 24 and 24a of the transfer transistor formed at 0a are made of titanium polycide and have a size of 0.15 to 0.2 μm. This gate electrode 2
4, 24a are word lines of the memory device. Also,
The distance between the adjacent gate electrodes 24 and 24a is 0.2 μm
The degree is set. Furthermore, the gate electrodes 24, 24a
Is also set to about 0.2 μm. Peripheral circuit section 20
Gate electrode 25 of the MOS transistor formed in b
Is generally larger than the dimensions of the gate electrodes 24, 24a of the transfer transistors of the memory cell portion 20a, and is set to about 0.3 μm. Buffer layer 26
Is formed by covering the above-mentioned gate electrodes 24, 24a, 25, and further an etching stopper layer 27 is formed so as to cover the buffer layer 26. Here, the buffer layer is a silicon oxide film having a film thickness of about 10 nm, and the etching stopper layer 27 is a silicon oxide film containing excess silicon (hereinafter referred to as an SRO film) having a film thickness of about 50 nm.

The method of forming the SRO film will be briefly described below. The method of forming this film is basically the same as the method of forming a silicon dioxide film by the CVD method. That is, LP which heats a quartz reaction tube which can be decompressed with a heater.
In a CVD furnace, the temperature of the furnace is set at 700 ° C. to 800 ° C., and monosilane and nitrous oxide gases are introduced into the furnace through different gas inlets as reaction gases. Here, nitrogen gas is used as the atmospheric gas, and the total pressure of these gases is set to about 1 Torr. With this film formation method, the silicon dioxide film contains excess silicon. For this purpose, the gas flow rate of monosilane and nitrous oxide is changed to increase the gas flow rate of monosilane. Here, as the gas flow ratio of monosilane increases, the excess silicon amount increases. Thus, a thin film of silicon oxide containing excess silicon, that is, an SRO film is formed. This SRO film is an insulator having a structure in which minute silicon aggregates are mixed in a silicon dioxide (SiO ₂ ) film.

Next, similar to the first embodiment, the shallow diffusion layer 2 forming the source / drain of the MOS transistor is formed.
8, 28a is formed. Here, this shallow diffusion layer 2
The concentration of the impurities of 8,28a is set to about 1 × 10 ¹⁸ atoms / cm ³ .

As shown in FIG. 3B, a coat insulating film 29 'having a film thickness of 5 nm to 10 nm is deposited so as to cover the whole. Here, this coat insulating film 29 'is CV
It is a silicon oxide film formed by the D method. Further, a BPSG film, for example, by the LPCVD method is formed as the first coating insulating film 29 that covers the coating insulating film 29 '. Here, the concentration of phosphorus atoms contained in this BPSG film is about 8 mol%, and the content of boron atoms is 3
It is about mol%. And the film thickness of this BPSG is 20
It is set to about 0 nm.

Next, anisotropic etchback by RIE is applied. Here, the reaction gas of RIE is C ₄ F ₈
A mixed gas of CO and CO is used. By such etch-back, as shown in FIG.
First sidewall layers 30, 30a are provided on the side walls of 4a, 25a.
Is formed. Here, the first side wall layer is formed of the above-described coat insulating film 2 having a thickness of 5 to 10 nm.
9'and the first coating insulating film 29, and the total film thickness thereof is set to about 150 nm. In this etch back process, together with the formation of the first sidewall layer,
A gate electrode 24 having a small separation distance in the memory cell portion 2a,
A buried insulating layer 31 is formed between 24a. here,
The buried insulating layer 31 is composed of the first sidewall layer 30 and is formed by integrating adjacent first sidewall layers, and is composed of the coat insulating film 29 ′ and the first covering insulating film 30. ing.

Next, as shown in FIG. 4A, a resist mask 12 that covers the memory cell portion 20a is formed. next,
Ion implantation is performed using this as a mask and the MOS of the peripheral circuit portion 20b is
Impurities are introduced into the shallow diffusion layer 8a of the transistor and heat treatment is applied to form a deep diffusion layer 8b. This allows
The MOS transistor of the peripheral circuit portion 20b has an LDD structure in which the source / drain region is composed of the shallow diffusion layer 8a and the deep diffusion layer 8b.

Next, after removing the resist mask 12, an interlayer insulating film 13 is formed on the entire surface to form a gate electrode 24,
The steps caused by 24a, 25, etc. are flattened. Here, as the interlayer insulating film 13, B as in the first embodiment is used.
A PSG film is used. Next, a resist film is formed on the interlayer insulating film 13, and this is patterned to form a contact hole forming resist mask 14. Next, as shown in FIG. 4B, the interlayer insulating film 13 and the embedded insulating layer 31 formed of the coat insulating film 29 ′ and the first covering insulating film 29 are etched using this as a mask. As a result, the contact hole 15 is formed. Here, the gate electrodes 24, 2
Since the etching stopper layers 27 are formed on the respective 4a, the contact holes 15 are formed in the gate electrodes 24, 2
4a is self-aligned. Here, the coat insulating film 29 ′ is composed of a silicon oxide film having an etching rate slower than that of the interlayer insulating film 13. However, this film thickness is about 1/10 of the distance between the gate electrodes 24 and 24a. Therefore, the buried insulating layer 31 is almost filled with the BPSG film having a high etching rate. Therefore,
When the contact hole 15 is formed, the etching stopper layer 27
The exposure time of the element to the etchant is longer than that of the first embodiment, but can be shorter than that of the prior art.

Next, as shown in FIG. 4C, a second coating insulating film 16 is deposited on the entire surface so as to cover the contact hole 15 and the interlayer insulating film 13. The second coating insulating film 16 is
For example, an HTO film is used as in the first embodiment. next,
By etching back the second coating insulating film 16,
As shown in (d), the second sidewall layer 17 is formed on the sidewalls of the gate electrodes 24, 24a, and the interlayer insulating film 13 is formed.
The sidewall layer 17 'is also formed on the inner wall of the contact hole 15 formed in the above, and finally the contact hole 15' is formed. Then, similarly to the first embodiment, the digit line connected to the diffusion layer 8 via the contact hole 15 'is formed.

In this embodiment, the first sidewall layer 3
0, 30a and the buried insulating layer 31 are coated with the insulating film 29 '.
And the first covering insulating film 29. That is, the coat insulating film 29 ′ is formed between the first covering insulating film 29 and the gate electrodes 24, 24 a, 25 and the gate insulating film 23. Further, the coat insulating film 29 'is composed of an impurity non-doped silicon oxide film having a film thickness of about 1/10 of the distance between the gate electrodes 24 and 24a. Further, the first coating insulating film 29 is composed of a BPSG film,
First sidewall layers 30 and 30a and buried insulating layer 3
Most of No. 1 is composed of a BPSG film. Therefore, BP
When the etching for forming the contact hole 15 in the interlayer insulating film 13 made of the SG film is completed, the buried insulating layer 31 made of the first sidewall layer 30 is also removed. As a result, the etching time required to form the contact hole 15 is somewhat longer than that in the first embodiment, but can be shortened compared to the conventional case. Further, when the etching of the interlayer insulating film 13 for forming the contact hole 15 is completed, the buried insulating layer 3 including the first sidewall layer 30 is formed.
Since 1 is also removed, the time when the etching stopper layer 27 is exposed to the etchant can be shortened. As a result, the film thickness of the etching stopper layer 7 can be prevented. By preventing the film loss, the gate electrodes 24 and 24a forming the word line are formed.
It is possible to prevent the occurrence of defective insulation between the contact hole 15 'and the contact hole 15'. Further, according to the present embodiment, it is possible to reduce the film thickness of the etching stopper layer 27, so that the film thickness of the etching stopper layer 27 formed on the gate electrodes 24 and 24a can be reduced.
As a result, the contact hole 15 'is made shallow by thinning the etching stopper layer 27, and the gate electrodes 24 and 24a forming the word line and the contact hole 1 are formed.
It is possible to achieve both prevention of occurrence of a short circuit defect with 5 '.

Further, in the present embodiment, the coat insulating film 2
By providing 9 ′, it is possible to prevent the impurity diffusion from the impurity-doped silicon oxide film such as the BPSG film forming the first covering insulating film 29 to the semiconductor substrate 21.
This will be described with reference to FIG. FIG.
It is a graph which shows the thermal diffusion of phosphorus from a PSG film of 0 mol% concentration to a silicon substrate. Here, a silicon oxide film having a film thickness of 5 to 20 nm is formed between the PSG film and the silicon substrate, and after the PSG film is deposited, 800 ° C.
This is the case where the heat treatment for 2 hours is added. From this figure, even if the silicon oxide film has a thickness of 5 nm, the amount of phosphorus entering the silicon substrate is 2E16 cm ^−3, that is, 2 × 10 ¹⁶
The number of atoms / cm ^{3 is} approximately 10 nm or less. In the manufacturing process of the 256M DRAM, it is assumed that the heat treatment is performed at a temperature of 850 ° C. or higher for 1 to 2 hours after forming the word line. If the film is provided below, the diffusion of impurities from the impurity-doped silicon oxide film into the semiconductor substrate will not be a problem, and the transistor characteristics can be prevented from being affected. That is, in the present embodiment, by providing the coat insulating film 29 ′, it is possible to prevent the impurity diffusion from the impurity-doped silicon oxide film such as the BPSG film forming the first cover insulating film 29 to the semiconductor substrate 21, and the transistor. It is possible to prevent fluctuations in characteristics. That is, by making the etching stopper layer 27 thin, the depth of the contact hole 15 'is made shallow, and the gate electrodes 24, 24 forming the word line are formed.
It is possible to prevent the transistor characteristic from fluctuating while preventing the occurrence of a short circuit failure between the a and the contact hole 15 '.

In the case of the second embodiment, since the SRO film is used as the etching stopper layer, the reliability of the MOS transistor formed is improved as compared with the case of the first embodiment. Since the BPSG film is used as the first covering insulating film, the etching rate ratio in dry etching between the first covering insulating film and the etching stopper layer is 2
Since it is ensured at about 0, it becomes easy to form a highly reliable self-aligned contact hole.

In this embodiment, BPSG is used as the first covering insulating film 29 for the interlayer insulating film 13 of the BPSG film.
The membrane was chosen and explained. However, other films can be used as in the first embodiment. When an impurity-doped silicon oxide film such as a PSG film, a BSG film, a BPSG film, or a laminated film thereof is used for the interlayer insulating film 13, the first covering insulating film 29 is a PSG film, a BSG film, a BP.
An impurity-doped silicon oxide film such as an SG film or a laminated film thereof can be used. Particularly, when the BPSG film is used as the first coating insulating film for the interlayer insulating film of the PSG film, the etching rate of the first coating insulating film is higher than that of the interlayer insulating film for the etchant for forming the contact hole. can do.

Next, a third embodiment will be described with reference to FIGS. 6 and 7. In the case of this embodiment, a method of forming a self-aligned contact hole when the element isolation insulating film is exposed is shown. As shown in FIG. 6A, the element isolation insulating film 42 is formed in the groove formed on the surface of the silicon substrate 41. The element isolation insulating film 42 has a depth of 0.3 μm to 0.8 μ in a predetermined region of the silicon substrate 41.
A groove of about m is formed by known dry etching, a thin silicon oxide film having a thickness of about 2 nm to 5 nm is provided on the side wall of the groove, and an SRO film is buried in the groove. Alternatively, only the SRO film is formed to be buried in the groove.

The subsequent process of forming a self-aligned contact hole is similar to that of the first embodiment, but the structure is different and will be described in detail below. The element isolation insulating films 42 and 42a are formed as described above, and the gate insulating film 43 is formed as shown in FIG. Here, the gate insulating film is a silicon oxide film or a silicon oxynitride film having a thickness of about 4 to 6 nm. Then, a MOS transistor in the memory cell portion, that is, a transfer transistor and a CMOS transistor in the peripheral circuit portion are formed. The gate electrodes 44 and 44a of the transfer transistor formed in the memory cell portion are made of titanium polycide and have a size of about 0.2 μm. Then, the gate electrode 44a is formed on the element isolation insulating film 42. The distance between adjacent gate electrodes 44 and 44a is set to about 0.3 μm. Further, the thickness of the gate electrodes 44, 44a is set to about 0.2 μm.
On the other hand, the size of the gate electrode 45 of the CMOS transistor formed in the peripheral circuit section is generally larger than the size of the gate electrode of the transfer transistor in the memory cell section, and is set to about 0.3 μm. Next, the buffer layer 46 forms the gate electrodes 44, 44a, 45 described above.
And an etching stopper layer 47 which covers the buffer layer 46. here,
The buffer layer is a silicon oxide film with a thickness of about 10 nm, and the etching stopper layer is an SR with a thickness of about 50 nm.
It is an O film. Next, shallow diffusion layers 48 and 48a that form the source / drain of the MOS transistor are formed.
Here, the impurity concentration of the shallow diffusion layers 48 and 48a is set to about 1 × 10 ¹⁸ atoms / cm ³ .

After this, as shown in FIG. 6B, a first coating insulating film 49 having a film thickness of 150 nm is deposited so as to cover the entire surface. Here, the first coating insulating film 4
Reference numeral 9 denotes a silicon dioxide film formed by a CVD method. Next, anisotropic etchback is applied to the first covering insulating film 49. By such etch back, as shown in FIG. 6C, the first sidewalls of the gate electrodes 44, 44a, 45 are formed.
The sidewall layers 50 and 50a are formed. Here, the thickness of the first sidewall layer is 100
Set to nm. In this etch back process, the buried insulating layer 51 is formed between the gate electrodes 44 and 44a having a small separation distance in the memory cell portion together with the formation of the first sidewall layer described above.

Next, by well-known selective ion implantation, impurities are introduced again into only the shallow diffusion layer 48a of the CMOS transistor in the peripheral circuit portion and a heat treatment is applied, so that FIG.
A shallow diffusion layer 48b shown in (a) is formed. here,
The impurity concentration of this deep diffusion layer 48b is 1 × 10 ¹⁹ to 1 ×.
It is set to 10 ²⁰ atoms / cm ³ . As described above, the diffusion layers of the source and drain of the CMOS transistor in the peripheral circuit portion are formed to have a well-known LDD structure. Next, the interlayer insulating film 53 is formed. Here, the interlayer insulating film 53 is a BPSG film having a thickness of 400 nm. After this, the contact hole resist mask 54 is formed by patterning into a predetermined shape. Then, using this as a mask for dry etching, the interlayer insulating film 53 and the buried insulating layer 51 are etched. In this way, the contact hole 55 is formed.
Since the etching stopper layer 47 is formed on the gate electrodes 44 and 44a, the contact holes are formed on the diffusion layer 48 and the element isolation insulating film 42 by self-aligning with the gate electrodes 44 and 44a as described above. 55 is formed. In the dry etching of the interlayer insulating film 53 and the buried insulating layer 51, it is more preferable to increase the etching rate ratio between the interlayer insulating film 53 and the buried insulating layer 51 and the etching stopper layer 7. Therefore, as the reaction gas in RIE, a gas in which CO is mixed with C ₄ F ₈ is used. By selecting such a gas, the etching rate ratio becomes about 20, and the role of the etching stopper layer as the etching mask is secured.

Next, as shown in FIG. 7B, the second coating insulating film 56 is formed into the contact hole 55 and the interlayer insulating film 5 described above.
3 is deposited. Here, the second covering insulating film 56 is a silicon oxide film having a thickness of about 60 nm. This silicon oxide film is a film formed by a CVD method at a high film formation temperature of about 800 ° C.

After this, the second coated insulating film 5 is formed.
6 is performed. Here, in this etch back, C is used as anisotropic RIE reaction gas.
₄ mixed gas of F ₈ and CO is used. In this way, as shown in FIG. 7C, the second sidewall layer 57 is formed on the sidewalls of the gate electrodes 44 and 44a of the transfer transistor in the memory cell portion. The second in this case
The thickness of the sidewall layer 17 is about 50 nm. And the final size of the contact hole 55 'is 200 nm.
About. Here, this self-aligned contact hole 5
In 5 ', the exposed portion of the element isolation insulating film region is 100 nm.
Degree included.

In the case of this embodiment, it is important to secure the dry etching rate ratio between the silicon dioxide film used as the first covering insulating film and the SRO film. The etching rate ratio will be described below with reference to FIG. As the dry etching apparatus, a magnetron type is used. The frequency of the high frequency power source of the device in this case is normally used 1
3.56 MHz. Further, CO gas is mixed with C ₄ F ₈ and introduced as a reaction gas. FIG. 8 is a graph showing the relationship between the ratio of the etching rate of the silicon dioxide film to the etching rate of the SRO film and the amount of silicon contained in the SRO film in this case. As shown in FIG. 8, when the amount of silicon in the SRO film becomes 35% or more, the etching ratio becomes 15 or more. Here, the amount of silicon in the SRO film is about 33.3%
The case corresponds to the silicon dioxide film. This indicates that any SRO film containing 2% or more excess silicon than the silicon dioxide film can be used as the first insulating film. Then, the dry etching is performed under such conditions. The etching rate of the BPSG film used as the interlayer insulating film in the third embodiment is much higher than that of the silicon dioxide film.

This SRO film is used as an element isolation insulating film. For this reason, it is necessary to ensure the insulation of the SRO film. FIG. 9 shows the relationship between the specific resistance and the relative dielectric constant of the SRO film and the excess silicon amount in the SRO film. Here, the thickness of the SRO film is 100 nm, and the specific resistance is low (1 ×
10 ⁶ v / cm or less). 0.2 mentioned above
The allowable leakage current of the diffusion layer in a semiconductor device such as a DRAM designed on the basis of the dimension of μm is on the order of 10 ⁻¹⁷ amperes. Therefore, if the specific resistance value of this element isolation insulating film is 10 ¹⁴ Ω · cm or more, it is in a range that can be sufficiently dealt with. In the case of the SRO film, this condition is satisfied if the silicon content is 40 at% or less, as can be seen from FIG. Here, considering that the case of the silicon amount of 33.3% corresponds to the silicon dioxide film as described in FIG. 8, the above condition is satisfied if the excess silicon amount in the silicon dioxide film is 6 at% or less. Will be done. Further, within this range, the relative permittivity of the SRO film is about 4, which is about the same as that of the silicon dioxide film and causes no problem.

In the case of the third embodiment, both the first side wall layer and the second side wall layer are formed of a silicon dioxide film having higher insulation or moisture resistance than a silicon oxide film containing phosphorus glass or boron glass. To be done. Therefore, a high quality semiconductor device can be formed more easily than in the case of the first and second embodiments. In this way, a thick side wall layer is formed on the side wall of the gate electrode of the CMOS transistor of the peripheral circuit section that requires high reliability, and the side wall layer between the gate electrodes of the memory cell section is once removed. A thin sidewall layer is formed again on the sidewalls of the gate electrodes of the memory cell portions having a small interval. Here, the etching stopper layer formed on the upper surface of the gate electrode is used as a dry etching mask for forming these sidewall layers. Therefore, it becomes possible to form a contact hole for wiring in a memory cell in a semiconductor device, particularly a semiconductor memory device such as a DRAM, in a self-aligning manner with high reliability. Further, the manufacturing process of the contact hole is stabilized. Then, the deterioration of the characteristics or the deterioration of the reliability of the CMOS transistor of the peripheral circuit portion, which often occurs in the conventional technique, is eliminated, the density or miniaturization of the memory cell portion is facilitated, and the semiconductor device is reduced in size and has a large capacity. The conversion is promoted. Further, the performance or the yield of the semiconductor device is improved and the variation thereof is greatly reduced.

[0058]

As described above, according to the present invention,
By setting the etching rate of the sidewall layer to be equal to or higher than the etching rate of the interlayer insulating film, the interlayer insulating film between the wirings and the sidewall layer are removed to form the contact hole. As a result, the etching time required for forming the contact hole can be shortened.

Further, according to the present invention, the etching rate of the etching stopper layer is slower than the etching rate of the interlayer insulating film, and the etching rate of the sidewall layer is equal to or higher than the etching rate of the interlayer insulating film. Since the etching is performed, the etching time of the sidewall layer can be shortened and the time during which the etching stopper layer is exposed to the etchant can be shortened. Thereby, the etching amount of the etching stopper layer by the etchant can be reduced. Therefore, while thinning the etching stopper layer formed on the plurality of wirings,
It is possible to prevent the occurrence of defective insulation between the wiring and the contact hole. As a result, it is possible to reduce the depth of the formed contact hole and eliminate defective insulation between the plurality of wirings and the contact hole.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of manufacturing steps for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view in the order of manufacturing steps for explaining the first embodiment of the present invention.

FIG. 3 is a cross-sectional view in the manufacturing process order for explaining the second embodiment of the present invention.

FIG. 4 is a cross-sectional view in the manufacturing process order for explaining the second embodiment of the present invention.

FIG. 5 is a graph showing the amount of phosphorus impurities entering the silicon substrate from the PSG film.

FIG. 6 is a cross-sectional view in the manufacturing process order for explaining the third embodiment of the present invention.

FIG. 7 is a sectional view in order of manufacturing steps, for illustrating a third embodiment of the present invention.

FIG. 8 is a silicon oxide film containing excess silicon (SR
It is a graph which shows the dry etching characteristic of an (O film).

FIG. 9 is a graph showing insulation characteristics of an SRO film.

FIG. 10 is a cross-sectional view in the order of manufacturing steps for explaining the conventional technique.

FIG. 11 is a cross-sectional view in the manufacturing process order for explaining the conventional technique.

Claims (12)

[Claims] 1. A step of forming a plurality of wirings on a semiconductor substrate, a step of forming a sidewall layer on a side surface of the plurality of wirings, and an interlayer insulating film covering the plurality of wirings and the sidewall layer. And a step of forming a contact hole by removing the interlayer insulating film and the sidewall layer between the wirings by making the etching rate of the sidewall layer equal to or higher than the etching rate of the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: 2. A step of forming a plurality of wirings on a semiconductor substrate, a step of forming an etching stopper layer on each of the plurality of wirings, and a step of forming a sidewall layer on a side surface of the plurality of wirings. A step of forming an interlayer insulating film covering the plurality of wirings and the sidewall layer, and a step of forming a contact hole in the interlayer insulating film between the plurality of wirings, wherein an etching rate of the etching stopper layer is And a step of forming a contact hole by making the etching rate of the sidewall layer slower than the etching rate of the interlayer insulating film and equal to or more than the etching rate of the interlayer insulating film. Method. 3. The silicon oxide film doped with impurities such as PSG, BSG, BPSG or a laminated film thereof is used as the interlayer insulating film and the sidewall layer. Manufacturing method of semiconductor device. 4. The side wall layer covers the impurity-doped silicon oxide film, the side walls of the plurality of wirings, and the surface of the semiconductor substrate, thereby separating the impurity-doped silicon oxide film from the semiconductor substrate. And a membrane.
Alternatively, the method of manufacturing a semiconductor device according to claim 3. 5. The method according to claim 1, further comprising a step of covering side walls of the plurality of wirings exposed in the contact holes with another insulating film. Manufacturing method of semiconductor device. 6. A step of forming a plurality of wirings on a semiconductor substrate, a step of forming an etching stopper layer on each of the plurality of wirings, and a buried insulating layer so as to fill a space between the plurality of wirings. A step of forming an interlayer insulating film covering the plurality of wirings and the buried insulating layer, and a step of forming a contact hole in the interlayer insulating film and the buried insulating layer between the plurality of wirings, Forming a contact hole by making the etching rate of the etching stopper layer slower than the etching rate of the interlayer insulating film and making the etching rate of the buried insulating layer equal to or higher than the etching rate of the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: 7. The manufacturing of a semiconductor device according to claim 6, wherein an impurity-doped silicon oxide film such as PSG, BSG, BPSG, or a laminated film thereof is used as the interlayer insulating film and the buried insulating layer. Method. 8. The coating insulation, wherein the buried insulating layer covers the impurity-doped silicon oxide film, the sidewalls of the plurality of wirings, and the surface of the semiconductor substrate, thereby separating the impurity-doped silicon oxide film from the semiconductor substrate. 8. A method of manufacturing a semiconductor device according to claim 6, further comprising a film. 9. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of covering sidewalls of the plurality of wirings exposed in the contact holes with another insulating film. Method. 10. A step of partitioning a semiconductor substrate into a peripheral circuit section and a memory cell section with an element isolation insulating film, a first gate electrode is formed in the peripheral circuit section, and a second and a second gate electrodes are formed in the memory cell section. Forming a third gate electrode, forming an etching stopper layer on each of the second and third gate electrode wirings, and aligning the first gate electrode with a shallow source / drain region around the periphery. Forming a shallow source / drain region in the memory cell portion in alignment with the second and third gate electrodes, respectively, and forming first to third side surfaces of the first to third gate electrodes. Forming each of the third sidewall layers,
Forming shallow source / drain regions in the peripheral circuit portion in alignment with the first sidewall layer; and interlayer insulation covering the first to third wirings and the first to third sidewall layers. A step of forming a film and a step of forming a contact hole in the interlayer insulating film between the second and third gate electrodes, wherein an etching rate of the etching stopper layer is higher than an etching rate of the interlayer insulating film. And a step of forming a contact hole by setting the etching rate of the second and third sidewall layers to be equal to or higher than the etching rate of the interlayer insulating film. 11. The second and third sidewall layers located between the second and third gate electrodes are integrally formed to fill the space between the second and third gate electrodes. 11. The method of manufacturing a semiconductor device according to claim 10, wherein a buried insulating layer is formed, and a contact hole penetrating the buried insulating layer is formed in the step of forming a contact hole in the interlayer insulating film. . 12. The buried insulating layer covers the impurity-doped silicon oxide film, the sidewalls of the second and third gate electrodes, and the surface of the semiconductor substrate, whereby the impurity-doped silicon oxide film is covered with the semiconductor. The method of manufacturing a semiconductor device according to claim 11, further comprising a coat insulating film which is separated from the substrate.