JPH09232365A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH09232365A JPH09232365A JP8037724A JP3772496A JPH09232365A JP H09232365 A JPH09232365 A JP H09232365A JP 8037724 A JP8037724 A JP 8037724A JP 3772496 A JP3772496 A JP 3772496A JP H09232365 A JPH09232365 A JP H09232365A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- external electrode
- lead
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000011347 resin Substances 0.000 claims abstract description 14
- 229920005989 resin Polymers 0.000 claims abstract description 14
- 238000007789 sealing Methods 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 22
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 239000002184 metal Substances 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 17
- 229910001111 Fine metal Inorganic materials 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、小型化・薄型化を
実現できる半導体装置およびその製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be made compact and thin, and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、半導体装置を用いた電子機器類は
小型化の方向にあり、そのため半導体装置自体もその動
向にともない、微細化、高集積化が進行している。その
ため、半導体装置の組立・実装技術も小型化・薄型化が
進行している。2. Description of the Related Art In recent years, electronic devices using semiconductor devices have been miniaturized, and accordingly, the semiconductor devices themselves have been miniaturized and highly integrated in accordance with the trend. Therefore, the assembling / mounting technology for semiconductor devices is also becoming smaller and thinner.
【０００３】以下、従来の半導体装置について図面を参
照しながら説明する。図８は従来の半導体装置の構造を
示す概略断面図である。図９は従来の半導体装置の半導
体素子とリードフレームとの接続構造を示す概略平面図
である。A conventional semiconductor device will be described below with reference to the drawings. FIG. 8 is a schematic sectional view showing the structure of a conventional semiconductor device. FIG. 9 is a schematic plan view showing a connection structure between a semiconductor element and a lead frame of a conventional semiconductor device.
【０００４】図８、図９において、半導体素子１は支持
基板であるリードフレーム２のダイパッド部３上に接着
剤により接合され、搭載されている。そして搭載された
半導体素子１とリードフレーム２の外部との接続用のリ
ード部４は、金線などの金属細線５により電気的導通が
可能なように接続されている。また半導体素子１および
ダイパッド３を含む外囲領域は、封止樹脂６によりモー
ルドされ、半導体装置を構成しているものである。In FIGS. 8 and 9, the semiconductor element 1 is mounted on the die pad portion 3 of the lead frame 2 serving as a supporting substrate by bonding with an adhesive. The lead portion 4 for connecting the mounted semiconductor element 1 and the outside of the lead frame 2 is connected by a thin metal wire 5 such as a gold wire so as to be electrically conductive. The surrounding area including the semiconductor element 1 and the die pad 3 is molded with the sealing resin 6 to form a semiconductor device.
【０００５】また小型化・薄型化という目的で、キャリ
アテープを用いて、キャリアテープのリード部と半導体
素子とをバンプにより接続する技術も開発されている。For the purpose of downsizing and thinning, a technique has been developed in which a carrier tape is used to connect the lead portion of the carrier tape and a semiconductor element by bumps.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら従来のよ
うに、半導体素子をリードフレーム上に搭載して、金属
細線で接続する場合には、接続した金属細線の高さが制
限され、金属細線の高さを低くすることは現在の技術で
は困難な状態にある。そのため、半導体装置自体を薄く
することはできない。また図９に示すように、金属細線
で接続する場合は、リード部４と半導体素子１との間に
一定の距離が確保されなければならず、半導体装置の小
型化にも限界があった。さらに金属細線で半導体素子と
リードフレームとを接続するにしても、キャリアテープ
を用いて、キャリアテープのリード部と半導体素子とを
バンプにより接続するにしても、組立工程では接続手段
を設ける工程が必ず必要となり、組立工程での工程数を
削減させることができないものである。However, when a semiconductor element is mounted on a lead frame and is connected with a thin metal wire as in the prior art, the height of the thin metal wire connected is limited, and the height of the thin metal wire is increased. It is difficult to reduce the height with the current technology. Therefore, the semiconductor device itself cannot be thinned. Further, as shown in FIG. 9, in the case of connecting with a thin metal wire, a certain distance must be secured between the lead portion 4 and the semiconductor element 1, and there is a limit to miniaturization of the semiconductor device. Further, even if the semiconductor element and the lead frame are connected by a thin metal wire, or if the carrier tape is used to connect the lead portion of the carrier tape and the semiconductor element by bumps, a step of providing a connecting means in the assembly step is required. It is always necessary and the number of steps in the assembly process cannot be reduced.
【０００７】本発明は、従来のような課題を解決するも
ので、半導体装置自体を小型化・薄型化し、しかも組立
工程での工程数を削減することができる半導体装置およ
びその製造方法を提供することを目的とする。The present invention solves the conventional problems, and provides a semiconductor device which can be made smaller and thinner and the number of steps in the assembly process can be reduced, and a manufacturing method thereof. The purpose is to
【０００８】[0008]
【課題を解決するための手段】本発明は、課題を解決す
るために、リードフレームの各リード部上に接合された
半導体素子と、少なくともその半導体素子とリード部の
一部とを封止している封止樹脂とよりなる半導体装置に
おいて、半導体素子と各リード部とはその半導体素子の
各電極パッドと接続した外部電極部により接続されてい
るものであり、金属細線により接続手段を有することな
く、またリードフレームのダイパッド部を除去したもの
である。SUMMARY OF THE INVENTION In order to solve the problems, the present invention seals a semiconductor element bonded on each lead portion of a lead frame and at least the semiconductor element and a part of the lead portion. In the semiconductor device made of the encapsulating resin, the semiconductor element and each lead portion are connected by the external electrode portion connected to each electrode pad of the semiconductor element, and have a connecting means by a thin metal wire. In addition, the die pad portion of the lead frame is removed.
【０００９】また製造方法にあっては、半導体素子の電
極パッドの領域外から、裏面におよぶ領域に絶縁層を形
成する第１の前処理工程と、半導体素子に形成した絶縁
層上に導電性材料により外部電極部を形成する第２の前
処理工程と、半導体素子に形成した各外部電極部とリー
ドフレームのリード部とを対応させて、リード部上に半
導体素子を搭載する第１の組立工程と、半導体素子およ
びリード部の一部を含む外囲領域を封止樹脂により封止
する第２の組立工程とよりなるものであり、ワイヤーボ
ンディング工程を除去し、組立工程では大きくダイスボ
ンディング工程と封止工程とを有するものである。Further, in the manufacturing method, a first pretreatment step of forming an insulating layer in a region extending from outside the electrode pad region of the semiconductor element to the rear surface thereof and conducting on the insulating layer formed on the semiconductor element are conducted. A first pre-processing step of forming an external electrode portion with a material, and a first assembly in which a semiconductor element is mounted on the lead portion by associating each external electrode portion formed on the semiconductor element with the lead portion of the lead frame. And a second assembly step of sealing the surrounding area including the semiconductor element and a part of the lead portion with a sealing resin. The wire bonding step is removed, and the die bonding step is largely performed in the assembly step. And a sealing step.
【００１０】[0010]
【発明の実施の形態】前記手段により、半導体素子とリ
ードフレームとの接続は、金属細線を用いていないの
で、金属細線の高さ制限を受けることはなく、また半導
体素子とリード部との間にも距離を設けなくてもよいの
で、半導体装置として小型化・薄型化できるものであ
る。また金属細線を用いていないので、組立工程での金
属細線での接続工程、すなわちワイヤーボンディング工
程を削除することができ、組立工程での工程数を削減す
ることができる。By the means described above, since the metal thin wire is not used for the connection between the semiconductor element and the lead frame, there is no restriction on the height of the metal thin wire, and between the semiconductor element and the lead portion. Since it is not necessary to provide a distance, the semiconductor device can be made smaller and thinner. Further, since the thin metal wire is not used, the connecting step using the thin metal wire in the assembling step, that is, the wire bonding step can be eliminated, and the number of steps in the assembling step can be reduced.
【００１１】以下、本発明の一実施形態について図面を
参照しながら説明する。図１は、本実施形態の半導体装
置の構造を示す概略断面図である。図２は、本実施形態
の半導体装置の半導体素子とリードフレームとの接続構
造を示す概略平面図である。Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing the structure of the semiconductor device of this embodiment. FIG. 2 is a schematic plan view showing the connection structure between the semiconductor element and the lead frame of the semiconductor device of this embodiment.
【００１２】図１、図２において、半導体素子７は支持
基板であるリードフレーム８のリード部９上に接着剤に
より接合され、搭載されている。そして搭載された半導
体素子７とリードフレーム８の外部との接続用のリード
部９は、半導体素子７に半導体素子７の製造プロセス段
階で形成された外部電極部１０により、電気的導通が可
能なように接続されている。また半導体素子７およびリ
ード部９の一部を含む外囲領域は、封止樹脂１１により
モールドされ、半導体装置を構成しているものである。
なお、図２において、ハッチングを付した箇所が、外部
電極部１０を示しており、また破線で示した構成は、半
導体素子７の裏面に配設したリードフレーム８のリード
部９である。In FIGS. 1 and 2, the semiconductor element 7 is mounted on a lead portion 9 of a lead frame 8 which is a supporting substrate by bonding with an adhesive. The lead portion 9 for connecting the mounted semiconductor element 7 and the outside of the lead frame 8 can be electrically conducted by the external electrode portion 10 formed on the semiconductor element 7 during the manufacturing process of the semiconductor element 7. Are connected as. The surrounding area including the semiconductor element 7 and a part of the lead portion 9 is molded with the sealing resin 11 to form a semiconductor device.
In FIG. 2, the hatched portion indicates the external electrode portion 10, and the configuration indicated by the broken line is the lead portion 9 of the lead frame 8 arranged on the back surface of the semiconductor element 7.
【００１３】次に本実施形態で示した半導体装置の半導
体素子７に形成された外部電極部１０の構造について説
明する。図３は半導体素子に形成された外部電極部の構
造を示す断面図である。Next, the structure of the external electrode portion 10 formed on the semiconductor element 7 of the semiconductor device shown in this embodiment will be described. FIG. 3 is a cross-sectional view showing the structure of the external electrode portion formed on the semiconductor element.
【００１４】図３に示すように、半導体素子７上の電極
パッド１２から半導体素子７の裏面まで外部電極部１０
が設けられているが、外部電極部１０の下層には、各外
部電極１０どうしが短絡しないように、半導体素子７上
の電極パッド１２の領域外から半導体素子７の裏面まで
を絶縁層１３が設けられ、各外部電極部１０は分離独立
されている。この絶縁層１３は、半導体素子７である例
えばシリコンチップなどの外部電極部を形成する領域を
絶縁化処理したり、半導体素子７の外部電極部を形成す
る領域にポリイミドなどの絶縁性材料を形成するなどし
て形成することができる。また外部電極部１０は、導電
性樹脂を用いて形成したり、金などの導電性材料を用い
て蒸着したり、メッキするなどして形成することができ
る。As shown in FIG. 3, the external electrode portion 10 extends from the electrode pad 12 on the semiconductor element 7 to the back surface of the semiconductor element 7.
The insulating layer 13 is provided below the external electrode portion 10 from outside the area of the electrode pad 12 on the semiconductor element 7 to the back surface of the semiconductor element 7 so that the external electrodes 10 are not short-circuited. The external electrode portions 10 are provided so as to be separated and independent. The insulating layer 13 insulates a region of the semiconductor element 7 in which external electrodes such as a silicon chip are formed, or forms an insulating material such as polyimide in a region of the semiconductor element 7 in which external electrodes are formed. It can be formed, for example. In addition, the external electrode portion 10 can be formed by using a conductive resin, vapor deposition using a conductive material such as gold, or plating.
【００１５】次に本実施形態の半導体装置の製造方法に
ついて説明する。図４〜図７は、製造工程を示す断面図
である。Next, a method of manufacturing the semiconductor device of this embodiment will be described. 4 to 7 are cross-sectional views showing the manufacturing process.
【００１６】図４に示すようにまず前処理として、シリ
コンチップに代表される半導体素子７の電極パッド１２
の領域外から、裏面におよぶ領域にリソグラフィー技術
によりポリイミドなどの感光性絶縁性材料を用いて絶縁
層１３を形成しておく。この場合、半導体素子７の表
面、側面、裏面と三面に絶縁層１３を形成するので、ま
ず表面と側面とに絶縁層を形成し、次いで側面と裏面と
に絶縁層を形成する、という二段リソグラフィーにより
形成することができる。勿論、それ以外の方法で形成し
てもよい。As shown in FIG. 4, first, as a pretreatment, the electrode pad 12 of the semiconductor element 7 represented by a silicon chip is used.
The insulating layer 13 is formed in advance from outside the region to the back surface by a lithographic technique using a photosensitive insulating material such as polyimide. In this case, since the insulating layer 13 is formed on the front surface, the side surface, and the back surface of the semiconductor element 7, the insulating layer is first formed on the front surface and the side surface, and then the insulating layer is formed on the side surface and the back surface. It can be formed by lithography. Of course, it may be formed by other methods.
【００１７】次に図５に示すように、半導体素子７に形
成した絶縁層１３上に導電性材料により外部電極部１０
を形成する。この外部電極部１０の形成は、感光性樹脂
に導電物質を含有させた導電性材料を用いて、前記絶縁
層１３の形成と同様にリソグラフィー技術により形成す
ることができる。Next, as shown in FIG. 5, the external electrode portion 10 is made of a conductive material on the insulating layer 13 formed on the semiconductor element 7.
To form The external electrode part 10 can be formed by a lithographic technique using a conductive material containing a conductive material in a photosensitive resin, similarly to the formation of the insulating layer 13.
【００１８】次に図６に示すように組立工程として、半
導体素子７に形成した各外部電極部１０を対応させて、
リードフレーム８のリード部９上に導電性接着剤により
接合する。Next, as shown in FIG. 6, in the assembly process, the external electrode portions 10 formed on the semiconductor element 7 are made to correspond to each other.
It is bonded onto the lead portion 9 of the lead frame 8 with a conductive adhesive.
【００１９】そして図７に示すように、半導体素子７お
よびリード部９の一部を含む外囲領域を封止樹脂１１に
よりトランスファーモールドして、封止する。Then, as shown in FIG. 7, the surrounding area including the semiconductor element 7 and a part of the lead portion 9 is transfer-molded by the sealing resin 11 and sealed.
【００２０】以上のように、本実施形態の半導体装置の
製造方法は、予め半導体素子７に対して外部電極部１０
を形成しているので、組立工程では、リードフレーム８
に接合するだけで、電気的接続工程を完了させることが
でき、金属細線によるワイヤーボンディング工程を削除
して、組立工程の簡素化を実現できるものである。As described above, according to the method of manufacturing the semiconductor device of this embodiment, the external electrode portion 10 is previously attached to the semiconductor element 7.
Since the lead frame 8 is formed in the assembly process,
The electrical connection step can be completed simply by joining the wires to the wire, and the wire bonding step using the fine metal wires can be eliminated to simplify the assembly step.
【００２１】以上のように本実施形態の半導体装置は、
半導体素子７に設けた外部電極部１０によりリードフレ
ーム８のリード部９と接合することができ、金属細線を
使用した接続手段を用いることがないため、金属細線を
使用した場合の金属細線の高さ制限を受けず、さらにダ
イパッド部を削除したリードフレームを使用できるの
で、薄型化を実現した半導体装置である。またリードフ
レームのリード部と半導体素子との間に一定距離を設け
る必要もないので、小型化を実現した半導体装置であ
る。As described above, the semiconductor device of this embodiment is
Since the external electrode portion 10 provided on the semiconductor element 7 can be joined to the lead portion 9 of the lead frame 8 and a connecting means using a metal thin wire is not used, the height of the metal thin wire when the metal thin wire is used is increased. Since the lead frame can be used without the limitation of the size and the die pad portion is further removed, the semiconductor device is thin. Further, since it is not necessary to provide a fixed distance between the lead portion of the lead frame and the semiconductor element, the semiconductor device can be miniaturized.
【００２２】また製造方法においては、予め組立工程の
前工程において、半導体素子７に対して外部電極部１０
を形成しているので、組立工程では、リードフレーム８
に接合するだけで、電気的接続工程を完了させることが
でき、金属細線によるワイヤーボンディング工程を削除
して、組立工程の簡素化を実現できるものである。In the manufacturing method, the external electrode portion 10 is previously attached to the semiconductor element 7 in the pre-process of the assembling process.
Since the lead frame 8 is formed in the assembly process,
The electrical connection step can be completed simply by joining the wires to the wire, and the wire bonding step using the fine metal wires can be eliminated to simplify the assembly step.
【００２３】[0023]
【発明の効果】以上、本発明の半導体装置は、半導体素
子に設けた外部電極部によりリードフレームと接合する
ことができ、従来のような金属細線を使用した場合の金
属細線の高さ制限を受けず、薄型化を実現した半導体装
置である。またリードフレームのリード部と半導体素子
との間に一定距離を設ける必要もないので、小型化を実
現した半導体装置である。As described above, the semiconductor device of the present invention can be joined to the lead frame by the external electrode portion provided on the semiconductor element, and the height of the metal thin wire is restricted when the metal thin wire is used as in the prior art. It is a semiconductor device that has not been received and has realized a thin structure. Further, since it is not necessary to provide a fixed distance between the lead portion of the lead frame and the semiconductor element, the semiconductor device can be miniaturized.
【００２４】また製造方法においては、予め組立工程の
前工程において、半導体素子に対して外部電極部を形成
しているので、組立工程では、リードフレームに接合す
るだけで、電気的接続工程を完了させることができ、金
属細線によるワイヤーボンディング工程を削除して、組
立工程の簡素化を実現できるものである。Further, in the manufacturing method, since the external electrode portion is formed on the semiconductor element in advance in the pre-process of the assembling process, the electrical connecting process is completed only by joining to the lead frame in the assembling process. Therefore, the wire bonding process using the fine metal wires can be eliminated, and the assembly process can be simplified.
【図１】本発明の一実施形態の半導体装置を示す断面図FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施形態の半導体装置を示す平面図FIG. 2 is a plan view showing a semiconductor device according to an embodiment of the present invention.
【図３】本発明の一実施形態の半導体装置の半導体素子
を示す断面図FIG. 3 is a sectional view showing a semiconductor element of a semiconductor device according to an embodiment of the present invention.
【図４】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 4 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図５】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 5 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図６】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 6 is a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図７】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.
【図８】従来の半導体装置を示す断面図FIG. 8 is a sectional view showing a conventional semiconductor device.
【図９】従来の半導体装置を示す平面図FIG. 9 is a plan view showing a conventional semiconductor device.
１ 半導体素子 ２ リードフレーム ３ ダイパッド部 ４ リード部 ５ 金属細線 ６ 封止樹脂 ７ 半導体素子 ８ リードフレーム ９ リード部 １０ 外部電極部 １１ 封止樹脂 １２ 電極パッド １３ 絶縁層 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Lead frame 3 Die pad part 4 Lead part 5 Metal thin wire 6 Sealing resin 7 Semiconductor element 8 Lead frame 9 Lead part 10 External electrode part 11 Sealing resin 12 Electrode pad 13 Insulating layer
Claims (6)
た半導体素子と、少なくとも前記半導体素子と前記リー
ド部の一部とを封止している封止樹脂とよりなる半導体
装置であって、前記半導体素子と各リード部とは前記半
導体素子の各電極パッドと接続した外部電極部により接
続されていることを特徴とする半導体装置。1. A semiconductor device comprising a semiconductor element bonded on each lead portion of a lead frame, and a sealing resin sealing at least the semiconductor element and a part of the lead portion, A semiconductor device, wherein the semiconductor element and each lead portion are connected by an external electrode portion connected to each electrode pad of the semiconductor element.
電極部は、その下層に各外部電極部どうしが短絡しない
ように、絶縁層を設けて各外部電極どうしが分離独立し
ている外部電極部であることを特徴とする請求項１記載
の半導体装置。2. The external electrode portion connected to each electrode pad of the semiconductor element is provided with an insulating layer so that the external electrode portions are separated and independent from each other so that the external electrode portions are not short-circuited under the external electrode portion. The semiconductor device according to claim 1, wherein the semiconductor device is a part.
電極部は、半導体素子上の電極パッドから半導体素子の
側面を経由して半導体素子の裏面まで設けられている外
部電極部であることを特徴とする請求項１記載の半導体
装置。3. The external electrode portion connected to each electrode pad of the semiconductor element is an external electrode portion provided from the electrode pad on the semiconductor element to the back surface of the semiconductor element via the side surface of the semiconductor element. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
面におよぶ領域に絶縁層を形成する第１の前処理工程
と、前記半導体素子に形成した絶縁層上に導電性材料に
より外部電極部を形成する第２の前処理工程と、前記半
導体素子に形成した各外部電極部とリードフレームのリ
ード部とを対応させて、前記リード部上に半導体素子を
搭載する第１の組立工程と、前記半導体素子およびリー
ド部の一部を含む外囲領域を封止樹脂により封止する第
２の組立工程とよりなることを特徴とする半導体装置の
製造方法。4. A first pretreatment step of forming an insulating layer in a region extending from the outside of an electrode pad region of a semiconductor element to a back surface thereof, and an external electrode portion made of a conductive material on the insulating layer formed in the semiconductor element. A second pretreatment step of forming a semiconductor element, and a first assembly step of mounting the semiconductor element on the lead portion by associating each external electrode portion formed on the semiconductor element with the lead portion of the lead frame, 2. A method of manufacturing a semiconductor device, comprising: a second assembly step of sealing an outer peripheral region including the semiconductor element and a part of the lead portion with a sealing resin.
縁性樹脂を形成する工程ですることを特徴とする請求項
４記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein the first pretreatment step of forming the insulating layer is a step of forming an insulating resin.
は、導電性樹脂を形成する工程ですることを特徴とする
請求項４記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 4, wherein the second pretreatment step of forming the external electrode portion is a step of forming a conductive resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8037724A JPH09232365A (en) | 1996-02-26 | 1996-02-26 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8037724A JPH09232365A (en) | 1996-02-26 | 1996-02-26 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09232365A true JPH09232365A (en) | 1997-09-05 |
Family
ID=12505459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8037724A Pending JPH09232365A (en) | 1996-02-26 | 1996-02-26 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09232365A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001110811A (en) * | 1999-10-08 | 2001-04-20 | Oki Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| JP2007012699A (en) * | 2005-06-28 | 2007-01-18 | Oki Electric Ind Co Ltd | Semiconductor device |
-
1996
- 1996-02-26 JP JP8037724A patent/JPH09232365A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001110811A (en) * | 1999-10-08 | 2001-04-20 | Oki Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| JP2007012699A (en) * | 2005-06-28 | 2007-01-18 | Oki Electric Ind Co Ltd | Semiconductor device |
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