JPH09223740A - Flattening of layer insulating film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure a sufficient wiring formation reliability by eliminating steep steps in a process of flattening a layer insulating film based on chemical- mechanical polishing with use of a 2-layer stopper. SOLUTION: A nondoped glass(NSG) film 21 of a low polishing rate is formed to cover a step pattern of gate electrodes 13-1 to 13-3 formed on a silicon-on- insulator(SOI) layer 15-1, 15-2. Further formed on a borophosphosilicate glass(BPSG) film 22 of a high polishing rate, on which an NSG film 23 of a low polishing rate is formed. In this case, the thicknesses of the NSG, BPSG and NSG films 21, 22 and 23 are set so that the highest level surface of the NSG film 21 in a dense pattern region 12 becomes nearly the same as the lowest level surface of the NSG film 23. The laminate is then entirely flattened by the CMP. Therefore, after the CMP process, there remains no steep step in the dense pattern region 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of flattening an interlayer insulating film formed on a stepped pattern of an underlayer, and more particularly to a CMP (Chemical and Mec.
hanical Polishing: A method for planarizing an interlayer insulating film using a chemical mechanical polishing method.

[0002]

2. Description of the Related Art With the miniaturization and high integration of semiconductor devices, demands for processing techniques in LSI (Large Scale Integrated circuit) chip manufacturing processes are becoming more and more severe. In particular, in recent years, in pattern formation by a lithographic process and pattern processing by dry etching, it is required to improve the degree of integration and further improve a margin in a region close to a limit.

On the other hand, as the degree of device integration increases,
The number of wiring layers increases, and along with this, the steps of the device also increase. Therefore, DOF in the lithography process
(Depth of focus) Decrease in margin and step coverage of step portion in dry etching process (step coverage)
Problems such as stringer-like residue of the metal layer caused by deterioration of

Of these, the former problem (the problem of a decrease in the DOF margin in the lithography process) is that when the steps on the device surface become large, a resist mask is applied and formed on the entire surface including these steps, and exposure is performed by a stepper exposure apparatus. In this case, the focus range of the optical system of the stepper device is limited to a narrow range, and a clear exposure pattern cannot be obtained.

The latter problem (problem of stringer-like metal layer residue) is as follows. For example, FIG.
As shown in FIG. 3, when the insulating film 102 is formed so as to cover the pattern 101 such as the metal wiring or the gate electrode formed on the lower layer 100 such as the interlayer insulating film or the silicon substrate, the step portion of the pattern 101 is formed. The step coverage is expressed as a ratio A / B of the film thickness A to the film thickness B, where A is the film thickness of the insulating film 102 in B and B is the film thickness of the insulating film 102 in the portion away from the step. It is desirable that this value be "1", but if the level difference of the wiring pattern becomes large, this value will also decrease. In such a state, Blk-W for filling the contact hole
When a (blanket-tungsten) layer or the like is formed and etching is performed, the stepped portions 103 to 10 of the pattern 101 are formed.
Bl in 5 (especially the space 104 between dense patterns)
A stringer-like residue of the kW layer remains. Therefore, due to the presence of this stringer-like metal layer residue,
The metal wiring patterns formed thereafter will be short-circuited.

With respect to such a problem, in recent years, research has been actively conducted on a planarization process for an interlayer insulating film and wiring, and an improvement measure has been proposed. In particular, in order to improve the DOF margin in the lithography process by achieving a global flattened shape, a flattening technique for an interlayer insulating film using the CMP method is in the limelight. If the interlayer insulating film is completely planarized by this technique, not only the DOF margin can be improved, but also the amount of overetch required for dry etching can be reduced, and the metal film formation as described above can be performed. It is also possible to avoid the problem of deterioration in the reliability of the wiring due to the decrease in step coverage over time.

As such a CMP flattening technique, for example, the specification of the present applicant (Japanese Patent Application No. 06-28734).
As described in No. 1), there is a so-called two-layer stopper CMP flattening method. This method is, for example, BPSG
CMP polishing is performed after forming an interlayer insulating film of sandwich structure in which a film with a high polishing rate such as (boron, phosphorus, silicate, glass) is sandwiched by a film with a low polishing rate such as NSG (non-doped glass), etc. By doing so, the steps of the gate electrode and the like are removed. By utilizing the difference in the polishing rates of the two types of silicon oxide films, the in-plane distribution of the polishing rate is absorbed and the margin for detecting the polishing end point is provided. It can be increased. According to this technique, it is possible to essentially avoid the non-uniformity portion caused by polishing as the wafer diameter increases,
It is expected that this technology will become more and more important in the future.

The CMP flattening method using the above-mentioned two-layer stopper will be described below with reference to FIGS. 10 and 11.

As shown in FIG. 10, in the semiconductor device which is the target of this CMP flattening technique, an isolated pattern region 211 in which gate electrode patterns are not dense and a dense pattern region 212 in which gate electrode patterns are dense. And include. The base of this semiconductor device is a single crystal silicon SOI (Silicon-On-Insulator) layer 215-1, 2 near the surface of an insulating layer substrate 214 such as a silicon oxide layer.
15-2 is formed and configured. Of these, a single gate electrode 213-1 is formed on the SOI layer 215-1 in the isolated pattern region 211 via the gate insulating film 220 made of a silicon oxide film, and the dense pattern region 2 is formed.
On the 12th SOI layer 215-2.
Two gate electrodes 21 arranged with a small interval between
3-2 and 213-3 are formed. These gate electrodes 213-1 to 213-3 are composed of a polycrystalline silicon layer 216 on the lower layer side and a tungsten silicon (WSi) layer on the upper layer side.
Offset layer 218 made of an insulating film such as a silicon oxide film is formed on the silicide layer 217.
And side walls 219 made of an insulating film such as a silicon oxide film are formed on both side surfaces. Although not shown, each of the gate electrodes 213-1 to 213-1 is formed in a shallow region near each surface of the SOIs 215-1 and 215-2.
Impurity diffusion regions are selectively formed in a self-aligned manner with the sidewalls 219 of 213-3 to form source / drain regions.

On a substrate having such a gate electrode pattern, first, an NSG film 221 containing no impurities is formed as a first insulating film so as to cover the entire substrate,
A BPSG film 222 as a second insulating film is formed thereon, and an NSG film 22 as a third insulating film is further formed thereon.
Form 3 Of these, the BPSG film 222 is N
It has a property that it is more easily polished (the polishing rate is faster) than the SG films 221 and 223. In a normal production line, these insulating films are formed by the atmospheric pressure CVD method from the viewpoint of improving the throughput.

Here, the highest surface of the first insulating film (NSG film 221) in the isolated pattern area 211 is the first stopper surface, and the gate electrode 2 in the isolated pattern area 211.
13-1 The uppermost insulating film (NSG) formed on the part other than 13-1.
When the lowest surface of the film 223) is called a second stopper surface, the NSG film 221, the BPSG film 222 and the NSG film 221 are formed.
The film thickness of each film 223 is set so that the height of the first stopper surface and the height of the second stopper surface match. At this time, since the step coverage of the insulating film formed by the atmospheric pressure CVD method is not good, the lowest surface of the uppermost insulating film (NSG film 223) in the dense pattern region 212 is the lowermost insulating film (NSG film 221). The height is lower than the height of the highest surface of the two stopper surfaces, and the two stopper surfaces do not match.

Next, as shown in FIG. 11, CMP polishing is performed according to the height of the first stopper surface in the isolated pattern region 211. As a result, the isolated pattern region 21
In No. 1, flattening is almost complete. On the other hand, in the dense pattern region 212, the gate electrode 213-
Areas other than 2, 213-3 are polishing surfaces (first stopper surface)
It remains in a lower state, resulting in a step. These steps are
It is quite steep reflecting the poor step coverage of the insulating film formed by the atmospheric pressure CVD method. In particular, a steep and relatively large step remains in the region between the two gate electrodes 213-2 and 213-3.

After that, a metal layer of Blk-W or the like is formed and etched to fill the contact hole, and then a metal wiring layer made of aluminum or the like is formed and patterned.

[0014]

As described above, according to the CMP flattening technique, the DOF margin in the lithography process can be improved by the global flattening, and the polishing rate of two kinds of silicon oxide films can be improved. By utilizing the difference, it is possible to absorb the in-plane distribution of the polishing rate or increase the margin for detecting the polishing end point.

However, as described above, in the conventional method, the thickness of each of the three insulating films formed in the sandwich structure is based on the step in the isolated pattern region 11 and the height of the first stopper surface and the second stopper surface. Since the heights of the surfaces are aligned with each other, the two stopper surfaces are not aligned in the dense pattern area 12, and as shown in FIG.
A steep step remains even after MP polishing. If the contact hole filling metal film is formed and the sputter etching is performed with such a steep step portion remaining, the angle of view at the corner portion of the step is small even if the step size is small. Therefore, the number of incident ions to that portion is extremely reduced and the sputter rate is lowered. For this reason, as shown in FIG. 11, the stringer-like etch residues 25 to 27 of the contact hole filling metal film remain in these step portions, which causes a short circuit between wirings. It was

The present invention has been made in view of the above problems, and its object is to eliminate the steep step in the planarization process of the interlayer insulating film using the CMP method using the two-layer stopper, and to improve the reliability of wiring formation. It is to provide a method of planarizing an interlayer insulating film that can be sufficiently secured.

[0017]

According to a method of planarizing an interlayer insulating film of the present invention, a first insulating film having a relatively low polishing rate is formed so as to cover a pattern having a step formed on a semiconductor substrate. Forming step, forming a second insulating film having a relatively high polishing rate on the first insulating film, and forming a third insulating film having a relatively low polishing rate on the second insulating film. A top surface of the first insulating film in the dense pattern region of the semiconductor substrate, including a step of forming the third insulating film and a step of flattening a step on the surface of the semiconductor substrate by chemical mechanical polishing after forming the third insulating film. Is so set that the film thicknesses of the first to third insulating films are set so as to be substantially the same height as the lowest surface of the third insulating film.

In this flattening method for the interlayer insulating film, the second insulating film having a high polishing rate is sandwiched between the first insulating film and the third insulating film having a slow polishing rate on the step pattern on the semiconductor substrate. An interlayer insulating film having a sandwich structure is formed, and a step on the surface of the semiconductor substrate after forming the third insulating film is flattened by a chemical mechanical polishing method. At this time,
The film thickness of each insulating film is set such that the highest surface of the first insulating film and the lowest surface of the third insulating film have substantially the same height with reference to the dense pattern region.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view for explaining a method of planarizing an interlayer insulating film according to one embodiment of the present invention.

As shown in FIG. 1, the semiconductor device which is the subject of the present method has an isolated pattern region 211 in which the gate electrode patterns are not dense, as in the case of FIG.
And a dense pattern region 212 in which the pattern of the gate electrode is dense. The base of this semiconductor device is formed by forming SOI layers 13-1 and 13-2 made of single crystal silicon in the vicinity of the surface of an insulating layer substrate 14 such as a silicon oxide layer. SO
A single gate electrode 13-1 is formed on the I layer 13-1 via a gate insulating film 20 made of a silicon oxide film, and the gate insulating film 20 is formed on the SOI layer 13-2 in the dense pattern region 12. Two gate electrodes 13-2 and 13-31 are formed with a small space between them. These gate electrodes 13-1 to 13-3 are composed of a lower layer polycrystalline silicon layer 16 and an upper layer silicide layer 17 made of tungsten silicon or the like. An offset layer 18 made of an insulating film such as a silicon oxide film is formed on each gate electrode 13-1 to 13-3, and silicon oxide is formed on both side surfaces of each gate electrode 13-1 to 13-3. A sidewall 19 made of an insulating film such as a film is formed. Although not shown, the SOI15-
Impurity diffusion regions are selectively formed in the shallow regions near the surfaces of the gate electrodes 1 and 15-2 in a self-aligned manner with the sidewalls 19 of the gate electrodes 13-1 to 13-3 to form source / drain regions. doing. The offset layer 18 is
When forming a dual gate type semiconductor device (where MOS transistors formed in one semiconductor device have different conductivity types), impurities are introduced into the gate during ion implantation for source / drain formation. Is formed, and the thickness of the sidewall 19 as a spacer of the LDD structure is ensured to prevent a short circuit between the gate and the contact at the time of forming the self-aligned contact.

On a substrate having such a gate electrode pattern, an NSG film 21 which is a first insulating film is first formed so as to cover the entire substrate, and a BPSG which is a second insulating film is formed thereon. A film 22 is formed, and an NSG film 23 which is a third insulating film is further formed thereon. Of these, BP
The SG film 22 has a property that the polishing rate by the CMP method is higher than that of the NSG films 21 and 23 and that it is relatively easily polished. From the viewpoint of improving the throughput, these insulating films are formed under atmospheric pressure CVD (Chemical Vapor Deposition) with high deposition rate.
position: chemical vapor deposition) method.

In this embodiment, the NSG film 21 and BPS are
As shown in FIG. 1, the film thicknesses of the G film 22 and the NSG film 23 are set so that the highest surface of the NSG film 21 in the dense pattern region 12 is almost the same height as the lowest surface of the NSG film 23. This is set, and this surface is used as a stopper surface in CMP polishing. In this case, in the isolated pattern area 11, NS
The highest surface (first stopper surface) of the G film 21 is the NSG film 23.
Is formed at a position lower than the lowest surface (second stopper surface) of the two stopper surfaces.

Next, as shown in FIG. 2, CMP polishing is performed according to the height of the stopper surface in the dense pattern region 12. As a result, the dense pattern area 12 is almost completely flattened, and a steep step unlike the conventional case does not occur. On the other hand, in the isolated pattern region 11, as shown in FIG. 2, since the high portion is easily polished and removed more quickly, the isolated pattern (gate electrode 1
3-1) and the vicinity thereof, B is reached until the highest surface of the NSG film 21, which is the first stopper surface, is exposed.
The PSG film 22 is polished, but in other regions, the polishing does not proceed due to the existence of the NSG film 23 having a slow polishing rate, and eventually the lowest surface (second stopper surface) of the NSG film 23.
Remain. At this time, a steep step is unlikely to occur due to the characteristic of CMP polishing that the polishing rate of the high corner portion is high, and the step between the first stopper surface and the second stopper surface becomes relatively gentle.

After that, a metal layer of Blk-W or the like is formed to fill the contact hole and etched to form a metal wiring layer of aluminum or the like, and this is patterned. At this time, since a steep step is not formed in the dense pattern region 12, a stringer-like etch residue of the contact hole filling metal film does not remain in the step portion as in the conventional case. Further, although some level difference is generated in the isolated pattern region 11, since it is not steep as described above, a stringer-like etch residue of the contact hole filling metal film hardly remains at the level difference part. Even if some such etch residue remains, since the wiring pattern is sparse in the isolated pattern region 11, there is almost no short circuit between the wirings that occurs in the dense pattern region 12. This does not reduce the yield in the wiring process.

As described above, according to the flattening method of the interlayer insulating film of the present embodiment, the DOF margin in the lithography process is improved by the global flattening, and the difference in the polishing rate between the two kinds of silicon oxide films is utilized. By doing so, it is possible to absorb the in-plane distribution of the polishing rate, expand the margin for detecting the polishing end point, and prevent the formation of a sharp step in the dense pattern region 12. Therefore, it is possible to effectively prevent a short circuit between wirings due to a stringer-like etch residue of the contact hole filling metal film, which is a problem in the conventional CMP method using a two-layer stopper, and to secure the reliability of wiring formation. can do.

Next, a semiconductor manufacturing method using the interlayer insulating film planarizing method according to the present invention will be described in more detail. Here, for the sake of simplification of description, only the dense pattern area 12 will be illustrated and described.

First, as shown in FIG. 3A, the SOI layer 15-made of, for example, single crystal silicon containing P-type impurities is formed near the surface of the insulating layer substrate 14 made of a silicon oxide layer (SiO ₂ ) or the like. 2 is selectively formed to form an SOI substrate. The SOI substrate is formed by, for example, a wafer bonding method.

Next, as shown in FIG. 3B, a gate insulating film 20 such as a silicon oxide film is formed to a thickness of about 9 nm, and then a polycrystalline silicon layer 16 having a thickness of about 70 nm is formed.
And a silicide layer 17 of tungsten silicon or the like having a film thickness of about 70 nm, and further 120 n
The offset layer 18 having a thickness of about m is formed. And
By the selective etching using the RIE (Reactive Ion Etching) method or the like, the offset layer 18 and the silicide layer 1 are formed.
7 and the polycrystalline silicon layer 16 are patterned to form S
Gate electrodes 13-2 and 13-3 are formed on the OI layer 15-2. Of course, although not shown, the gate electrode 13 is also formed on the SOI layer 15-1 in the isolated pattern region 11 at the same time.
-1 is formed. In the following description, the description of the isolated pattern area 11 will be omitted.

Next, as shown in FIG. 3C, the SOI
In the shallow region near the surface of the layer 15-2, the gate electrode 13-
2. N-type impurities are selectively ion-implanted in a self-aligning manner with 2, 13-3 to form LDD (Lightly Doped Drain) regions.
^- after forming a diffusion layer 25, the silicon oxide film is formed on the entire surface is anisotropically etched so, the sidewalls 19 on the side surfaces of the gate electrodes 13-2 and 13-3 and the offset layer 18 formed To do. At this time, most of the gate insulating film 20 on the N ⁻ type diffusion layer 25 is also removed.
Further, in a self-aligned manner with the sidewall 19,
N-type impurities are ion-implanted into a shallow region near the surface of the SOI layer 15-2 to form a high-concentration N ⁺ -type diffusion layer 26 serving as a source / drain region. As a result, two NMOS transistors having the LDD structure are formed in the dense pattern region 12.

Next, as shown in FIG. 4A, the normal pressure C
After the NSG film 21 having a thickness of about 200 nm is formed on the entire surface by the VD method, the BPSG film 22 having a thickness of about 300 nm is formed on the entire surface as shown in FIG. As shown in c), the NSG film 23 having a film thickness of about 50 nm is formed on the entire surface. The conditions for forming each insulating film at this time are as follows, for example. First, the NSG film 21
For the above, the substrate temperature was set to 430 ° C. under atmospheric pressure, and the gas flow rates were monosilane (SiH ₄ ), oxygen (O ₂ ), and nitrogen (N ₂ ) 30, 540, respectively.
23000 cc / min. For the BPSG film 22, the substrate temperature is set to 380 ° C. under atmospheric pressure, and the gas flow rates are monosilane (SiH ₄ ), silane (B ₂ H)
₆ ), phosphine (PH ₃ ), oxygen (O ₂ ) and nitrogen (N ₂ ) 40, 2.0, 5.9 and 360, respectively.
It is 0.19000 cc / min. The NSG film 23 is formed under the same conditions as the NSG film 21.

Conventionally, the thickness of the BPSG film 22 is set to 210 n.
Although the two stopper surfaces in the isolated pattern area 11 are aligned with each other at about m, in the present embodiment,
Considering the decrease in the step coverage of the BPSG film 22 in the dense pattern region 12, the BPS in the flattened portion is taken into consideration.
The thickness of the G film 22 is set to about 300 nm, which is slightly thicker than in the past. As described above, the reason why the thickness is slightly thick is that the step coverage of the BPSG film 22 is slightly reduced when the aspect ratio is not so high as in the gate electrode.

Next, as shown in FIG. 5A, the entire surface is polished by the CMP method to mainly remove the high parts of the NSG film 23 and the BPSG film 22 to planarize the entire surface. In this CMP method, an abrasive is suspended in a solvent (water or the like), and the solvent itself has the ability to chemically etch an object to be polished, and the polishing treatment is performed using a polishing cloth or the like. In addition to being mainly used for mirror polishing of silicon wafers, in recent years, it has also been used as a flattening method for VLSI (Very High Integrated Circuit).
In this embodiment, polishing is performed under the following conditions. For example, as the polishing pad, a hard type (for example, commercially available under the trade name Suba800) which is a non-woven cloth made of a wet foam and treated with a secondary resin is used, and a silica-based slurry (polishing liquid) ( For example, the product name G3250) is supplied at a rate of 30 cc / min. Also, for example, the pressure is 160 g / cm
² and the platen rotation speed is 38 rpm. However, the conditions are not limited to those shown here, and appropriate conditions can be selected as necessary.

By this CMP process, as shown in FIG. 5 (a), a steep step is not formed in the dense pattern region 12, although a slight amount is not formed, and almost complete flattening is achieved.
Of course, as described in FIG. 2, the isolated pattern area 1
No sharp step is formed in No. 1, but only a slightly gentle step is formed.

Then, as shown in FIG. 5B, a PS film having a film thickness of about 200 nm is formed on the flattened interlayer insulating film so as to have an interlayer film thickness required for a final device.
A G (phosphorus silicate glass) film 28 is formed. The conditions for forming the PSG film 28 are, for example, that the substrate temperature is set to 390 ° C. under atmospheric pressure, and the gas flow rates are monosilane, phosphine, oxygen and nitrogen of 35, respectively.
2.8,670,22000 cc / min. In the subsequent steps, after forming a contact hole according to a normal process, the contact hole is filled with a metal layer such as Blk-W, and a metal wiring layer such as aluminum is formed as an upper layer.

Next, a method of planarizing an interlayer insulating film according to another embodiment of the present invention will be described with reference to FIGS. The present embodiment targets a metal wiring pattern such as aluminum on the interlayer insulating film, and flattens the interlayer insulating film formed so as to cover the metal wiring pattern by the CMP method. Note that, also in the present embodiment, illustration of the isolated pattern region of the wiring is omitted,
Only the dense pattern area of the wiring will be illustrated and described.

First, as shown in FIG. 6A, an interlayer insulating film 32 such as a silicon oxide film is formed on a semiconductor substrate 31. Here, the semiconductor substrate 31 is assumed to be a substrate in which the surface step of the interlayer insulating film in the gate portion is flattened by the flattening method shown in the above embodiment.

Next, as shown in FIG. 6B, a metal wiring layer made of an aluminum-based alloy is deposited and formed on the interlayer insulating film 32, and then this is patterned and arranged with a minute interval. The wiring layers 33-1 and 33-2 are formed. This wiring layer is, for example, Ti in order from the lower layer side.
(Titanium) / TiN (Titanium nitride) / Ti / A
It has a 7-layer structure of l-Cu / Ti / TiN / Ti,
The film thickness of each layer is, for example, 20 nm / 20 nm /
5 nm / 500 nm / 5 nm / 200 nm / 5 nm. Therefore, the total step difference of the wiring layers 33-1 and 33-2 is about 650 nm.

Next, as shown in FIG. 6C, as in the case of the above-described embodiment, the NSG film 34 having a thickness of about 200 nm is formed on the entire surface by the atmospheric pressure CVD method, and thereafter, As shown in FIG. 7A, a BPSG film 35 having a film thickness of about 900 nm is formed on the entire surface, and further, an NSG film 36 having a film thickness of about 100 nm is formed on the entire surface as shown in FIG. 7B. Form. The conditions for forming each insulating film at this time are the same as those in the above-described embodiment.

Conventionally, the film thickness of the BPSG film 35 is 550 n.
Although the two stopper surfaces in the isolated pattern area 11 are aligned with each other at about m, in the present embodiment,
In consideration of the decrease in the step coverage of the BPSG film 35 in the dense pattern region, the film thickness of the BPSG film 35 in the flattened portion is set to about 900 nm, which is considerably thicker than in the past. In this way, I made it quite thick,
The space between the wiring layers 33-1 and 33-2 is usually 1 μm or less, and the aspect ratio of the stepped region between both wirings is considerably high. This is because the thickness is suitable.

Next, as shown in FIG. 7C, the entire surface is polished by the CMP method to remove the high portions of the NSG film 36 and the BPSG film 35 to flatten the entire surface. The polishing conditions in this case are similar to those in the above-described embodiment, but are not limited thereto, and it is possible to select appropriate conditions as necessary.

By this CMP step, as shown in FIG. 7C, a steep step is not formed at all in the dense pattern area, and almost complete flattening is achieved. Of course, no steep step is formed in the isolated pattern region (not shown), and only a slightly gentle step is formed.

Then, as shown in FIG. 8, the NSG film 3 having a film thickness of about 300 nm is formed on the planarized interlayer insulating film so as to have an interlayer film thickness required for a final device.
7 is formed. In the subsequent steps, after forming a contact hole according to a normal process, the contact hole is filled with a metal layer such as Blk-W, and a metal wiring layer such as aluminum is formed as an upper layer.

Although the present invention has been described above with reference to some embodiments, the present invention is not limited to these embodiments and can be variously modified within the equivalent range. For example, in each of the above embodiments, the gate step and the aluminum alloy wiring step are targeted, but the present invention is not limited to this, and for example, a step pattern in which capacitors and the like are densely arranged is also targeted.

In the above embodiment (FIGS. 1, 2 and 3 to 5), the case where the gate step is formed on the SOI substrate has been described, but the same applies to the case of a normal bulk silicon substrate. is there. Further, the film thickness of each interlayer insulating film is merely one example described, and it is needless to say that it is appropriately changed according to the density of the pattern and the degree of step coverage of the CVD film.

As the first and third insulating layers, C
Although it has been described that the NSG film deposited by the VD method is used, the present invention is not limited to this.
Any insulating film having a polishing rate lower than that of the insulating film may be used, and for example, a silicon nitride film (Si ₃ N ₄ ) may be used. Further, as the second insulating film, B deposited by the CVD method
Although it is described that the PSG film is used, the present invention is not limited to this, and any film having a higher polishing rate than the first and third insulating films may be used.
Silicate glass) and BSG (boron silicate
Glass) or the like.

[0047]

As described above, according to the method of flattening an interlayer insulating film of the present invention, a second insulating film having a high polishing rate and a first polishing layer having a low polishing rate are formed on a step pattern on a semiconductor substrate.
When forming an interlayer insulating film having a sandwich structure sandwiched between the third insulating film and the third insulating film, the highest surface of the first insulating film and the lowest surface of the third insulating film are defined with reference to the dense pattern area. Since the thicknesses of the respective insulating films are set so that they have substantially the same height, after the steps on the surface of the semiconductor substrate after the third insulating film is formed are flattened by chemical mechanical polishing, There is no inconvenience that a steep step remains in the dense pattern area. Therefore, the over-etching time at the time of processing the wiring of the upper layer can be minimized, and the processing margin can be increased. Further, when a step of forming a metal layer for filling the contact hole and removing the portion other than the contact portion by etching is performed thereafter, the metal layer does not remain as a stringer-like residue in the step portion,
There is an advantage that the reliability of the wiring formation can be secured without any inconvenience such as a short circuit defect between the wirings in the upper layer or a disconnection of the wiring.

[Brief description of drawings]

FIG. 1 is a device sectional view for illustrating a method for planarizing an interlayer insulating film according to an embodiment of the present invention.

FIG. 2 is another element cross-sectional view for explaining the method of planarizing the interlayer insulating film according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step in a semiconductor manufacturing method to which the interlayer insulating film planarizing method according to the embodiment of the present invention is applied.

FIG. 4 is a sectional view illustrating a step following FIG. 3;

FIG. 5 is a cross-sectional view illustrating a process following the process in FIG.

FIG. 6 is a cross-sectional view showing a step in a semiconductor manufacturing method to which an interlayer insulating film planarizing method according to another embodiment of the present arrangement is applied.

FIG. 7 is a sectional view illustrating a step following FIG. 6;

8 is a cross-sectional view illustrating a process following the process in FIG.

FIG. 9 is a cross-sectional view for explaining a decrease in step coverage in a dense pattern area.

FIG. 10 is an element cross-sectional view for explaining a conventional method of planarizing an interlayer insulating film.

FIG. 11 is another element cross-sectional view for explaining the conventional flattening method of the interlayer insulating film.

[Explanation of symbols]

11: isolated pattern area, 12: dense pattern area, 1
3-1 to 13-3 ... Gate electrode, 14 ... Insulating layer substrate, 1
5-1, 15-2 ... SOI layer, 21, 34 ... NSG film (first insulating film), 22, 35 ... BPSG film (second insulating film), 23, 36 ... NSG film (third insulating film) film)

Claims (4)

[Claims] 1. A first polishing tool having a relatively low polishing rate so as to cover a stepped pattern formed on a semiconductor substrate.
Forming an insulating film, forming a second insulating film having a relatively high polishing rate on the first insulating film, and forming a third insulating film having a relatively low polishing rate on the second insulating film. Forming a third insulating film, and planarizing a step on the surface of the semiconductor substrate after forming the third insulating film by chemical mechanical polishing, the first insulating in the dense pattern region of the semiconductor substrate. The film thickness of the first to third insulating films is set so that the highest surface of the film has substantially the same height as the lowest surface of the third insulating film. Planarization method. 2. The method for planarizing an interlayer insulating film according to claim 1, wherein the first insulating film and the third insulating film are each formed of a silicon oxide film or a silicon nitride film containing no impurities. . 3. The planarization of the interlayer insulating film according to claim 1, wherein the second insulating film is composed of boron-phosphorus-silicate glass, phosphorus-silicate glass, or boron-silicate glass. Method. 4. The method of planarizing an interlayer insulating film according to claim 1, wherein the pattern is formed by a gate electrode or a metal wiring.