JPH09223656A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow positioning of a semiconductor mask to a pattern on a semiconductor substrate in a completely flattened semiconductor substrate. SOLUTION: A groove 400 is formed on a semiconductor substrate 10 whose width W1 may be above two times of a value of a piled film thickness Tsio2 of a silicon oxide film 60 and a film thickness (Tpoly + Twsi ) of a gate electrode 73 and a depth Dini may be above a value deducted from the sum of a value of a piled film width Tsio2 of the silicon oxide film 60 and a value of a film thickness (Tpoly + Twsi ) by a value of a depth Dsii of a groove 50 so as to form the grooves 50 and 401. Later, the silicon oxide film 60 is piled up so as to allow formation of a recessed part inspite of complete flattening by polishing so that this recessed part becomes a laminated key of a semiconductor mask in order to form the gate electrode 73.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art With the increase in density and miniaturization of semiconductor devices,
A chemical mechanical polishing method (CMP method) capable of realizing complete planarization is being applied to the planarization of trench isolation and the planarization of an interlayer insulating film.

A conventional trench isolation forming method to which the CMP method is applied will be described below with reference to FIG.

First, as shown in FIG. 8 (A), a thermal oxide film 21,
A silicon nitride film 25 is deposited and a resist pattern 350 is formed. Here, the silicon nitride film 25 functions as a polishing stopper film by CMP polishing.

Next, as shown in FIG. 8B, a trench isolation groove 50 is formed by a dry etching method, and at the same time, an alignment key groove 450 for aligning the semiconductor mask is formed.

Further, as shown in FIG. 8C, a silicon oxide film 60 is formed to fill the trench isolation trench 50 with an insulating film.

Next, as shown in FIG. 8D, the silicon oxide film 60 is polished by the CMP technique until the silicon nitride film 25 is exposed. At this time, since the silicon nitride film 25 is a polishing stopper film, polishing does not proceed more than necessary.

Next, as shown in FIG. 8E, the silicon nitride film 25 and the thermal oxide film 21 are removed, and the surface of the silicon substrate 10 can be completely planarized at this point.

Further, as shown in FIG. 8F, a gate oxide film 70, a polysilicon 71 and a tungsten silicide 72 are formed for forming a gate electrode.

[0010]

Usually, when aligning a semiconductor mask with a pattern formed on a semiconductor substrate, a special pattern formed for mask alignment is scanned using light or the like, The semiconductor mask is aligned by sensing surface irregularities. However, when the trench isolation is flattened as in the above-described conventional example, the surface unevenness cannot be captured in FIG. 8F because the surface is completely flattened, and the semiconductor mask Cannot be aligned.

In order to solve such a problem, when the film on the surface of the semiconductor substrate transmits light, there is a method of reading a special pattern formed for mask alignment by image recognition processing. When a metal material such as tungsten silicide 72 or aluminum alloy that does not transmit light as in the conventional example is formed on the surface of the semiconductor substrate, this method cannot be used and the semiconductor mask is used as a pattern on the semiconductor substrate. Cannot be aligned with.

Further, in the method of reading a special pattern formed for mask alignment by image recognition processing, interference fringes due to light diffraction occur due to variations in film thickness between chips due to process variations in the process. There is also a problem that the special pattern may not be surely recognized as an image.

The present invention has been made in view of the above technical problems, and a semiconductor mask is used even in a semiconductor substrate in which trench isolation or interlayer insulating film is completely planarized by applying the CMP technique. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be aligned with a pattern on a semiconductor substrate.

[0014]

The present invention is a method of manufacturing a semiconductor device in which a semiconductor element is formed on a semiconductor substrate, wherein a required width and a required width for aligning a semiconductor mask on the semiconductor substrate. Forming a positioning groove or a positioning hole having a depth, and positioning a first semiconductor mask in the positioning groove or the positioning hole to form a first mask pattern. , By etching at least the first groove or the first
Forming a hole, forming a first film on the semiconductor substrate, polishing the first film to planarize it, and forming a second film on the semiconductor substrate. In the process and the alignment groove or alignment hole,
A step of aligning a second semiconductor mask to form a second mask pattern and etching the second film, wherein the required width and the required width of the alignment groove or the alignment hole are formed. The depth is large enough to form a recess in the alignment groove or the alignment hole by the step of forming the second film.

According to the present invention, even in a semiconductor substrate which has been completely flattened by the CMP technique, a recess is formed by preventing the flattening of the alignment key portion of the semiconductor mask, and the semiconductor mask is formed by utilizing this recess. Can be easily aligned with the pattern on the semiconductor substrate.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a method for manufacturing a semiconductor device in which a semiconductor element is formed on a semiconductor substrate, which is used for aligning a semiconductor mask on the semiconductor substrate. A step of forming an alignment groove or an alignment hole having a required width and a required depth, and the alignment groove or the alignment hole,
Aligning a first semiconductor mask to form a first mask pattern and forming at least a first groove or a first hole by etching; and forming a first film on the semiconductor substrate. A step of polishing the first film to flatten it, a step of forming a second film on the semiconductor substrate, and a second semiconductor mask in the alignment groove or alignment hole. Align the second
Forming a mask pattern and etching the second film, the required width and required depth of the alignment groove or the alignment hole are determined by the step of forming the second film. The size is sufficient to form a recess in the alignment groove or the alignment hole by the above method. For example, in a semiconductor substrate in which the CMP technique is applied to flatten the trench isolation and the element region is completely flattened. A recess can be formed in the alignment key portion of the semiconductor mask, and the recess can be used to accurately align the semiconductor mask with the pattern on the semiconductor substrate.

According to a second aspect of the present invention, in the invention according to the first aspect, the positioning groove or the positioning hole is etched simultaneously with the etching of the first groove or the first hole. , The required width is larger than twice the sum of the film thicknesses of the first film and the second film, and the required depth is the sum of the film thickness and the first groove or It is larger than the difference with the depth of the first hole,
As a result, even in the semiconductor substrate in which the element region is completely flattened, a concave portion can be formed in the alignment key portion of the semiconductor mask, and the concave portion can be used to accurately form the semiconductor mask in a pattern on the semiconductor substrate. It becomes possible to align.

According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method for forming a semiconductor element on a semiconductor substrate, wherein a required width for aligning a semiconductor mask on the semiconductor substrate is set. Forming an alignment groove or alignment hole having a required depth, and
Forming a groove or a first hole, and aligning a first semiconductor mask with the alignment groove or the alignment hole to form a first mask pattern, and at least a second mask is formed by etching. Groove or second
Forming a hole, forming a first film on the semiconductor substrate, polishing the first film to planarize it, and forming a second film on the semiconductor substrate. In the process and the alignment groove or alignment hole,
A step of aligning a second semiconductor mask to form a second mask pattern and etching the second film, wherein the required width and the required width of the alignment groove or the alignment hole are formed. The depth is large enough to form a recess in the alignment groove or the alignment hole by the step of forming the second film. For example, the CMP technique is applied to flatten the trench isolation, Even in a semiconductor substrate that has been completely flattened in a region, a recess can be formed in the alignment key portion of the semiconductor mask, and the recess can be used to accurately align the semiconductor mask with the pattern on the semiconductor substrate. Is possible. And the first
Since the depth of the groove or the first hole is different from that of the second groove or the second hole, it is possible to form trench patterns having different depths, and to miniaturize and highly integrate the device. It is effective in planning.

According to a fourth aspect of the present invention, in the invention according to the third aspect, the step of forming the second groove or the second hole includes the step of forming the second groove or the second hole. Simultaneously with the etching, the alignment groove or the alignment hole is etched, and the required width is larger than twice the sum of the film thicknesses of the first film and the second film. The required depth is larger than the difference between the sum of the film thicknesses and the depth of the second groove or the second hole, whereby a semiconductor in which the element region is completely flattened. Also in the substrate, a concave portion can be formed in the alignment key portion of the semiconductor mask, and the concave portion can be used to accurately align the semiconductor mask with the pattern on the semiconductor substrate. Different trench patterns Can be formed, the miniaturization of the element,
This is effective in achieving high integration.

The invention according to claim 5 of the present invention is the invention according to claim 1.
In the invention described in any one of (1) to (4), the second film is a laminated film, and a concave portion can be formed in the alignment key portion of the semiconductor mask of the laminated film. The mask can be accurately aligned with the pattern on the semiconductor substrate.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a semiconductor element is formed on a semiconductor substrate, the required width for aligning a semiconductor mask on the semiconductor substrate, A step of forming an alignment groove or an alignment hole having a required depth, a step of forming a film on the semiconductor substrate substrate and polishing and flattening the film, the alignment groove or the alignment A hole for forming a mask pattern by aligning a semiconductor mask, and etching the film, the required width and required depth of the alignment groove or alignment hole, The size is large enough to form a recess in the alignment groove or the alignment hole in the step of forming the film. For example, the CMP technique is applied to planarize the interlayer insulating film. Even in the semiconductor substrate in which the element region is completely flattened, a concave portion can be formed in the alignment key portion of the semiconductor mask, and the concave portion is used to accurately align the semiconductor mask with the pattern on the semiconductor substrate. It becomes possible.

The invention according to claim 7 of the present invention is a method of manufacturing a semiconductor device in which a semiconductor element is formed on a semiconductor substrate, wherein a first groove or a first hole is formed on the semiconductor substrate, A step of embedding and polishing the first film to planarize it, a step of forming a second film on the semiconductor substrate and polishing and planarizing the second film, and a step for aligning the semiconductor mask. The alignment groove or the alignment hole having the width and the required depth of the second film or the first film.
And forming the second film by etching, the step of etching the second film to form a contact hole, and the step of forming a third film and etching to form the third film. Embedding in the contact hole,
A step of forming a fourth film on a semiconductor substrate, a semiconductor pattern is aligned with the alignment groove or the alignment hole to form a mask pattern, and the fourth film is etched to form a wiring. A step of forming the positioning groove or the positioning hole, wherein the required width and the required depth of the positioning groove or the positioning hole are recessed in the positioning groove or the positioning hole by the step of forming the fourth film. Is sufficient for forming the interlayer insulating film. For example, in the semiconductor substrate in which the CMP technique is applied to planarize the interlayer insulating film and the element region is completely planarized, a concave portion is formed in the alignment key portion of the semiconductor mask. It is possible to accurately align the semiconductor mask with the pattern on the semiconductor substrate by utilizing this recess.

According to an eighth aspect of the present invention, in the invention according to the seventh aspect, the required width is more than twice the sum of the film thicknesses of the third film and the fourth film. And the required depth is larger than the film thickness of the fourth film, so that even in the semiconductor substrate in which the element region is completely flattened, a recess is formed in the alignment key portion of the semiconductor mask. And the semiconductor mask can be accurately aligned with the pattern on the semiconductor substrate by utilizing this recess.

The invention according to claim 9 of the present invention is a method of manufacturing a semiconductor device in which a semiconductor element is formed on a semiconductor substrate, wherein an alignment having a required width and a required depth is performed on the semiconductor substrate. Forming a contact groove or an alignment hole and forming a contact hole; forming a first film and performing etching to fill the first film in the contact hole; A step of forming a second film, a first semiconductor mask is aligned with the alignment groove or the alignment hole to form a first mask pattern, and the second film is etched. A step of forming a wiring, a step of forming a third film on the semiconductor substrate, a step of polishing the third film to flatten it, and a step of forming a second groove in the alignment groove or the alignment hole. The by aligning the semiconductor mask 2
Forming a mask pattern and etching the third film to form a via hole, wherein the required width and required depth of the alignment groove or the alignment hole are The size is sufficient to form a recess in the alignment groove or the alignment hole in the step of forming the film of No. 3, and for example, CMP technology is applied to planarize the interlayer insulating film to completely flatten the element region. Also in the semiconductor substrate that has been subjected to the above step, a concave portion can be formed in the alignment key portion of the semiconductor mask, and the concave portion can be utilized to accurately align the semiconductor mask with the pattern on the semiconductor substrate.

According to a tenth aspect of the present invention, in the invention according to the ninth aspect, the required width is more than twice the sum of the film thicknesses of the first film and the third film. And the required depth is larger than the difference between the polishing amount of the third film and the thickness of the wiring, so that even in the semiconductor substrate in which the element region is completely flattened, the semiconductor mask A concave portion can be formed in the alignment key portion, and the concave portion can be used to accurately align the semiconductor mask with the pattern on the semiconductor substrate.

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a process sectional view of a method of manufacturing a semiconductor device according to a first embodiment of the present invention. This first embodiment includes a process corresponding to claim 1. It is a waste.

In the method of manufacturing a MOS transistor according to the first embodiment, first, as shown in FIG. 1A, a thermal oxide film 20 is formed on a silicon substrate 10 and a resist pattern is formed using a semiconductor mask. Form 300.

Next, as shown in FIG. 1B, the alignment key groove 4 for aligning the semiconductor mask is formed by dry etching using the resist pattern 300 as a mask.
00 is formed. The alignment key groove 400 is formed to have a required width and a required depth as described later.

Next, as shown in FIG. 1C, after removing the resist 300, a thermal oxide film 21 is formed and a silicon nitride film 25 is deposited to form a first mask pattern in claim 1. A resist pattern 301 is formed. Here, the semiconductor mask used for forming the resist pattern 301 is aligned by the alignment key groove 400. A resist opening is also provided on the alignment key groove 400.

Further, as shown in FIG. 1D, the silicon nitride film 25 is formed by using the resist pattern 301 as a mask.
The thermal oxide film 21 and the silicon substrate 10 are dry-etched to form the alignment key groove 401 and the first in claim 1.
A trench isolation groove 50 is formed as the groove of.

Next, as shown in FIG. 1E, a silicon oxide film 60 as a first film in claim 1 is deposited to a desired film thickness, and further, FIG. As shown, the silicon oxide film 60 is polished using the CMP technique until the silicon nitride film 25 is exposed. Here, the shallow trench 51 filled with the silicon oxide film 60 is formed. Further, although the trench isolation groove 50 is completely flattened by the flattening, the alignment key groove 400 has a required width and a required depth as described later, so that the alignment key 402 portion is It is not completely flattened and a recess is formed.

Next, as shown in FIG. 1G, the silicon nitride film 25 and the thermal oxide film 21 are removed by wet etching, and further, a gate electrode is formed as shown in FIG. 1H. In order to do so, a gate oxide film 70 is formed, and polysilicon 71 and tungsten silicide 72 as a second film in claim 1 are deposited. Then, a resist pattern 302 as a second mask pattern in claim 1 is formed. Here, the resist pattern 30
The semiconductor mask used to form 2 is an alignment key 40
Align to 2. The gate oxide film 70 may be included as the second film.

Next, as shown in FIG. 1I, the gate electrode 73 is patterned by dry etching.

Now, the required width and required depth of the alignment key groove 400 will be described. The required width and required depth of the alignment key groove 400 form the gate oxide film 70 shown in FIG.
After depositing the tungsten silicide 72 and the tungsten silicide 72, a recess for aligning the semiconductor mask for forming the resist pattern 302 is formed in the alignment key groove 400. It is set as follows.

Here, the width of the alignment key groove 400 is W ₁ , the initial depth shown in FIG. 1B is D _ini , and FIG.
The depth of the trench isolation trench 50 shown in (D) is D _sti , the deposition film thickness of the silicon oxide film 60 shown in FIG. 1 (E) is T _sio2 , and the polysilicon 71 shown in FIG. The deposited film thickness is T _poly , the deposited film thickness of the tungsten silicide 72 is T _wsi , and the sum of these film thicknesses is T ₁ (= T _sio2 + T _poly
+ T _wsi ), and an explanation will be given based on the enlarged sectional view of FIG. Note that FIG. 2 shows the alignment key groove 401 of FIG. 1D.

In FIG. 2, assuming that the film thickness in the width direction of the alignment key groove 401 is T ₂ , the alignment key groove 401
However, in order not to be embedded by the film, its width W
₁ needs to be W ₁ > 2 · T ₂ and the film thickness T ₂ in the alignment key groove 401 is T ₂ ≦ T _1. Therefore, the width W ₁ of the alignment key groove 401 is It will be shown by a formula.

W ₁ > 2 · T ₁ = 2 · (T _sio 2 + T _poly + T _wsi ) That is, the width W ₁ of the alignment key groove 401 _{depends on} the film thickness T _{sio 2 of the} silicon oxide film 60 and the film of polysilicon 71. Thickness T _poly
And a value greater than twice the sum of the film thickness T _wsi of the tungsten silicide 72.

On the other hand, the alignment key groove 40 shown in FIG.
The depth D ₁ of ₁ is the sum of the above-mentioned initial depth D _ini and the depth D _sti of the trench isolation groove 50, and the alignment key groove 4
_No. 01 has a depth D ₁ (= D _ini + D _sti ) in order to form a concave portion even if it is flattened, it is necessary that D ₁ > T ₁ is _satisfied. Depth D
_ini will be represented by the following equation.

D _ini > T ₁ -D _sti = (T _sio2 + T _poly +
T _wsi ) -D _sti, that is, the alignment key groove 400 shown in FIG.
The initial depth D _ini of the silicon oxide film 60 is T _sio2
When a deposited film thickness T _poly polysilicon 71, is larger than a value obtained by subtracting the depth D _sti trench isolation trench 50 from the sum of the deposited film thickness T _wsi tungsten silicide 72.

Thus, the width W ₁ of the alignment key groove 400 is
By setting the depth and the depth D _ini to the required width and required depth, the trench isolation trench 50 in the element region is formed.
Is not completely flattened by the flattening using the CMP technique, the alignment key groove 401 of the semiconductor mask is not completely flattened, and a concave portion is formed. The semiconductor mask can be easily aligned with the pattern on the substrate.

In the first embodiment, as shown in FIG. 1D, the alignment key groove 401 is also etched when the trench isolation groove 50 is formed by etching. 1B, the depth shown in FIG. 1D, that is, the depth D ₁ in FIG. 2 is formed in advance, and is adjusted when the trench isolation trench 50 is formed. The key groove 400 may be masked so as not to be etched.

In the first embodiment, the case where the alignment key has a groove pattern has been described.
The same can be applied to the hole-shaped pattern.

(Embodiment 2) FIG. 3 is a process sectional view of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. This second embodiment includes a process corresponding to claim 3. It is a waste.

In the manufacturing method of the second embodiment, first, as shown in FIG. 3A, a thermal oxide film 20 is formed on a silicon substrate 10 and a resist pattern 310 is formed using a semiconductor mask.

Next, as shown in FIG. 3B, a registration key groove 410 for aligning the semiconductor mask is formed by dry etching using the resist pattern 310 as a mask, and the n-well and p-type well are formed. Forming a well separating groove 52 as a first groove in claim 3 for electrically separating the well.

The alignment key groove 410 has a required width and depth described later, as in the first embodiment.

Next, as shown in FIG. 3C, after removing the resist 310, a thermal oxide film 21 is formed and a silicon nitride film 25 is deposited to form a first mask pattern in claim 3. Forming a resist pattern 311. Here, the semiconductor mask used to form the resist pattern 311 is aligned with the alignment key groove 410. Further, a resist opening is also provided on the alignment key groove 410 and the well separation groove 52.

Further, as shown in FIG. 3D, the silicon nitride film 25 is formed by using the resist pattern 311 as a mask.
The thermal oxide film 21 and the silicon substrate 10 are dry-etched to form the alignment key groove 411, the well isolation groove 53, and the trench isolation groove 5 as the second groove in claim 3.
Form 0. The width of the well separating groove 53 may be arbitrarily set so that it is completely filled with the silicon oxide film 60 and can be electrically separated. Normally, the width of the matching key groove 410 is set. The width is about 4 μm, whereas the width of the well separating groove 53 is 1 μm or less, so that the well separating groove 53 is completely filled.

Next, as shown in FIG. 3E, a silicon oxide film 60 as a first film in claim 3 is deposited to a desired film thickness, and further, FIG. As shown, the silicon oxide film 60 is polished using the CMP technique until the silicon nitride film 25 is exposed. Here, the shallow trenches 51 and the deep trenches 54 filled with the silicon oxide film 60 are formed. Also, the trench isolation groove 5
0 is completely flattened by flattening, but since the alignment key groove 410 has a required width and a required depth, the alignment key 412 is not completely flattened and a recess is formed. It

Next, as shown in FIG. 3G, the silicon nitride film 25 and the thermal oxide film 21 are removed by wet etching, and further, a gate electrode is formed as shown in FIG. 3H. To this end, a gate oxide film 70 is formed, polysilicon 71 and tungsten silicide 72 as a second film in claim 3 are deposited, and a resist pattern 312 as a second mask pattern in claim 3 is formed.
To form Here, the semiconductor mask used to form the resist pattern 312 is aligned with the alignment key 412. The gate oxide film 70 may be included as the second film.

Next, as shown in FIG. 3I, the gate electrode 73 is patterned by dry etching.

[0053] The combined key groove 410, as in the first embodiment described above, the width, the deposited film thickness T _sio2 of the silicon oxide film 60, a deposited film thickness T _poly polysilicon 71, a tungsten silicide 2 of the sum of 72 and the deposited film thickness T _wsi
Is more than doubled and its initial depth D _ini is
The deposited film thickness T _sio2 of the silicon oxide film 60 and the polysilicon 71
From the sum of the deposited film thickness T _poly of the tungsten silicide 72 and the deposited film thickness T _wsi of the tungsten silicide 72.
It is larger than the value obtained by subtracting _sti .

By thus setting the width and depth of the alignment key groove 410 to the required width and depth, the trench isolation groove 50 in the element region is flattened by the CMP technique. Even if completely flattened, the alignment key groove 410 of the semiconductor mask is not completely flattened, and a recess is formed. Even after polishing and flattening, the pattern on the semiconductor substrate can be easily formed on the semiconductor mask. Can be aligned.

Further, since the well separating groove 52 is also formed when forming the alignment key groove 410, two kinds of trench patterns having different depths are formed in the trench pattern for electrically separating the elements. can do. In general, the deeper the trench pattern is, the higher the isolation capability is, so that it is possible to easily realize the miniaturization and high integration of the device.

Also in the second embodiment, as in the above-described first embodiment, the depth of the alignment key groove in FIG. 3 (B) is formed to the depth shown in FIG. 3 (D). However, the alignment key groove may not be etched when the trench isolation groove is formed. Further, it is also possible to implement a matching key having a hole pattern.

(Third Embodiment) FIGS. 4A to 4C are process sectional views of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. In the third embodiment, a process corresponding to claim 6 is included. It is a waste.

In the manufacturing method of the third embodiment, first, as shown in FIG. 4A, a MOS transistor is formed in accordance with the method of the first embodiment, and the alignment key groove 4 is formed.
20 is formed in advance, and the alignment key groove 420 in the state of FIG. 4A has a required width and a required depth, as described later.

Next, in FIG. 4B, a silicon oxide film 61 is deposited to a desired film thickness, and as shown in FIG. 4C, the silicon oxide film 61 is formed by using the CMP technique. Are polished to flatten the surface. At this time, the alignment key groove 42
Since 0 has a required width and a required depth as described later, the alignment key 421 portion is not completely flattened and a recess is formed. Then, a resist pattern 320 is formed. Here, the semiconductor mask used to form the resist pattern 320 is aligned with the alignment key 421.

Next, as shown in FIG. 4D, the contact hole 80 is formed by dry etching using the resist pattern 320 as a mask.

Here, the required width and required depth of the alignment key groove 420 will be described. The alignment key groove 420 is for aligning the semiconductor mask forming the resist pattern 320 with the alignment key groove 420 after the silicon oxide film 61 shown in FIG. 4B is deposited and polished. It is large enough to form a recess,
Specifically, it is set as follows.

Here, as shown in FIG. 5, the width of the alignment key groove 420 is W ₂ , the depth is D ₂ , and the alignment key groove 4 is
20 is T ₃ , the thickness of the silicon oxide film 61 is T _D , the thickness of the silicon oxide film 61 after polishing is T, the polishing amount is T _E , and the thickness of the gate electrode 73 is T T. _{Assuming G} , the width W ₂ of the alignment key groove 420 is expressed by the following equation, as in the first embodiment.

W ₂ > 2 · T _D, that is, the width W ₂ of the alignment key groove 420 is larger than twice the deposited film thickness T _D of the silicon oxide film 61.

On the other hand, since the concave portion is formed in the alignment key groove 420 after the silicon oxide film 61 is polished and flattened, the deposited film thickness of the silicon oxide film 61 is as shown in FIG. T _D needs to be smaller than the sum of the depth D ₂ of the alignment key groove 420 and the film thickness T of the silicon oxide film 61 after polishing. That is, D ₂ + T> T _{D, and} therefore D ₂ > T _D −T. Here, the film thickness T of the silicon oxide film 61 after polishing is
The deposition thickness T _D of the silicon oxide film 61 is equal to the value obtained by subtracting the polishing amount T _E from the value obtained by adding T _G to the thickness of the gate electrode 73. That, T = T _D + T _G because it is -T _E above _{equations, D 2> T D -T =} T D -T D -T G + T E = T E -T G However, T _E> T _G Becomes

That is, the depth D of the alignment key groove 420
_{The value 2} is larger than the value obtained by subtracting the thickness T _G of the gate electrode 73 from the polishing amount T _E.

By thus setting the width and depth of the alignment key groove 420 to the required width and depth, the silicon oxide film 61, which is an interlayer insulating film formed immediately before the contact hole is formed, Even if completely flattened by the flattening using the CMP technique, the alignment key portion of the semiconductor mask is not completely flattened and a recess is formed. Therefore, even after polishing and flattening, the pattern on the semiconductor substrate can be easily formed. It is possible to align the semiconductor mask.

In the third embodiment, the alignment key groove for forming the contact hole of the third embodiment is formed in the alignment key groove portion for forming the MOS transistor according to the method of the first embodiment. Although the groove 420 is formed, as another embodiment of the present invention, an alignment key groove for forming the contact hole of the third embodiment at a position different from the alignment key groove of the first embodiment. 420 may be formed.

(Embodiment 4) FIG. 6 is a process sectional view of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. This fourth embodiment includes a process corresponding to claim 7. It is a waste.

In the manufacturing method of the fourth embodiment, first,
As shown in FIG. 6 (A), the shallow trench as the first groove in claim 7 in which the silicon oxide film 60 as the first film in claim 7 is buried and planarized by a known technique. Embedded layer 430 for the trench 51 and the matching key
Are formed, a gate electrode 73 is formed, a silicon oxide film 61 as a second film in claim 7 is deposited as an interlayer insulating film, and polished / planarized by the CMP technique.

Next, as shown in FIG. 6B, a resist pattern 330 for forming a contact hole.
To form Here, an opening is also provided on the embedding layer 430 for the alignment key. Although the silicon oxide film 61 is completely flattened in the element region, the alignment between the semiconductor mask for forming the resist pattern 330 and the pattern on the semiconductor substrate is performed in the above-described third embodiment. It is practicable if the semiconductor substrate is manufactured according to the above. That is, the resist pattern 330 of FIG. 6 (B) is formed by using the alignment key groove similar to that of the third embodiment not shown.

In the fourth embodiment, next, FIG.
As shown in FIG. 3, the contact hole 80 and the alignment key groove 431 for aligning the semiconductor mask are formed by dry etching using the resist 330 as a mask. The alignment key groove 431 has a required width and a required depth as described later.

Further, as shown in FIG. 6D, after removing the resist 330, a tungsten plug 81 is formed in the contact hole 80 as a third film in claim 7 by using the tungsten-embedded plug technique. Form. At this time, the tungsten sidewall 82 is formed in the alignment key groove 431, and the alignment key 432 is formed.

Next, as shown in FIG. 6 (E), as a fourth film in claim 7, a wiring material such as aluminum alloy 90 is deposited to a desired film thickness, and further, FIG. 6 (F). The resist pattern 331 as the mask pattern in claim 7 is formed as shown in FIG. Here, the semiconductor mask for forming the resist pattern 331 is aligned with the alignment key 432. That is, the alignment key groove 4
Since 31 has a required width and a required depth as described later, a recess is formed in the alignment key 432, and the semiconductor mask for forming the resist pattern 331 is
It is possible to align with the alignment key 432.

Next, as shown in FIG. 6G, the aluminum alloy 90 is dry-etched using the resist 331 as a mask to form the wiring 91.

Now, a required width and a required depth of the alignment key groove 431 will be described.

The width W ₄ of the alignment key groove 431 shown in FIG. 6C is the same as in the above-described embodiments.
Tungsten sidewall 82 shown in FIG.
Is larger than twice the sum of the width W _T and the deposited film thickness T _Al of the aluminum alloy 90 shown in FIG. 6 (E).

On the other hand, FIG. 6C of the alignment key groove 431.
The depth D ₄ shown in is the deposition thickness T _{Al of the} aluminum alloy 90.
Is greater than.

By thus setting the width and depth of the alignment key groove 431 to the required width and required depth, the silicon oxide film 61, which is an interlayer insulating film immediately before the formation of the contact hole, becomes Completely flattened by the flattening using the CMP technique. As a result, even after the aluminum alloy 90 is deposited, the alignment key portion of the semiconductor mask is not completely flattened and a concave portion is formed even if the surface has no unevenness. Even after the polishing and flattening, the semiconductor mask can be easily aligned with the pattern on the semiconductor substrate.

In the fourth embodiment, the alignment key groove 431 is formed by digging down the silicon substrate 10 as shown in FIG. 6C. However, as another embodiment of the present invention, silicon is used. The substrate 10 may be formed without digging.

Further, in the fourth embodiment, the case where the alignment key is the groove-shaped pattern has been described, but the same can be applied to the hole-shaped pattern.

(Fifth Embodiment) FIG. 7 is a process sectional view of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. This fifth embodiment includes a process corresponding to claim 9. It is a waste.

In the manufacturing method of the fifth embodiment, first,
As shown in FIG. 7A, a well-known technique is used to form a shallow trench 51 which is filled and planarized with a silicon oxide film 60, forms a gate electrode 73, and forms a silicon oxide film as an interlayer insulating film. The alignment key for aligning the contact hole having the tungsten plug 81 and the semiconductor mask having the tungsten side wall 83 with the tungsten as the first film according to claim 9 by depositing 61, polishing and planarizing by the CMP technique. Groove 4
40 is formed. The alignment key groove 440 has a required width and a required depth described later. The silicon substrate 10 may be dug in the alignment key groove 440. Further, the second aspect of claim 9
10. The wiring material as the film is etched to form the wiring 91, and the silicon oxide film 62 as the third film in claim 9 is formed.
To a desired film thickness.

Next, as shown in FIG. 7B, CM
Using the P technique, the silicon oxide film 62 is polished and completely flattened. Here, the matching key 441 is formed.

Further, as shown in FIG. 7C, a resist pattern 340 as a second mask pattern in claim 9 is formed. Resist pattern 3 here
The semiconductor mask for forming 40 is an alignment key 441.
Align with.

Now, a required width and a required depth of the alignment key groove 440 will be described.

The width W ₅ of the alignment key groove 440 shown in FIG. 7A is the same as that in the fourth embodiment described above.
2 which is the sum of the width W _T of the tungsten sidewall 83 and the value of the deposited film thickness T _sio2 of the silicon oxide film 62 shown in FIG.
Greater than double.

On the other hand, the alignment key groove 440 shown in FIG.
The depth D ₅ shown in is similar to that of the third embodiment described above.
The value is larger than the value obtained by subtracting the thickness of the wiring 91 from the polishing amount of the silicon oxide film 62.

By thus setting the width and depth of the alignment key groove 440 to the required width and depth,
The alignment key 441 is not completely flattened by polishing,
The semiconductor mask for forming the resist pattern 340 in which the concave portion is formed can be aligned with the alignment key 441.

That is, by setting the width and depth of the alignment key groove 440 as described above, the silicon oxide film 62, which is an interlayer insulating film formed after the wiring is formed, is
Even if the surface is completely flattened by the flattening using the P technique and the surface has no unevenness, the alignment key portion of the semiconductor mask is not completely flattened as described above, and thus the recessed portion is formed. Even after the formation, the semiconductor mask can be easily aligned with the pattern on the semiconductor substrate.

In the fifth embodiment, the case where the alignment key is the groove-shaped pattern has been described, but the same can be applied to the hole-shaped pattern.

Further, in the multi-layer wiring which has been completely flattened by using the CMP technique, the above-mentioned embodiment is realized by devising a device such as forming a pad by using a wiring material when forming the alignment key groove. Embodiment 4 or Embodiment 5
The position of the semiconductor mask can be aligned by applying.

[0092]

As described above, according to the present invention, since the alignment groove or the alignment hole having the required width and the required depth is formed, the CMP is performed for trench isolation and planarization of the interlayer insulating film. Even in the semiconductor substrate in which the technology is applied and the element region is completely flattened, a concave portion can be formed in the alignment key portion of the semiconductor mask, and the concave portion can be used to form the semiconductor mask into a pattern on the semiconductor substrate. It becomes possible to perform accurate alignment.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view for explaining the width and depth of the alignment key groove of FIG.

FIG. 3 is a process sectional view showing the method for manufacturing the semiconductor device in the second embodiment of the present invention.

FIG. 4 is a process sectional view showing the method for manufacturing the semiconductor device in the third embodiment of the present invention.

5 is an enlarged cross-sectional view for explaining the width and depth of the alignment key groove of FIG.

FIG. 6 is a process sectional view showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is a process sectional view showing the method for manufacturing the semiconductor device in the fifth embodiment of the present invention.

FIG. 8 is a process sectional view of a conventional example.

[Explanation of symbols]

10 Silicon Substrate 20, 21 Thermal Oxide Film 25 Silicon Nitride Film 50 Trench Separation Groove 51 Shallow Trench 52, 53 Well Separation Groove 54 Deep Trench 60, 61, 62 Silicon Oxide Film 70 Gate Oxide Film 71 Polysilicon 72 Tungsten Silicide 73 Gate electrode 80 Contact hole 85 Via hole 91 Wiring 400, 401, 411, 431, 450 Alignment key groove

Front page continued (72) Inventor Takashi Nakabayashi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor device in which a semiconductor element is formed on a semiconductor substrate, wherein an alignment groove having a required width and a required depth for aligning a semiconductor mask is provided on the semiconductor substrate. Or a step of forming a positioning hole, and a first step is performed in the positioning groove or the positioning hole.
Aligning the semiconductor mask to form a first mask pattern and forming at least a first groove or a first hole by etching; and forming a first film on the semiconductor substrate. A step of polishing the first film to planarize it, a step of forming a second film on the semiconductor substrate, a step of forming the alignment groove or the alignment hole,
Aligning the semiconductor mask to form a second mask pattern and etching the second film, wherein the required width and required depth of the alignment groove or the alignment hole. Is a size sufficient to form a recess in the alignment groove or the alignment hole by the step of forming the second film. 2. The step of forming the first groove or the first hole is a step of etching the alignment groove or the alignment hole at the same time as etching the first groove or the first hole. And the required width is greater than twice the sum of the film thicknesses of the first film and the second film, and the required depth is the sum of the film thickness and the first film. The method of manufacturing a semiconductor device according to claim 1, wherein the difference is larger than the difference between the groove and the depth of the first hole. 3. A method of manufacturing a semiconductor device in which a semiconductor element is formed on a semiconductor substrate, wherein an alignment groove having a required width and a required depth for aligning a semiconductor mask is provided on the semiconductor substrate. Alternatively, a step of forming a positioning hole and forming a first groove or a first hole; and a step of forming a first groove or a first hole in the positioning groove or the positioning hole
Aligning the semiconductor mask to form a first mask pattern, and forming at least a second groove or a second hole by etching; and forming a first film on the semiconductor substrate. A step of polishing the first film to planarize it, a step of forming a second film on the semiconductor substrate, a step of forming the alignment groove or the alignment hole,
Aligning the semiconductor mask to form a second mask pattern and etching the second film, wherein the required width and required depth of the alignment groove or the alignment hole. Is a size sufficient to form a recess in the alignment groove or the alignment hole by the step of forming the second film. 4. The step of forming the second groove or the second hole includes etching the alignment groove or the alignment hole at the same time as etching the second groove or the second hole. And the required width is larger than twice the sum of the film thicknesses of the first film and the second film, and the required depth is the sum of the film thickness and the second film. The method of manufacturing a semiconductor device according to claim 3, wherein the difference is larger than the difference between the groove and the depth of the second hole. 5. The second film is a laminated film.
5. The method for manufacturing a semiconductor device according to any one of 4 to 4. 6. A method of manufacturing a semiconductor device, wherein a semiconductor element is formed on a semiconductor substrate, wherein an alignment groove having a required width and a required depth for aligning a semiconductor mask is provided on the semiconductor substrate. Alternatively, a step of forming an alignment hole, a step of forming a film on the semiconductor substrate substrate and polishing and flattening the film, and an alignment of a semiconductor mask with the alignment groove or the alignment hole. Forming a mask pattern and etching the film, wherein the required width and required depth of the alignment groove or the alignment hole are determined by the film formation step. Alternatively, the method of manufacturing a semiconductor device is characterized in that the size is large enough to form a recess in the alignment hole. 7. A method of manufacturing a semiconductor device, wherein a semiconductor element is formed on a semiconductor substrate, wherein a first groove or a first hole is formed on the semiconductor substrate,
A step of embedding and polishing the first film to planarize it, a step of forming a second film on the semiconductor substrate and polishing the second film to planarize it, and a step for aligning the semiconductor mask. A positioning groove or a positioning hole having a width and a required depth is formed by etching the second film or the first film and the second film, and the second film is formed. A step of forming a contact hole by etching, a step of forming a third film and etching to embed the third film in the contact hole, and a step of forming a fourth film on a semiconductor substrate. A step of forming a mask pattern by aligning a semiconductor mask with the alignment groove or the alignment hole, and etching the fourth film to form a wiring, the alignment groove or Position The required width and required depth of the baffle hole are large enough to form a recess in the alignment groove or the alignment hole in the step of forming the fourth film. Of manufacturing a semiconductor device. 8. The required width is greater than twice the sum of the film thicknesses of the third film and the fourth film, and the required depth is greater than the film thickness of the fourth film. Is also large.
The manufacturing method of the semiconductor device described in the above. 9. A method of manufacturing a semiconductor device in which a semiconductor element is formed on a semiconductor substrate, which comprises an alignment groove having a required width and a required depth for aligning a semiconductor mask on the semiconductor substrate. Forming a contact hole and forming a contact hole; forming a first film and etching the first film to fill the contact hole; and forming a second film on the semiconductor substrate. A step of forming a film, and a first step in the alignment groove or the alignment hole.
Aligning the semiconductor mask to form a first mask pattern, etching the second film to form a wiring; forming a third film on a semiconductor substrate; A step of polishing and flattening the film of step 2;
Aligning the semiconductor mask to form a second mask pattern, and etching the third film to form a via hole. The method of manufacturing a semiconductor device, wherein the width and the required depth are large enough to form a recess in the alignment groove or the alignment hole by the step of forming the third film. 10. The required width is greater than twice the sum of the film thicknesses of the first film and the third film, and the required depth is the polishing amount of the third film. The method of manufacturing a semiconductor device according to claim 9, wherein the difference is larger than the difference between the thickness of the wiring and the wiring.